FUNCTIONAL BLOCK DIAGRAM 3 4 5 6 VDD4A VGG1A 2 VDD3A Output power for 1 dB compression (P1dB): 21 dBm typical Saturated output power (PSAT): 22 dBm typical Gain: 19 dB typical Output third-order intercept (IP3): 28 dBm typical Supply voltage: 4 V at 320 mA 50 Ω matched input/output Die size: 2.3 mm × 1.8 mm × 0.05 mm VDD2A FEATURES VDD1A RFOUT 7 HMC1144 APPLICATIONS 11 10 9 VDD4B 8 13143-001 12 VDD3B RFIN VDD1B 1 VGG1B Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military and space Telecommunications infrastructure Fiber optics VDD2B Data Sheet 35 GHz to 70 GHz, GaAs, pHEMT, MMIC, Medium Power Amplifier HMC1144 Figure 1. GENERAL DESCRIPTION The HMC1144 is a gallium arsenide (GaAs), pseudomorphic high electron mobility transfer (pHEMT), monolithic microwave integrated circuit (MMIC), distributed power amplifier that operates from 35 GHz to 70 GHz. In the lower band of 35 GHz to 50 GHz, the HMC1144 provides 19 dB (typical) of gain, 28 dBm output IP3, and 19 dBm and 19.5 dBm, respectively, of output P1dB gain compression. In the upper band of 50 GHz to 70 GHz, the HMC1144 provides 19 dB (typical) of gain, 32 dBm Rev. C output IP3, and 21 dBm of output power at 1 dB gain compression. The HMC1144 requires 320 mA from a 4 V supply. The HMC1144 amplifier inputs/outputs are internally matched to 50 Ω, facilitating integration into multichip modules (MCMs). All data is taken with the chip connected via two 0.025 mm (1 mil) wire bonds of 0.076 mm (3 mil) minimal length. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC1144 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 11 General Description ......................................................................... 1 Applications Information .............................................................. 12 Revision History ............................................................................... 2 Alternate Biasing Configuration .............................................. 12 Electrical Specifications ................................................................... 3 35 GHz to 40 GHz Frequency Range......................................... 3 Mounting and Bonding Techniques for Millimeterwave GaAs MMICs ......................................................................................... 13 40 GHz to 50 GHz Frequency Range......................................... 3 Typical Application Circuit ........................................................... 14 50 GHz to 70 GHz Frequency Range......................................... 4 Assembly Diagram ..................................................................... 15 Absolute Maximum Ratings............................................................ 5 Outline Dimensions ....................................................................... 16 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 16 Pin Configuration and Function Descriptions ............................. 6 REVISION HISTORY 7/2017—Rev. B to Rev. C Changes to Title and General Description Section ...................... 1 Added Table 1; Renumbered Sequentially .................................... 3 Changes to Figure 10 to Figure 15 .................................................. 7 Changes to Figure 16 to Figure 21 .................................................. 8 Changes to Figure 22 to Figure 27 .................................................. 9 Added Figure 28; Renumbered Sequentially .............................. 10 Changes to Figure 32 ...................................................................... 10 10/2016—Rev. A to Rev. B Change to Features Section ............................................................. 1 Changes to Mounting and Bonding Techniques for Millimeterwave GaAs MMICs Section, Figure 35, and Figure 36 ................................................................................... 12 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 1/2016—Rev. 0 to Rev. A Changes to Table 3 ............................................................................ 4 Added Figure 28 to Figure 32; Renumbered Sequentially .......... 8 10/2015—Revision 0: Initial Version Rev. C | Page 2 of 16 Data Sheet HMC1144 ELECTRICAL SPECIFICATIONS 35 GHz TO 40 GHz FREQUENCY RANGE TA = 25°C, VDD = VDD1A = VDD2A = VDD3A = VDD4A = 4 V, IDD = IDD1A + IDD2A + IDD3A + IDD4A = 320 mA, unless otherwise stated. Adjust VGG1B from −2 V to 0 V to achieve IDD = 320 mA typical. Table 1. Parameter FREQUENCY RANGE GAIN Gain Variation Over Temperature RETURN LOSS Input Output OUTPUT Output Power for 1 dB Compression Saturated Output Power Output Third-Order Intercept SUPPLY CURRENT Total Supply Current Total Supply Current vs. VDD IDD = 290 mA IDD = 320 mA IDD = 350 mA Symbol P1dB PSAT IP3 Test Conditions/Comments Min 35 Measurement taken at POUT/tone = 10 dBm IDD Typ Max 40 19 0.022 Unit GHz dB dB/°C 33 16 dB dB 19 21 28 dBm dBm dBm 320 mA 4 4 4 V V V 40 GHz TO 50 GHz FREQUENCY RANGE TA = 25°C, VDD = VDD1A = VDD2A = VDD3A = VDD4A = 4 V, IDD = IDD1A + IDD2A + IDD3A + IDD4A = 320 mA, unless otherwise stated. Adjust VGG1B from −2 V to 0 V to achieve IDD = 320 mA typical. Table 2. Parameter FREQUENCY RANGE GAIN Gain Variation Over Temperature RETURN LOSS Input Output OUTPUT Output Power for 1 dB Compression Saturated Output Power Output Third-Order Intercept SUPPLY CURRENT Total Supply Current Total Supply Current vs. VDD IDD = 290 mA IDD = 320 mA IDD = 350 mA Symbol P1dB PSAT IP3 Test Conditions/Comments Min 40 17 17 Measurement taken at POUT/tone = 10 dBm IDD Rev. C | Page 3 of 16 Typ Max 50 19 0.023 Unit GHz dB dB/°C 35 16 dB dB 19.5 21.5 28 dBm dBm dBm 320 mA 4 4 4 V V V HMC1144 Data Sheet 50 GHz TO 70 GHz FREQUENCY RANGE TA = 25°C, VDD = VDD1A = VDD2A = VDD3A = VDD4A = 4 V, IDD = IDD1A + IDD2A + IDD3A + IDD4A = 320 mA, unless otherwise stated. Adjust VGG1B from −2 V to 0 V to achieve IDD = 320 mA typical. Table 3. Parameter FREQUENCY RANGE GAIN Gain Variation Over Temperature RETURN LOSS Input Output OUTPUT Output Power for 1 dB Compression Saturated Output Power Output Third-Order Intercept SUPPLY CURRENT Total Supply Current Total Supply Current vs. VDD IDD = 290 mA IDD = 320 mA IDD = 350 mA Symbol P1dB PSAT IP3 Test Conditions/Comments Min 50 17 19 Measurement taken at POUT/tone = 10 dBm IDD Rev. C | Page 4 of 16 Typ Max 70 19 0.016 Unit GHz dB dB/°C 22 25 dB dB 21 22 32 dBm dBm dBm 320 mA 4 4 4 V V V Data Sheet HMC1144 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Drain Bias Voltage (VDD1A to VDD4A) Gate Bias Voltage (VGG1B) RF Input Power (RFIN) Channel Temperature Continuous Power Dissipation (PDISS), TA = 85°C (Derate 19.2 mW/°C Above 85°C) Thermal Resistance, θJA (Channel to Bottom Die) Storage Temperature Range Operating Temperature Range ESD Sensitivity, Human Body Model (HBM) Rating 4.5 V −2 V to 0 V dc 22 dBm 175°C 1.770 W Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 50.83°C/W ESD CAUTION −65°C to +150°C −55°C to +85°C ±125 V, Class 0B Rev. C | Page 5 of 16 HMC1144 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VGG1A 2 VDD1A VDD2A 3 4 VDD3A 5 VDD4A 6 7 RFOUT HMC1144 TOP VIEW (Not to Scale) RFIN 12 VGG1B 11 10 VDD1B VDD2B 9 VDD3B 8 VDD4B 13143-002 1 Figure 2. Pad Configuration Table 5. Pad Function Descriptions Pad No. 1 2 3 to 6 Mnemonic RFIN VGG1A VDD1A to VDD4A 7 8 to 11 RFOUT VDD4B to VDD1B 12 VGG1B Die Bottom GND Description RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. Gate Control Pad for Alternate Bias Configuration. See Figure 4 for the interface schematic.. Drain Bias Voltage Pads for the Amplifier. External bypass capacitors of 100 pF and 0.1 µF are required. See Figure 5 for the interface schematic. RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. Drain Bias Voltage Pads for Alternate Bias Configuration. External bypass capacitors of 100 pF and 0.1 µF are required for decoupling. See Figure 7 for the interface schematic. Gate Control Pad for the Amplifier. External bypass capacitors of 100 pF and 0.1 µF are required. See Figure 8 for the interface schematic. Die bottom must be connected to RF/dc ground. See Figure 9 for the interface schematic. 13143-003 INTERFACE SCHEMATICS Figure 3. RFIN Interface Schematic VGG1B Figure 4. VGG1A Interface Schematic Figure 8. VGG1B Interface Schematic GND 13143-005 VDD1A TO VDD4A Figure 5. VDD1A to VDD4A Interface Schematic Figure 9. GND Interface Schematic 13143-006 RFOUT 13143-108 Figure 7. VDD1B to VDD4B Interface Schematic 13143-004 VGG1A 13143-132 VDD1B TO VDD4B 13143-007 RFIN Figure 6. RFOUT Interface Schematic Rev. C | Page 6 of 16 Data Sheet HMC1144 TYPICAL PERFORMANCE CHARACTERISTICS 25 25 20 15 20 0 –5 S11 S21 S22 –10 –15 15 10 5 –20 35 40 45 50 55 60 65 70 75 FREQUENCY (GHz) 0 30 13143-310 –25 30 2.5V 3.0V 3.5V 4.0V 36 42 48 54 60 66 72 FREQUENCY (GHz) Figure 10. Response Gain and Return Loss vs. Frequency 13143-313 5 GAIN (dB) RESPONSE (dB) 10 Figure 13. Gain vs. Frequency for Various VDD at IDD = 250 mA 0 25 +85°C +25°C –55°C –5 RETURN LOSS (dB) GAIN (dB) 20 15 10 –10 –15 –20 5 36 42 48 54 60 66 72 FREQUENCY (GHz) –25 30 13143-311 0 30 36 42 48 54 60 66 72 FREQUENCY (GHz) Figure 11. Gain vs. Frequency at Various Temperatures 13143-314 +85°C +25°C –55°C Figure 14. Input Return Loss vs. Frequency at Various Temperatures 25 0 200mA 250mA 320mA RETURN LOSS (dB) –5 15 10 150mA 200mA 250mA 290mA 320mA 350mA 0 30 36 42 48 54 60 66 FREQUENCY (GHz) –10 –15 –20 72 Figure 12. Gain vs. Frequency for Various IDD at VDD = 4 V –25 30 36 42 48 54 FREQUENCY (GHz) 60 66 72 13143-315 5 13143-312 GAIN (dB) 20 Figure 15. Input Return Loss vs. Frequency for Various IDD at VDD = 4 V Rev. C | Page 7 of 16 HMC1144 Data Sheet 0 –10 –15 –10 –15 42 48 54 60 66 72 FREQUENCY (GHz) –25 30 13143-316 36 Figure 16. Input Return Loss vs. Frequency for Various VDD at IDD = 250 mA 36 42 48 54 60 66 72 FREQUENCY (GHz) 13143-319 –20 –20 –25 30 2.5V 3.0V 3.5V 4.0V –5 RETURN LOSS (dB) RETURN LOSS (dB) –5 0 2.5V 3.0V 3.5V 4.0V Figure 19. Output Return Loss vs. Frequency for Various VDD at IDD = 250 mA 0 0 +85°C +25°C –55°C +85°C +25°C –55°C –10 REVERSE ISOLATION (dB) RETURN LOSS (dB) –5 –10 –15 –20 –30 –40 –50 –60 –20 36 42 48 54 60 66 72 FREQUENCY (GHz) –80 30 13143-317 –25 30 42 48 54 60 66 72 FREQUENCY (GHz) Figure 20. Reverse Isolation vs. Frequency at Various Temperatures Figure 17. Output Return Loss vs. Frequency at Various Temperatures 24 0 200mA 250mA 320mA 20 –5 16 P1dB (dBm) –10 –15 12 8 –20 36 42 48 54 FREQUENCY (GHz) 60 66 72 13143-318 –25 30 4 Figure 18. Output Return Loss vs. Frequency for Various IDD at VDD = 4 V Rev. C | Page 8 of 16 +85°C +25°C –55°C 0 30 36 42 48 54 60 66 FREQUENCY (GHz) Figure 21. P1dB vs. Frequency at Various Temperatures 72 13143-321 RETURN LOSS (dB) 36 13143-320 –70 Data Sheet HMC1144 40 20 35 16 30 IP3 (dBm) 12 +85°C +25°C –55°C 25 20 8 4 15 290mA 320mA 350mA 42 48 54 60 66 72 FREQUENCY (GHz) 10 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 36 13143-322 0 30 FREQUENCY (GHz) 13143-325 P1dB (dBm) 24 Figure 25. Output IP3 vs. Frequency for Various Temperatures at POUT = 10 dBm/Tone Figure 22. P1dB vs. Frequency for Various IDD at VDD = 4 V 40 24 20 35 16 30 IP3 (dBm) 12 25 20 8 4 15 +85°C +25°C –55°C 42 48 54 60 66 72 FREQUENCY (GHz) 10 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 36 13143-323 0 30 FREQUENCY (GHz) Figure 23. PSAT vs. Frequency at Various Temperatures 13143-326 PSAT (dBm) 290mA 320mA 350mA Figure 26. Output IP3 vs. Frequency for Various IDD at POUT = 10 dBm/tone 24 55 20 50 45 40 35 30GHz 35GHz 40GHz 45GHz 50GHz 55GHz 60GHz 65GHz 70GHz 8 30 4 290mA 320mA 350mA 0 30 36 25 42 48 54 60 66 FREQUENCY (GHz) Figure 24. PSAT vs. Frequency for Various IDD at VDD = 4 V 72 20 6 8 10 POUT /TONE (dBm) 12 14 13143-327 IM3 (dBc) 12 13143-324 PSAT (dBm) 16 Figure 27. Output Third-Order Intermodulation (IMD3) vs. POUT/Tone for Various Frequencies at VDD = 4 V, IDD = 320 mA Rev. C | Page 9 of 16 470 15 420 10 370 5 320 0 –10 IDD (mA) 20 270 –8 –6 –4 –2 0 2 4 6 25 520 20 470 15 420 10 370 5 GAIN 320 POUT PAE IDD 270 4 6 13143-328 8 INPUT POWER (dBm) 0 –10 Figure 28. POUT, Gain, PAE, and IDD vs. Input Power at 35 GHz 2 65GHz 55GHz 45GHz 35GHz 470 1.6 370 5 GAIN 320 POUT PAE IDD 270 6 8 PDISS (W) 10 1.5 IDD (mA) 420 15 1.4 1.3 1.2 7 13143-332 6 5 3 4 1 2 0 –2 –1 –4 INPUT POWER (dBm) Figure 32. Power Dissipation (PDISS) vs. Input Power at 85°C for Various Frequencies Figure 29. POUT, Gain, PAE, and IDD vs. Input Power at 45 GHz 25 –3 1.0 –6 4 –5 –4 –2 0 2 INPUT POWER (dBm) –7 –6 –9 –8 –10 0 –10 1.1 13143-201 POUT (dBm), GAIN (dB), PAE (%) –4 –2 0 INPUT POWER (dBm) 1.8 1.7 20 –6 Figure 31. POUT, Gain, PAE, and IDD vs. Input Power at 65 GHz 520 25 –8 –8 POUT (dBm), GAIN (dB), PAE (%) POUT GAIN PAE IDD POUT (dBm), GAIN (dB), PAE (%) 520 25 IDD (mA) Data Sheet 13143-203 HMC1144 10 520 420 10 370 5 0 –10 –8 –6 –4 –2 0 INPUT POWER (dBm) 2 GAIN 320 POUT PAE IDD 270 4 6 7 6 5 4 3 2 1 25°C 0 50 55 60 65 FREQUENCY (GHz) 70 Figure 33. Noise Figure vs. Frequency at 25°C Figure 30. POUT, Gain, PAE, and IDD vs. Input Power at 55 GHz Rev. C | Page 10 of 16 75 13143-205 15 8 NOISE FIGURE (dB) 470 IDD (mA) 20 13143-202 POUT (dBm), GAIN (dB), PAE (%) 9 Data Sheet HMC1144 THEORY OF OPERATION The architecture of the HMC1144 power amplifier is shown in Figure 34. The HMC1144 uses two cascaded, four-stage amplifiers operating in quadrature between two 90° hybrids. This balanced amplifier approach forms an amplifier with a combined gain of 19 dB and a saturated output power (PSAT) of 22 dBm. The 90° hybrids ensure that the input and output return losses are greater than 15 dB. See the application circuits shown in Figure 38 and Figure 39 for further details on biasing the various blocks. RFOUT 13143-028 RFIN Figure 34. HMC1144 Architecture Rev. C | Page 11 of 16 HMC1144 Data Sheet APPLICATIONS INFORMATION The VDD = 4 V and IDD = 320 mA bias conditions are the operating points recommended to optimize the overall performance. Unless otherwise noted, the data shown was taken using the recommended bias condition. Operation of the HMC1144 at different bias conditions may provide performance that differs from what is shown in the Typical Performance Characteristics section. Biasing the HMC1144 for higher drain current typically results in higher P1dB, output IP3, and gain, but at the expense of increased power consumption. The HMC1144 is a GaAs, pHEMT, MMIC power amplifier. Capacitive bypassing is required for VDD1A through VDD4A and VDD1B through VDD4B (see Figure 38). VGG1B is the gate bias pad for all four gain stages. Apply a gate bias voltage to VGG1B and use capacitive bypassing as shown in Figure 38. All measurements for this device were taken using the typical application circuit (see Figure 38) and configured as shown in the assembly diagram (see Figure 40). The following is the recommended bias sequence during power-up: 1. 2. 3. 4. 5. ALTERNATE BIASING CONFIGURATION It is possible to bias the gate from the north (instead of the south) and bias the drain from the south (instead of the north). Although this alternate bias configuration was not measured during production testing and was evaluated minimally during product validation, it does offer flexibility in cases where it is more convenient to have the gate and drain bias approach the die from a different direction (see Figure 39). Connect to ground. Set the gate bias voltage to −2 V. Set all the drain bias voltages, VDD = 4 V. Increase the gate bias voltage to achieve a quiescent current, IDD = 320 mA. Apply the RF signal. The following is the recommended bias sequence during power-down: 3. 4. Turn off the RF signal. Decrease the gate bias voltage to −2 V to achieve IDD = 0 mA (approximately). Decrease all of the drain bias voltages to 0 V. Increase the gate bias voltage to 0 V. VDD1A VDD2A VDD1B VDD3A VDD2B VDD4A VDD3B VDD4B RFIN RFOUT 1A 1B 2A 2B 3A 3B 4A 4B 13143-021 1. 2. In the alternate bias configuration, capacitive bypassing is required for the VGG1A pad to which the bias voltage is applied, as well as for all eight VDDxA/VDDxB pads. VGG1A VGG1B Figure 35. Simplified Block Diagram Rev. C | Page 12 of 16 Data Sheet HMC1144 Handling Precautions MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Attach the die directly to the ground plane eutectically or with conductive epoxy (see the Handling Precautions section, the Mounting section, and the Wire Bonding section). Microstrip, 50 Ω, transmission lines on 0.127 mm (5 mil) thick alumina, thin film substrates are recommended for bringing the radio frequency to and from the chip (see Figure 36). When using 0.254 mm (10 mil) thick alumina, thin film substrates, raise the die 0.150 mm (6 mil) to ensure that the surface of the die is coplanar with the surface of the substrate. One way to accomplish this is to attach the 0.05 mm (2 mil) thick die to a 0.150 mm (6 mil) thick, molybdenum (Mo) heat spreader (moly tab), which can then be attached to the ground plane (see Figure 37). To avoid permanent damage, follow these storage, cleanliness, static sensitivity, transient, and general handling precautions: • • • • • 0.05mm (0.002") THICK GaAs MMIC WIRE BOND 0.076mm (0.003") Place all bare die in either waffle or gel-based ESD protective containers and then seal the die in an ESD protective bag for shipment. After the sealed ESD protective bag is opened, store all die in a dry nitrogen environment. Handle the chips in a clean environment. Do not attempt to clean the chip using liquid cleaning systems. Follow ESD precautions to protect against ESD strikes. While bias is applied, suppress instrument and bias supply transients. Use shielded signal and bias cables to minimize inductive pickup. Handle the chip along the edges with a vacuum collet or with a sharp pair of bent tweezers. The surface of the chip may have fragile air bridges and must not be touched with vacuum collet, tweezers, or fingers. Mounting The chip is back metallized and can be die mounted with gold (Au) and tin (Sn) eutectic preforms or with electrically conductive epoxy. Ensure that the mounting surface is clean and flat. 0.127mm (0.005") THICK ALUMINA THIN FILM SUBSTRATE 13143-030 RF GROUND PLANE When a eutectic die is attached, an 80% gold/20% tin preform is recommended with a work surface temperature of 255°C and a tool temperature of 265°C. When hot 90% nitrogen/10% hydrogen gas is applied, ensure that the tool tip temperature is 290°C. Do not expose the chip to a temperature greater than 320°C for more than 20 sec. For attachment, no more than 3 sec of scrubbing is required. Figure 36. Routing RF Signals 0.05mm (0.002") THICK GaAs MMIC WIRE BOND 0.076mm (0.003") When an epoxy die is attached, apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip after it is placed into position. Cure the epoxy per the schedule of the manufacturer. RF GROUND PLANE Wire Bonding 13143-031 0.150mm (0.005") THICK MOLY TAB 0.254mm (0.010") THICK ALUMINA THIN FILM SUBSTRATE Figure 37. Routing RF Signals Using Moly Tab Place microstrip substrates as close to the die as possible to minimize bond wire length. Typical die to substrate spacing is 0.076 mm to 0.152 mm (3 mil to 6 mil). RF bonds made with two 1 mil wires are recommended. Ensure that these bonds are thermosonically bonded with a force of 40 g to 60 g. DC bonds of 0.001˝ (0.025 mm) in diameter, thermosonically bonded, are recommended. Create ball bonds with a force of 40 g to 50 g and wedge bonds with a force of 18 g to 22 g. Create all bonds with a nominal stage temperature of 150°C. Apply a minimum amount of ultrasonic energy to achieve reliable bonds. Keep all bonds as short as possible, less than 12 mil (0.31 mm). Rev. C | Page 13 of 16 HMC1144 Data Sheet TYPICAL APPLICATION CIRCUIT VDD 0.1µF 0.1µF 100pF 100pF 100pF 100pF 3 4 5 6 RFIN 1 RFOUT 7 8 9 10 11 12 100pF 100pF 100pF 100pF VGG1B 100pF 0.1µF 0.1µF THESE CAPACITORS ARE FOR DECOUPLING ONLY. NO DC BIAS APPLIED. 13143-023 0.1µF Figure 38. Typical Application Circuit THESE CAPACITORS ARE FOR DECOUPLING ONLY. NO DC BIAS APPLIED. 0.1µF 0.1µF VGG1A 0.1µF 100pF 100pF 100pF 100pF 100pF 2 3 4 5 6 RFIN 1 8 7 RFOUT 9 10 11 100pF 100pF 100pF 100pF 0.1µF Figure 39. Alternate Bias Application Circuit Rev. C | Page 14 of 16 0.1µF 13143-130 VDD1 TO VDD4A Data Sheet HMC1144 ASSEMBLY DIAGRAM TO VDD SUPPLY 0.1µF 0.1µF ALL BOND WIRES ARE 1mil DIAMETER 100pF 100pF 100pF 100pF 3mil NOMINAL GAP 50Ω TRANSMISSION LINE 0.1µF 100pF 100pF 0.1µF TO VGG1B SUPPLY Figure 40. Assembly Diagram Rev. C | Page 15 of 16 100pF 100pF 0.1µF 13143-024 100pF HMC1144 Data Sheet OUTLINE DIMENSIONS 2.300 0.206 0.203 0.201 3 2 0.201 0.199 0.200 0.199 0.051 6 5 4 0.093 0.200 0.400 0.130 0.888 7 0.130 0.130 1.800 1 0.902 0.130 0.447 12 11 10 0.102 9 8 SIDE VIEW TOP VIEW 0.093 0.206 0.203 0.201 0.199 0.201 0.199 0.200 0.400 0.200 0.043 09-28-2016-A (CIRCUIT SIDE) Figure 41. 12-Pad Bare Die [CHIP] (C-12-2) Dimensions shown in millimeters ORDERING GUIDE Model HMC1144 HMC1144-SX Temperature Range −55°C to +85°C −55°C to +85°C Package Description 12-Pad Bare Die [CHIP] 12-Pad Bare Die [CHIP] ©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13143-0-7/17(C) Rev. C | Page 16 of 16 Package Option C-12-2 C-12-2