DAC7624 DAC7625 ® DAC 762 4 DAC 762 5 12-Bit Quad Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● LOW POWER: 20mW The DAC7624 and DAC7625 are 12-bit quad voltage output digital-to-analog converters with guaranteed 12bit monotonic performance over the specified temperature range. They accept 12-bit parallel input data, have double-buffered DAC input logic (allowing simultaneous update of all DACs), and provide a readback mode of the internal input registers. An asynchronous reset clears all registers to a mid-scale code of 800H (DAC7624) or to a zero-scale of 000H (DAC7625). The DAC7624 and DAC7625 can operate from a single +5V supply or from +5V and –5V supplies. Low power and small size per DAC make the DAC7624 and DAC7625 ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closed-loop servo-control. The DAC7624 and DAC7625 are available in a 28-pin plastic doublewide or a 28-lead SOIC package, and offer guaranteed specifications over the –40°C to +85°C temperature range. ● UNIPOLAR OR BIPOLAR OPERATION ● SETTLING TIME: 10µs to 0.012% ● 12-BIT LINEARITY AND MONOTONICITY: –40°C to +85°C ● RESET TO MID-SCALE (DAC7624) OR ZERO-SCALE (DAC7625) ● DATA READBACK ● DOUBLE-BUFFERED DATA INPUTS APPLICATIONS ● PROCESS CONTROL ● ATE PIN ELECTRONICS ● CLOSED-LOOP SERVO-CONTROL ● MOTOR CONTROL ● DATA ACQUISITION SYSTEMS ● DAC-PER-PIN PROGRAMMERS VDD GND 12 DB0-DB11 I/O Buffer A0 A1 R/W CS Control Logic VREFH Input Register A DAC Register A DAC A VOUTA Input Register B DAC Register B DAC B VOUTB Input Register C DAC Register C DAC C VOUTC Input Register D DAC Register D DAC D VOUTD RESET LDAC VREFL VSS International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1997 Burr-Brown Corporation SBAS083 PDS-1419C 1 Printed in U.S.A. April, 2000 DAC7624/7625 SPECIFICATION At TA = –40°C to +85°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, unless otherwise noted. DAC7624P, U DAC7625P, U PARAMETER CONDITIONS ACCURACY Linearity Error(1) Linearity Matching(3) Differential Linearity Error Monotonicity Zero-Scale Error Zero-Scale Drift Zero-Scale Matching(3) Full-Scale Error Full-Scale Matching(3) Zero-Scale Error Zero-Scale Drift Zero-Scale Matching(3) Full-Scale Error Full-Scale Matching(3) Power Supply Rejection VSS = 0V or –5V VSS = 0V or –5V VSS = 0V or –5V TMIN to TMAX Code = 000H TYP MAX MIN Code = 00AH, VSS = 0V VSS = 0V VSS = 0V Code = FFFH, VSS = 0V VSS = 0V 5 ±4 5 ±2 ±4 ±2 ±8 10 ±4 ±8 ±4 ✻ ✻ 0 VREFL –1.25 VREFH VREFH +1.25 No Oscillation REFERENCE INPUT VREFH Input Range VREFL Input Range VREFL Input Range VSS = 0V or –5V VSS = 0V VSS = –5V DYNAMIC PERFORMANCE Settling Time(5) Channel-to-Channel Crosstalk Output Noise Voltage DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL VOH VOL Data Format IIH ≤ ±10µA IIL ≤ ±10µA IOH = –0.8mA I OL = 1.6mA POWER SUPPLY REQUIREMENTS VDD VSS IDD ISS Power Dissipation If VSS ≠ 0V VREFL +1.25 0 –2.5 ✻ ✻ ✻ ✻ ✻ 10 40 ✻ TTL-Compatible CMOS ✻ 2.4 –0.3 3.6 0.0 VDD +0.3 0.8 VDD 0.4 Straight Binary 4.75 –5.25 VSS = –5V VSS = 0V –40 ±1 ±1 ±1 LSB(2) LSB LSB Bits LSB ppm/°C LSB LS LSB LSB ppm/°C LSB LSB LSB ppm/V 1.5 –1.6 15 7.5 ✻ ✻ ±1 ✻ ±1 ✻ ✻ ±2 ✻ ±2 ✻ ✻ ✻ V V mA pF mA ✻ ✻ ✻ V V V ✻ µs LSB ✻ ✻ ✻ +2.5 VREFH –1.25 VREFH –1.25 5 0.25 –2.1 DAC7624P, U, PB, UB DAC7625P, U, PB, UB ✻ ✻ ✻ 100 +5, –120 Momentary To ±0.012% Full-Scale Step On any other DAC 0Hz to 1MHz UNITS ✻ 30 Output Current Load Capacitance Short-Circuit Current Short-Circuit Duration MAX ✻ 12 Code = FFFH VREFL = 0V, VSS = 0V VSS = –5V TYP ±2 ±2 ±1 2 ANALOG OUTPUT Voltage Output(4) TEMPERATURE RANGE Specified Performance MIN DAC7624PB, UB DAC7625PB, UB 5.25 –4.75 1.9 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V V V ✻ ✻ ✻ ✻ ✻ V V mA mA mW mW ✻ °C ✻ ✻ ✻ ✻ 20 10 +85 nV/√Hz ✻ ✻ ✻ ✻ ✻ NOTES: (1) If VSS = 0V, specification applies at code 00AH and above. (2) LSB means Least Significant Bit, when V REFH equals +2.5V and VREFL equals –2.5V, then one LSB equals 1.22mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error. (5) If VSS = –5V, full-scale 5V step. If VSS = 0V, full-scale positive 2.5V step and negative step from code FFFH to 00AH. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC7624/7625 2 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) VDD to VSS ............................................................................. –0.3V to 11V VDD to GND .......................................................................... –0.3V to 5.5V VREFL to VSS .............................................................. –0.3V to (VDD – VSS) VDD to VREFH ............................................................. –0.3V to (VDD – VSS) VREFH to VREFL .......................................................... –0.3V to (VDD – VSS) Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION MAXIMUM LINEARITY ERROR (LSB) MAXIMUM DIFFERENTIAL LINEARITY ERROR (LSB) SPECIFICATION TEMPERATURE RANGE PACKAGE PACKAGE DRAWING NUMBER(1) DAC7624P DAC7624U DAC7624PB DAC7624UB ±2 ±2 ±1 ±1 ±1 ±1 ±1 ±1 –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 28-Pin Plastic DIP 28-Lead SOIC 28-Pin Plastic DIP 28-Lead SOIC 215 217 215 217 DAC7625P DAC7625U DAC7625PB DAC7625UB ±2 ±2 ±1 ±1 ±1 ±1 ±1 ±1 –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 28-Pin Plastic DIP 28-Lead SOIC 28-Pin Plastic DIP 28-Lead SOIC 215 217 215 217 PRODUCT NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® 3 DAC7624/7625 PIN CONFIGURATIONS Top View DIP SOIC VREFH 1 28 VREFL VREFH 1 28 VREFL VOUTB 2 27 VOUTC VOUTB 2 27 VOUTC VOUTA 3 26 VOUTD VOUTA 3 26 VOUTD VSS 4 25 VDD VSS 4 25 VDD GND 5 24 NIC GND 5 24 NIC RESET 6 23 CS RESET 6 23 CS LDAC 7 22 A0 LDAC 7 22 A0 (LSB) DB0 8 21 A1 (LSB) DB0 8 21 A1 DB1 9 20 R/W DB1 9 20 R/W DB2 10 19 DB11 (MSB) DB2 10 19 DB11 (MSB) DB3 11 18 DB10 DB3 11 18 DB10 DB4 12 17 DB9 DB4 12 17 DB9 DB5 13 16 DB8 DB5 13 16 DB8 DB6 14 15 DB7 DB6 14 15 DB7 DAC7624 DAC7625 DAC7624 DAC7625 PIN DESCRIPTIONS PIN NAME DESCRIPTION 1 VREFH Reference Input Voltage High. Sets maximum output voltage for all DACs. 2 VOUTB DAC B Voltage Output. 3 VOUTA DAC A Voltage Output. 4 VSS 5 GND 6 RESET 7 LDAC 8 DB0 9 DB1 Data Bit 1 10 DB2 Data Bit 2 11 DB3 Data Bit 3 12 DB4 Data Bit 4 13 DB5 Data Bit 5 14 DB6 Data Bit 6 15 DB7 Data Bit 7 16 DB8 Data Bit 8 17 DB9 Data Bit 9 18 DB10 Data Bit 10 19 DB11 Data Bit 11. Most significant bit of 12-bit word. 20 R/W Read/Write Control Input (read = HIGH, write = LOW). 21 A1 Register/DAC Select (C or D = HIGH, A or B = LOW). 22 A0 Register/DAC Select (B or D = HIGH, A or C = LOW). 23 CS Chip Select Input. 24 NIC Not Internally Connected. Pin has no internal connection to the device. 25 VDD Positive Analog Supply Voltage, +5V nominal. 26 VOUTD DAC D Voltage Output. 27 VOUTC DAC C Voltage Output. 28 VREFL Reference Input Voltage Low. Sets minimum output voltage for all DACs. Negative Analog Supply Voltage, 0V or –5V. Ground. Asynchronous Reset Input. Sets DAC and input registers to either mid-scale (800H, DAC7624) or zero-scale (000H, DAC7625) when LOW. Load DAC Input. All DAC Registers are transparent when LOW. Data Bit 0. Least significant bit of 12-bit word. ® DAC7624/7625 4 TYPICAL PERFORMANCE CURVES: VSS = 0V At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. 0.50 0.25 0.25 LE (LSB) 0.50 0.00 –0.25 –0.50 0.50 0.50 0.25 0.00 –0.25 200H 400H 600H 800H A00H C00H 0.25 0.00 –0.25 –0.50 000H E00H FFFH 600H 800H A00H C00H E00H FFFH LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D) 0.25 LE (LSB) 0.50 0.25 0.00 –0.25 0.00 –0.25 –0.50 –0.50 0.50 0.50 0.25 0.00 –0.25 200H 400H 600H 800H A00H C00H 0.25 0.00 –0.25 –0.50 000H E00H FFFH 400H 600H 800H A00H C00H Digital Input Code LINEARITY ERROR vs CODE (DAC A, –40°C and +85°C) LINEARITY ERROR vs CODE (DAC B, –40°C and +85°C) 0.50 0.25 0.25 LE (LSB) 0.50 0.00 –0.25 E00H FFFH 0.00 –0.25 +85°C –0.50 0.50 0.50 0.25 0.25 LE (LSB) –0.50 0.00 –0.25 –40°C –0.50 000H 200H 200H Digital Input Code +85°C LE (LSB) 400H Digital Input Code 0.50 –0.50 000H 200H Digital Input Code DLE (LSB) LE (LSB) DLE (LSB) 0.00 –0.25 –0.50 –0.50 000H LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B) DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A) 400H 600H 800H A00H C00H 0.00 –0.25 –40°C –0.50 000H 200H E00H FFFH Digital Input Code 400H 600H 800H A00H C00H E00H FFFH Digital Input Code ® 5 DAC7624/7625 TYPICAL PERFORMANCE CURVES: VSS = 0V (CONT) At TA = +25°C, VDD = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. LINEARITY ERROR vs CODE (DAC D, –40°C and +85°C) 0.50 0.50 0.25 0.25 LE (LSB) LE (LSB) LINEARITY ERROR vs CODE (DAC C, –40°C and +85°C) 0.00 –0.25 0.00 –0.25 +85°C 0.50 0.50 0.25 0.25 LE (LSB) –0.50 0.00 –0.25 –40°C –0.50 000H 200H 6 400H 600H 800H A00H C00H 0.00 –0.25 –40°C –0.50 000H 200H E00H FFFH 400H 600H 800H A00H C00H E00H FFFH Digital Input Code Digital Input Code ZERO-SCALE ERROR vs TEMPERATURE (Code 010H) FULL-SCALE ERROR vs TEMPERATURE (Code FFFH) 6 5 5 4 Full-Scale Error (LSB) Zero-Scale Error (LSB) LE (LSB) +85°C –0.50 DAC D 3 DAC B 2 DAC A DAC C 1 0 –1 4 DAC D DAC B 3 DAC A 2 1 DAC C 0 –1 –2 –2 –40 –20 0 20 40 60 80 100 –40 Temperature (°C) 0 20 40 Temperature (°C) ® DAC7624/7625 –20 6 60 80 100 TYPICAL PERFORMANCE CURVES: VSS = –5V At TA = +25°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. 0.50 0.25 0.25 LE (LSB) 0.50 0.00 –0.25 –0.50 0.50 0.50 0.25 0.00 –0.25 200H 400H 600H 800H A00H C00H 0.25 0.00 –0.25 –0.50 000H E00H FFFH 600H 800H A00H C00H E00H FFFH LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D) 0.25 LE (LSB) 0.50 0.25 0.00 –0.25 0.00 –0.25 –0.50 –0.50 0.50 0.50 0.25 0.00 –0.25 200H 400H 600H 800H A00H C00H 0.25 0.00 –0.25 –0.50 000H E00H FFFH 400H 600H 800H A00H C00H Digital Input Code LINEARITY ERROR vs CODE (DAC A, –40°C and +85°C) LINEARITY ERROR vs CODE (DAC B, –40°C and +85°C) 0.50 0.25 0.25 LE (LSB) 0.50 0.00 –0.25 E00H FFFH 0.00 –0.25 +85°C –0.50 0.50 0.50 0.25 0.25 LE (LSB) –0.50 0.00 –0.25 –40°C –0.50 000H 200H 200H Digital Input Code +85°C LE (LSB) 400H Digital Input Code 0.50 –0.50 000H 200H Digital Input Code DLE (LSB) LE (LSB) DLE (LSB) 0.00 –0.25 –0.50 –0.50 000H LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B) DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A) 400H 600H 800H A00H C00H 0.00 –0.25 –40°C –0.50 000H 200H E00H FFFH Digital Input Code 400H 600H 800H A00H C00H E00H FFFH Digital Input Code ® 7 DAC7624/7625 TYPICAL PERFORMANCE CURVES: VSS = –5V (CONT) At TA = +25°C, VDD = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. LINEARITY ERROR vs CODE (DAC D, –40°C and +85°C) 0.50 0.50 0.25 0.25 LE (LSB) LE (LSB) LINEARITY ERROR vs CODE (DAC C, –40°C and +85°C) 0.00 –0.25 0.00 –0.25 +85°C 0.50 0.50 0.25 0.25 LE (LSB) –0.50 0.00 –0.25 Zero-Scale Error (LSB) –40°C –0.50 000H 200H 400H 600H 800H A00H C00H 0.00 –0.25 –40°C –0.50 000H 200H E00H FFFH 800H A00H C00H E00H FFFH ZERO-SCALE ERROR vs TEMPERATURE (Code 000H) FULL-SCALE ERROR vs TEMPERATURE (Code FFFH) 3.0 2.5 2.5 2.0 DAC D 1.5 DAC B DAC A DAC C 0.5 600H Digital Input Code 3.0 1.0 400H Digital Input Code Full-Scale Error (LSB) LE (LSB) +85°C –0.50 0.0 –0.5 2.0 DAC D 1.5 DAC B DAC A 1.0 DAC C 0.5 0.0 –0.5 –1.0 –1.0 –40 –20 0 20 40 60 80 100 –40 Temperature (°C) 0 20 40 Temperature (°C) ® DAC7624/7625 –20 8 60 80 100 THEORY OF OPERATION are set by the external voltage references (VREFL and VREFH, respectively). The digital input is a 12-bit parallel word and the DAC input registers offer a readback capability. The converters can be powered from a single +5V supply or a dual ±5V supply. Each device offers a reset function which immediately sets all DAC output voltages and DAC registers to mid-scale (DAC7624, code 800H) or to zero-scale (DAC7625, code 000H). See Figures 1 and 2 for the basic operation of the DAC7624/25. The DAC7624 and DAC7625 are quad, voltage output, 12-bit digital-to-analog converters (DACs). The architecture is a classic R-2R ladder configuration followed by an operational amplifier that serves as a buffer. Each DAC has its own R-2R ladder network and output op-amp, but all share the reference voltage inputs. The minimum voltage output (“zero-scale”) and maximum voltage output (“full-scale”) DAC7624 DAC7625 +2.500V 0.1µF 1 VREFH VREFL 28 0V to +2.5V 2 VOUTB VOUTC 27 0V to +2.5V 0V to +2.5V 3 VOUTA VOUTD 26 0V to +2.5V 4 VSS VDD 25 5 GND NIC 24 Reset DACs(1) 6 RESET CS 23 Load DAC Registers 7 LDAC A0 22 8 DB0 A1 21 9 DB1 R/W 20 10 DB2 DB11 19 0.1µF Data Bus 11 DB3 DB10 18 12 DB4 DB9 17 13 DB5 DB8 16 14 DB6 DB7 15 +5V 1µF to 10µF + Chip Select Address Bus or Decoder Read/Write Data Bus NOTE: (1) Reset LOW sets all DACs to code 800H on the DAC7624 and to code 000H on the DAC7625. FIGURE 1. Basic Single-Supply Operation of the DAC7624/25. DAC7624 DAC7625 +2.500V –2.500V 0.1µF –5V + 0.1µF 1 VREFH VREFL 28 –2.5V to +2.5V 2 VOUTB VOUTC 27 –2.5V to +2.5V –2.5V to +2.5V 3 VOUTA VOUTD 26 –2.5V to +2.5V 4 VSS VDD 25 5 GND NIC 24 Reset DACs(1) 6 RESET CS 23 Load DAC Registers 7 LDAC A0 22 8 DB0 A1 21 9 DB1 R/W 20 10 DB2 DB11 19 11 DB3 DB10 18 12 DB4 DB9 17 13 DB5 DB8 16 14 DB6 DB7 15 1µF to 10µF 0.1µF Data Bus 0.1µF 1µF to 10µF +5V + Chip Select Address Bus or Decoder Read/Write Data Bus NOTE: (1) Reset LOW sets all DACs to code 800H on the DAC7624 and to code 000H on the DAC7625. FIGURE 2. Basic Dual-Supply Operation of the DAC7624/25. ® 9 DAC7624/7625 ANALOG OUTPUTS The current into the VREFH input depends on the DAC output voltages and can vary from a few microamps to approximately 0.5 milliamp. The VREFH source will not be required to sink current, only source it. Bypassing the reference voltage or voltages with at least a 0.1uF capacitor placed as close to the DAC7624/25 package is strongly recommended. When VSS = –5V (dual supply operation), the output amplifier can swing to within 2.25V of the supply rails, guaranteed over the –40°C to +85°C temperature range. With VSS = 0V (single-supply operation), the output can swing to ground. Note that the settling time of the output op-amp will be longer with voltages very near ground. Also, care must be taken when measuring the zero-scale error when VSS = 0V. Since the output voltage cannot swing below ground, the output voltage may not change for the first few digital input codes (000H, 001H, 002H, etc.) if the output amplifier has a negative offset. DIGITAL INTERFACE Table I shows the basic control logic for the DAC7624/25. Note that each internal register is level triggered and not edge triggered. When the appropriate signal is LOW, the register becomes transparent. When this signal is returned HIGH, the digital word currently in the register is latched. The first set of registers (the Input Registers) are triggered via the A0, A1, R/W, and CS inputs. Only one of these registers is transparent at any given time. The second set of registers (the DAC Registers) are all transparent when LDAC input is pulled LOW. The behavior of the output amplifier can be critical in some applications. Under short circuit conditions (DAC output shorted to ground), the output amplifier can sink a great deal more current than it can source. See the specification table for more details concerning short circuit current. REFERENCE INPUTS Each DAC can be updated independently by writing to the appropriate Input Register and then updating the DAC Register. Alternatively, the entire DAC Register set can be configured as always transparent by keeping LDAC LOW— the DAC update will occur when the Input Register is written. The reference inputs, VREFL and VREFH, can be any voltage between VSS+2.25V and VDD–2.25V provided that VREFH is at least 1.25V greater than VREFL. The minimum output of each DAC is equal to VREFL plus a small offset voltage (essentially, the offset of the output op-amp). The maximum output is equal to VREFH plus a similar offset voltage. Note that VSS (the negative power supply) must either be connected to ground or must be in the range of –4.75V to –5.25V. The voltage on VSS sets several bias points within the converter, if VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not guaranteed. The double buffered architecture is mainly designed so that each DAC Input Register can be written at any time and then all DAC voltages updated simultaneously by pulling LDAC LOW. It also allows a DAC Input Register to be written to at any point and the DAC voltage to be synchronously changed via a trigger signal connected to LDAC. A1 A0 R/W CS RESET LDAC SELECTED INPUT REGISTER L(1) L H H L L H H L L H H X(3) X X L H L H L H L H L H L H X X X L L L L L L L L H H H H X X X L L L L L L L L L L L L H H X H(2) H H H H H H H H H H H H H L L L L L H H H H H H H H L H X A B C D A B C D A B C D NONE NONE ALL STATE OF SELECTED INPUT REGISTER STATE OF ALL DAC REGISTERS Transparent Transparent Transparent Transparent Transparent Transparent Transparent Transparent Readback Readback Readback Readback (All Latched) (All Latched) Reset(4) Transparent Transparent Transparent Transparent Latched Latched Latched Latched Latched Latched Latched Latched Transparent Latched Reset(4) NOTES: (1) L = Logic LOW. (2) H= Logic HIGH. (3) X = Don’t Care. (4) DAC7624 resets to 800H, DAC7625 resets to 000H. When RESET rises, all registers that are in their latched state retain the reset value. TABLE I. DAC7624 and DAC7625 Control Logic Truth Table. ® DAC7624/7625 10 DIGITAL TIMING DIGITAL INPUT CODING Figure 3 and Table II provide detailed timing for the digital interface of the DAC7624 and DAC7625. The DAC7624 and DAC7625 input data is in straight binary format. The output voltage is given by the following equation: – V REFL ) • N (V V OUT = V REFL + REFH 4096 where N is the digital input code. This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. tWCS CS tWH tAS tAH tLS tLH R/W tRCS CS tRDH tRDS tWS A0/A1 R/W tAH tAS LDAC A0/A1 tDH tDS tDZ Data Out tLWD Data In Data Valid tRESET tCSD RESET Digital Input Timing Data Output Timing FIGURE 3. Digital Input and Output Timing. SYMBOL DESCRIPTION MIN tRCS tRDS tRDH tDZ tCSD tWCS tWS tWH tAS t AH tLS t LH t DS tDH tLWD CS LOW for Read R/W HIGH to CS LOW R/W HIGH after CS HIGH CS HIGH to Data Bus in High Impedance CS LOW to Data Bus Valid CS LOW for Write R/W LOW to CS LOW R/W LOW after CS HIGH Address Valid to CS LOW Address Valid after CS HIGH LDAC LOW to CS LOW LDAC LOW after CS HIGH Data Valid to CS LOW Data Valid after CS HIGH LDAC LOW RESET LOW 200 10 0 tRESET TYP 100 100 MAX 160 50 0 0 0 0 70 50 0 0 50 50 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TABLE II. Timing Specifications (TA = –40°C to +85°C). ® 11 DAC7624/7625 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DAC7624U ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7624U DAC7624U/1K ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7624U DAC7624U/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7624U DAC7624UB ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7624U B DAC7624UB/1K ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7624U B DAC7624UBG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7624U B DAC7624UG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7624U DAC7625U ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7625U DAC7625U/1K ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7625U DAC7625U/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7625U DAC7625UB ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7625U B DAC7625UB/1K ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7625U B DAC7625UBG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7625U B DAC7625UG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 DAC7625U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2015 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC7624U/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 DAC7624UB/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 DAC7625U/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 DAC7625UB/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC7624U/1K SOIC DW 28 1000 367.0 367.0 55.0 DAC7624UB/1K SOIC DW 28 1000 367.0 367.0 55.0 DAC7625U/1K SOIC DW 28 1000 367.0 367.0 55.0 DAC7625UB/1K SOIC DW 28 1000 367.0 367.0 55.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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