Holtek HT82B40A I/o 8-bit mcu with usb interface Datasheet

HT82B40R/HT82B40A
I/O 8-Bit MCU with USB Interface
Features
· Operating voltage:
· Fully integrated 6MHz or 12MHz oscillator
fSYS=6M/12MHz: 3.3V~5.5V
· All I/O pins have wake-up functions
· Low voltage reset function
· Power-down function and wake-up feature reduce
· 34 bidirectional I/O lines (max.)
power consumption
· 8-bit programmable timer/event counter with
· 8-level subroutine nesting
overflow interrupt
· Up to 0.33ms instruction cycle with 12MHz system
· 16-bit programmable timer/event counter with
clock at VDD=5V
overflow interrupt
· Bit manipulation instruction
· Watchdog Timer
· 15-bit table read instruction
· PS2 and USB modes supported
· 63 powerful instructions
· USB 2.0 low speed function
· All instructions in one or two machine cycles
· 3 endpoints supported - endpoint 0 included
· 28/48-pin SSOP, 32-pin QFN and 48-pin LQFP
· 4096´15 program memory
packages
· 160´8 data memory RAM
· Integrated 1.5kW resistor between V33O and
USBPDN pins for USB applications
General Description
The HT82B40R and HT82B40A are 8-bit high performance, RISC architecture microcontroller devices specifically designed for multiple I/O control product
applications.
devices extremely suitable for use in computer peripheral
product applications as well as many other applications
such as industrial control, consumer products, subsystem controllers, etc.
The advantages of low power consumption, I/O flexibility,
timer functions, integrated USB interface, Power Down
and wake-up functions, Watchdog timer etc, make the
The HT82B40A mask version type is fully pin and functionally compatible with the HT82B40R OTP version device.
Rev. 1.70
1
November 5, 2014
HT82B40R/HT82B40A
Block Diagram
W a tc h d o g
T im e r
W a tc h d o g
T im e r O s c illa to r
R e s e t
C ir c u it
8 - b it
R IS C
M C U
C o re
P ro g ra m
M e m o ry
D a ta
M e m o ry
S ta c k
In te rru p t
C o n tr o lle r
L o w
V o lta g e
R e s e t
In te rn a l
O s c illa to r
R C
U S B
8 - b it
T im e r
I/O
P o rts
1 6 - b it
T im e r
V 3 3 O
Pin Assignment
P A
P A
P A
P A
P A
P A
P A 6 /T M R
P A 7 /T M R
P B 6
3
2 6
P B 1
P B 7
4
2 5
P B 0
V D D
5
2 4
P A 7 /T M R 1
V 3 3 O
6
2 3
P A 6 /T M R 0
U S B P D N /D A T A
7
2 2
P A 5
U S B P D P /C L K
8
2 1
P A 4
P E 0
9
2 0
P A 3
P E 1
1 0
1 9
P A 2
V S S
1 1
1 8
P A 1
R E S
1 2
1 7
P A 0
P C 0
1 3
1 6
P C 7
P C 1
1 4
1 5
P C 6
4
4 5
P B 4
N C
5
4 4
P B 3
N C
6
4 3
P B 2
N C
7
4 2
P B 1
N C
8
4 1
P B 0
V D D
9
4 0
P A 7 /T M R 1
V 3 3 O
1 0
3 9
P A 6 /T M R 0
U S B P D N /D A T A
1 1
3 8
P A 5
U S B P D P /C L K
1 2
3 7
P A 4
P E 0
1 3
3 6
P A 3
P E 1
1 4
3 5
P A 2
V S S
1 5
3 4
P A 1
R E S
1 6
3 3
P A 0
P C 0
1 7
3 2
P C 7
P C 1
1 8
3 1
P C 6
P C 2
1 9
3 0
P C 5
P C 3
2 0
2 9
P C 4
P D 0
2 1
2 8
P D 7
P D 1
2 2
2 7
P D 6
P D 2
2 3
2 6
P D 5
P D 3
2 4
2 5
P D 4
5
6
2 1
2 0
1 9
1 8
7
8
9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
1 7
V
V 3
U S B P D N /D A
U S B P D P /C
1
N C
3
N C
5
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
N C
N C
2
N C
4
N C
6
N C
8
3 6
3 5
3 4
3 3
3 2
N C
7
3 1
D D
3 O
T A
L K
9
H T 8 2 B 4 0 R /H T 8 2 B 4 0 A
4 8 L Q F P -A
3 0
2 9
2 8
1 0
2 7
1 1
1 2
2 6
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
2 5
P A 3
P A 2
P A 1
P A 0
P C 7
P C 6
P C 5
P C 4
P D 7
P D 6
P D 5
P D 4
S
3
2
1
0
3
2
1
0
1
2
H T 8 2 B 4 0 R
H T 8 2 B 4 0 A
3 2 Q F N -A
4
0
H T 8 2 B 4 0 R /H T 8 2 B 4 0 A
4 8 S S O P -A
P C 7
P C 6
P C 5
P C 4
P C 3
P C 2
P C 1
P C 0
2 2
S
Rev. 1.70
N C
2 4
2 3
3
P D
P D
P D
P D
P C
P C
P C
P C
R E
V S
P E
P E
H T 8 2 B 4 0 R /H T 8 2 B 4 0 A
2 8 S S O P -A
P B 5
0
P B 2
P B 6
4 6
1
2 7
4 7
3
2
2
2
N C
3
P B 5
N C
4
P B 3
P B 7
2
P A
R E S
P A
V S S
P E 1
P E 0
U S B P D P /C L K
U S B P D N /D A T
V 3 3 O
V D D
2 8
4 8
5
0
1
1
1
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5
1
P A 4
P A 5
6 /T M R 0
7 /T M R 1
P B 0
P B 1
P B 2
P B 3
A
P B 4
P B 5
P B 6
P B 7
P B 4
N C
P B 0
P B 1
P B 2
P B 3
P B 4
P B 5
P B 6
P B 7
November 5, 2014
HT82B40R/HT82B40A
Pin Description
Pin Name
PA0~PA5
PA6/TMR0
PA7/TMR1
I/O
I/O
Options
Description
Bidirectional 8-bit input/output port. Each pin can be configured as a
wake-up input by a configuration option. Software instructions deterPull-high
mine if the pin is a CMOS output or NMOS, PMOS or Schmitt Trigger
Wake-up
input. Configuration options determine if the structures are CMOS,
NMOS/CMOS/PMOS NMOS or PMOS types. Configuration options determine if the pins
have pull-high resistors. TMR0 and TMR1 are pin-shared with PA6
and PA7, respectively.
I/O
Pull-high
Wake-up
Bidirectional 8-bit input/output port. Each nibble can be configured as
a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors. The
power supply of PB0~PB7 can be optioned as VDD or V33O output.
I/O
Pull-high
Wake-up
Bidirectional 8-bit input/output port. Each nibble can be configured as
a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors.
I/O
Pull-high
Wake-up
Bi-directional 8-bit input/output port. Each nibble can be configured
as a wake-up input by a configuration option. Software instructions
determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors.
PE0~PE1
I/O
Pull-high
Wake-up
Bidirectional 2-bit input/output port. Each pin can be configured as a
wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if the pins have pull-high resistors.
USBPDP/CLK
I/O
¾
USBPDP line. USB function is controlled by software control register
USBPDN/DATA
I/O
¾
USBPDN line. USB function is controlled by software control register
RES
I
¾
Schmitt trigger reset input. Active low
VSS
¾
¾
Digital negative power supply, ground
VDD
¾
¾
Digital positive power supply
V33O
O
¾
3.3V regulator output
PB0~PB7
PC0~PC7
PD0~PD7
Note: As the Pin Description table applies to the largest package size not all pin may exist on smaller packages.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.70
3
November 5, 2014
HT82B40R/HT82B40A
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSYS=6MHz or 12MHz
3.3
¾
5.5
V
No load, fSYS=6MHz
¾
6.5
12
mA
No load, fSYS=12MHz
¾
7.5
16
mA
NO load, system USB
suspend, set CLK_adj
[22H] ²*²
¾
¾
400
mA
No load, system HALT,
input/output mode, set
SUSP2 & CLK_adj [22H]
¾
¾
15
mA
0
¾
0.8
V
0
¾
0.3VDDIO
V
0
¾
0.4VDD
V
¾
5
V
¾
VDDIO
V
¾
VDD
V
2.0
2.6
3.2
V
3.0
3.3
3.6
V
VDD
VDD
Operating Voltage
(Integrated oscillator)
¾
IDD
Operating Current
5V
Standby Current
ISTB
5V
Standby Current
(WDT Enabled)
Conditions
Input Low Voltage for PA, PC
VIL
Input Low Voltage for PB
5V
where VDDIO=VDD
or V33O by option for PB
Input Low Voltage for RES pin
Input High Voltage for PA, PC
VIH
Input High Voltage for PB
5V
Input High Voltage for RES pin
2
where VDDIO=VDD
0.8VDDIO
or V33O by option for PB
0.9VDD
¾
VLVR
Low Voltage Reset
5V
VV33O
3.3V Regulator Output for
USB SIE
5V
IV33O=70mA
IOL
Output Sink Current for I/O Pin
5V
VOL=0.4V
2
4
¾
mA
IOH
Output Source Current for I/O Pin
5V
VOH=3.4V
-2
-4
¾
mA
¾
4.7
¾
kW
15
30
45
kW
20
50
70
kW
Pull-high Resistance for CLK,
DATA
RPH
Pull-high Resistance for PB
¾
5V
Pull-high Resistance for PA, PC,
PD and PE0~PE1
Note: ²*² include 15kW loading on the USBPDP, USBPDN lines at the host terminal.
Rev. 1.70
4
November 5, 2014
HT82B40R/HT82B40A
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
fRCSYS
RC Clock with 8-bit Prescaler Register
5V
¾
¾
32
¾
kHz
tWDT
Watchdog Time-out Period
(System Clock)
¾
¾
1024
¾
¾
1/fRCSYS
tUSB
USBPDP, USBPDN Rising & Falling Time
¾
¾
75
¾
300
ns
Oscillation Start-up Timer Period
¾
¾
¾
1024
¾
tSYS
tOST
tOSCsetup Crystal Setup
¾
¾
¾
5
¾
ms
¾
10.80
12.00
13.20
MHz
fINO125V
Internal Oscillator Frequency for 12MHz
4.0V~
5.5V
fINO123V
Internal Oscillator Frequency for 12MHz
3.0~
4.0V
¾
10.56
12.00
13.44
MHz
fINOUSB
Internal Oscillator Frequency with USB
Mode
4.2~
5.5V
¾
11.82
12.00
12.18
MHz
Note:
tSYS=1/fSYS
Power_on period = tWDT + tOST + tOSCsetup
WDT Time_out in Normal Mode = 1/ fRCSYS ´ 256 ´ WDTS + tWDT
WDT Time_out in Power Down Mode = 1/ fRCSYS ´ 256 ´ WDTS + tOST + tOSCsetup
Trimmed for 5V operation using factory trim values. Frequency Trim to 12MHz ±3%
Power-on Reset Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RRVDD
VDD raising rate to Ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
tPOR
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
¾
¾
1
¾
¾
ms
V
D D
tP
O R
R R
V D D
V
P O R
T im e
Rev. 1.70
5
November 5, 2014
HT82B40R/HT82B40A
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O and A/D control system with maximum reliability and flexibility.
functions. In this way, one T1~T4 clock cycle forms one
instruction cycle. Although the fetching and execution of
instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one
instruction cycle. The exception to this are instructions
where the contents of the Program Counter are
changed, such as subroutine calls or jumps, in which
case the instruction will take one more instruction cycle
to execute.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. It must be
noted that only the lower 8 bits, known as the Program
Counter Low Register, are directly addressable by user.
Clocking and Pipelining
The system clock is derived from an internal oscillator
and is subdivided into four internally generated
non-overlapping clocks, T1~T4. The Program Counter
is incremented at the beginning of the T1 clock during
which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
4
:
5
:
6
1
D E L A Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.70
6
November 5, 2014
HT82B40R/HT82B40A
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writeable register.
By transferring data directly into this register, a short program jump can be executed directly, however, as only
this low byte is available for manipulation, the jumps are
limited to the present page of memory, that is 256 locations. When such program jumps are executed it should
also be noted that a dummy cycle will be inserted.
P ro g ra m
S ta c k L e v e l 1
T o p o f S ta c k
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
P ro g ra m
M e m o ry
S ta c k L e v e l 3
o f S ta c k
S ta c k L e v e l 8
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has 8 levels and is neither part of the data nor part
of the program space, and is neither readable nor
writeable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writeable. At a
subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program
Counter is restored to its previous value from the stack.
After a device reset, the Stack Pointer will point to the
top of the stack.
Mode
C o u n te r
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
· Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
Program Counter Bits
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
USB Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
@3
@2
@1
@0
Skip
Program Counter + 2
Loading PCL
PC11 PC10 PC9
PC8
@7
@6
@5
@4
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
PC11~PC8: Current Program Counter bits
#11~#0: Instruction code address bits
Rev. 1.70
@7~@0: PCL bits
S11~S0: Stack register bits
7
November 5, 2014
HT82B40R/HT82B40A
0 0 0 H
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
0 0 4 H
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
0 0 8 H
SIZA, SDZA, CALL, RET, RETI
0 0 C H
Program Memory
The Program Memory is the location where the user code
or program is stored. The HT82B40R is a One-Time Programmable, OTP, memory type device where users can
program their application code into the device. By using
the appropriate programming tools, OTP devices offer
users the flexibility to freely develop their applications
which may be useful during debug or for products requiring frequent upgrades or program changes. OTP devices
are also applicable for use in applications that require low
or medium volume production runs. The HT82B40A is a
Mask memory type device and offers the most cost effective solution for high volume products.
In itia lis a tio n
V e c to r
U S B
In te rru p t V e c to r
T im e r /E v e n t 0 C o u n te r
In te rru p t V e c to r
T im e r /E v e n t 1 C o u n te r
In te rru p t V e c to r
F F F H
1 5 b its
Program Memory Structure
· Location 00CH
This area is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program
jumps to this location and begins execution.
· Table location
Any location in the program memory can be used as
look-up tables. There are three methods to read the
Program Memory data using two table read instructions: ²TABRDC² and ²TABRDL², transfer the contents of the lower-order byte to the specified data
memory, and the higher-order byte to TBLH (08H).
The three methods are shown as follows:
Structure
The Program Memory has a capacity of 4K by 15 bits.
The Program Memory is addressed by the Program
Counter and also contains data, table information and
interrupt entries. Table data, which can be setup in any
location within the Program Memory, is addressed by
separate table pointer registers.
¨
Using the instruction ²TABRDC [m]² for the current
Program Memory page, where one page=
256words, where the table location is defined by
TBLP in the current page. This is where the configuration option has disabled the TBHP register.
¨
Using the instruction ²TABRDC [m]², where the table location is defined by registers TBLP and TBHP.
Here the configuration option has enabled the
TBHP register.
¨
Using the instruction ²TABRDL [m]², where the table location is defined by registers TBLP in the last
page which has the address range 0F00H~0FFFH.
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
· Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
· Location 004H
This area is reserved for the USB interrupt service
program. If the USB interrupt is activated, the interrupt
is enabled and the stack is not full, the program jumps
to this location and begins execution.
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, and the remaining 1-bit words are read as ²0². The Table
Higher-order byte register (TBLH) is read only. The table pointers, TBLP and TBHP, are read/write registers, which indicate the table location. Before
accessing the the table, the locations must be placed
· Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program
jumps to this location and begins execution.
Table Location Bits
Instruction
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m]
PC11
PC10
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
PC11~PC8: Current Program Counter bits
TBHP register Bit 3 ~ Bit 0 when TBHP is enabled.
@7~@0: Table Pointer TBLP bits
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HT82B40R/HT82B40A
in the TBLP and TBHP registers (if the configuration
option has disabled TBHP then the value in TBHP has
no effect). TBLH is read only and cannot be restored.
If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR
and errors can occur. Using the table read instruction
in the main routine and the ISR simultaneously should
be avoided. However, if the table read instruction has
to be applied in both the main routine and the ISR, the
interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has
been backed up. All table related instructions require
two cycles to complete the operation. These areas
may function as normal program memory depending
on the requirements.
Once TBHP is enabled, the instruction ²TABRDC [m]²
reads the Program Memory data as defined by the
TBLP and TBHP values. If the Program Memory code
option has disabled TBHP, the instruction ²TABRDC
[m]² reads the Program Memory data as defined by
TBLP only in the current Program Memory page.
After setting up the table pointers, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
Table Program Example
The following example shows how the table pointer and
table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is
²F00H² which refers to the start address of the last page
within the 4K Program Memory of device. The table
pointer is setup here to have an initial value of ²06H².
This will ensure that the first data read from the data table will be at the Program Memory address ²F06H² or 6
locations after the start of the last page. Note that the
value for the table pointer is referenced to the first address of the present page if the ²TABRDC [m]² instruction is being used. The high byte of the table data which
in this case is equal to zero will be transferred to the
TBLH register automatically when the ²TABRDL [m]² instruction is executed.
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the TBLP register and the
higher order address in the TBHP register. These two
registers define the full address of the look-up table.
Using the TBHP must be selected by configuration option, if not used table data can still be accessed but only
the lower byte address in the current page or last page
can be defined.
P ro g ra m C o u n te r
H ig h B y te
T B H P
P ro g ra m
M e m o ry
T B L P
T B L H
T a b le C o n te n ts H ig h B y te
T B L H
S p e c ifie d b y [m ]
T a b le C o n te n ts L o w
H ig h B y te o f T a b le C o n te n ts
B y te
S p e c ifie d b y [m ]
L o w
B y te o f T a b le C o n te n ts
Table Read - TBLP/TBHP
Table Read - TBLP only
Rev. 1.70
P ro g ra m
M e m o ry
T B L P
9
November 5, 2014
HT82B40R/HT82B40A
tempreg1 db
tempreg2 db
:
:
?
?
; temporary register #1
; temporary register #2
mov a,06h
; initialise table pointer - note that this address is referenced
mov tblp,a
:
:
; to the last page or present page
tabrdl
; transfers value in table referenced by table pointer to tempregl
; data at prog. memory address ²F06H² transferred to tempreg1 and TBLH
tempreg1
dec tblp
tabrdl
; reduce value of table pointer by one
tempreg2
:
:
org F00h
dc
;
;
;
;
;
transfers value in table referenced by table pointer to tempreg2
data at prog.memory address ²F05H² transferred to tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
the value ²00H² will be transferred to the high byte register TBLH
; sets initial address of last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use the table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
mon to all microcontrollers, such as ACC, PCL, etc.,
have the same Data Memory address.
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user program for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions, individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
Data Memory
0 0 H
S p e c
P u rp o
D a
M e m o
The Data Memory is a volatile area of 8-bit wide RAM
internal memory and is the location where temporary information is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some remain
protected from user manipulation. The second area of
Data Memory is reserved for general purpose use. All
locations within this area are read and write accessible
under program control.
3 F H
4 0 H
G e n e ra l
P u rp o s e
D a ta
M e m o ry
D F H
Data Memory Structure
Note:
Structure
The two sections of Data Memory, the Special Purpose
and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are
8 bits wide. The start address of the Data Memory for all
devices is the address ²00H². Registers which are comRev. 1.70
ia l
s e
ta
ry
10
Most of the Data Memory bits can be directly
manipulated using the ²SET [m].i² and ²CLR
[m].i² with the exception of a few dedicated bits.
The Data Memory can also be accessed
through the memory pointer register MP.
November 5, 2014
HT82B40R/HT82B40A
Special Purpose Data Memory
Special Function Registers
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. It is divided into two banks, Bank 0 and Bank1.
Most of the registers are both readable and writeable
but some are protected and are readable only, the details of which are located under the relevant Special
Function Register section. Note that for locations that
are unused, any read instruction to these addresses will
return the value ²00H².
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control. The
location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the
point where the General Purpose Memory begins is reserved and attempting to read data from these locations
will return a value of 00H.
The Special Purpose Registers for the USB interface
are stored in Bank 1 which can only be accessed by first
setting the Bank Pointer to a value of 01H and then using Indirect Addressing Register IAR1 and Memory
Pointer MP1. Bank 1 can only be accessed indirectly using the MP1 Memory Pointer, direct addressing is not
possible.
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
B a
IA
M
IA
M
n k 0
R 0
P 0
R 1
P 1
B P
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C
4 0 H
4 1 H
4 2 H
4 3 H
4 4 H
4 5 H
4 6 H
4 7 H
4 8 H
4 9 H
4 A H
Indirect Addressing Register - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together only access data from
Bank 0, while the IAR1 and MP1 register pair can access data from both Bank 0 and Bank 1. As the Indirect
Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will
return a result of ²00H² and writing to the registers indirectly will result in no operation.
B a n k 1
U S B _ S T A T
P IP E _ C T R L
A W R
S T A L L
P IP E
S IE S
M IS C
E N D P T _ E N
F IF O 0
F IF O 1
F IF O 2
T M R 0
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
P A
P A C
P B
P B C
P C
P C C
P D
P D C
P E
P E C
T B
U
U
S
H P
S C
S R
C C
Memory Pointer - MP0, MP1
For all devices, two Memory Pointers, known as MP0
and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be
manipulated in the same way as normal registers providing a convenient way with which to address and track
data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that
the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0 can only access data in Bank 0 while MP1 can access both banks.
: U n u s e d re a d a s "0 "
Special Purpose Data Memory
Rev. 1.70
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November 5, 2014
HT82B40R/HT82B40A
data .section ¢data¢
adres1
db ?
adres2
db ?
adres3
db ?
adres4
db ?
block
db ?
code .section at 0 ¢code¢
org 00h
start:
mov
mov
mov
mov
a,04h
block,a
a,offset adres1
mp0,a
; setup size of block
loop:
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
continue:
The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses.
Accumulator - ACC
data pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table read
data instruction has been executed.
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
Watchdog Timer Register - WDTS
The Watchdog feature of the microcontroller provides
an automatic reset function giving the microcontroller a
means of protection against spurious jumps to incorrect
Program Memory addresses. To implement this, a timer
is provided within the microcontroller which will issue a
reset command when its value overflows. To provide
variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register.
By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be
setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128.
Program Counter Low Register - PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Look-up Table Registers - TBLP, TBLH, TBHP
These two special function registers are used to control
operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointers and
indicate the location where the table data is located. Their
value must be setup before any table read commands are
executed. Their values can be changed, for example using
the ²INC² or ²DEC² instructions, allowing for easy table
Rev. 1.70
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November 5, 2014
HT82B40R/HT82B40A
b 7
b 0
T O
P D F
O V
Z
A C
C
S T A T U S R e g is te r
A r
C a
A u
Z e
ith m e
r r y fla
x ilia r y
r o fla g
O v e r flo w
g
tic /L o g ic O p e r a tio n F la g s
c a r r y fla g
fla g
S y s te m M
P o w e r d o w
W a tc h d o g
N o t im p le m
a n
n
tim
e
a g e m e n t F la g s
fla g
e - o u t fla g
n te d , re a d a s "0 "
Status Register
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Timer/Event Counter Registers TMR0, TMR0C, TMR1H, TMR1L, TMR1C
· C is set if an operation results in a carry during an ad-
Both devices possess a single internal 8-bit count-up
timer. An associated register known as TMR0 is the location where the timers 8-bit value is located. This register can also be preloaded with fixed data to allow
different time intervals to be setup. An associated control register, known as TMR0C, contains the setup information for this timer, which determines in what mode the
timer is to be used as well as containing the timer on/off
control function.
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
· AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
· Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
All devices possess one internal 16-bit count-up timer.
An associated register pair known as TMR1L/TMR1H is
the location where the timer 16-bit value is located. This
register can also be preloaded with fixed data to allow
different time intervals to be setup. An associated control register, known as TMR1C, contains the setup information for this timer, which determines in what mode the
timer is to be used as well as containing the timer on/off
control function.
· OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
· TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
Input/Output Ports and Control Registers
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the interrupt routine can change the status register, precautions must be
taken to correctly save it.
Within the area of Special Function Registers, the I/O
registers and and their associated control registers play
a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC, PD and
PE0~PE1. These labeled I/O registers are mapped to
specific addresses within the Data Memory as shown in
the Data Memory table, which are used to transfer the
appropriate output or input data on that port. With each
I/O port there is an associated control register labeled
PAC, PBC, PCC, PDC and PEC, also mapped to specific addresses with the Data Memory.
Interrupt Control Registers - INTC
The microcontrollers provide two internal timer/event
counter overflow interrupts and one USB interrupt. By
setting various bits within this register using standard bit
manipulation instructions, the enable/disable function of
each interrupt can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a
global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and
is set by executing the ²RETI² instruction.
Rev. 1.70
The control register specifies which pins of that port are
set as inputs and which are set as outputs. To setup a
pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low.
During program initialisation, it is important to first setup
the control registers to specify which pins are outputs
and which are inputs before reading data from or writing
data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the
13
November 5, 2014
HT82B40R/HT82B40A
²SET [m].i² and ²CLR [m].i² instructions. The ability to
change I/O pins from output to input and vice versa by
manipulating specific bits of the I/O control registers during normal program operation is a useful feature of
these devices.
Port A CMOS/NMOS/PMOS Structure
Bank Pointer - BP
The power supply for the Port B pins can be setup via
configuration option to be either VDD or V33O.
The pins on Port A can be setup via configuration option
to be either CMOS, NMOS or PMOS types.
Port B VDD/V33O Option Structure
The Special Purpose Data Memory is divided into two
Banks, Bank 0 and Bank 1. The USB control registers
are located in Bank 1, while all other registers are located in Bank 1. The Bank Pointer selects which bank
data is to be accessed from. If Bank 0 is to be accessed
then BP must be set to a value of 00H, while if Bank 1 is
to be accessed then BP must be set to a value of 01H.
b 7
b 0
B P 0
Port Pin Wake-up
If the HALT instruction is executed, the device will enter
the Power Down Mode, where the system clock will stop
resulting in power being conserved, a feature that is important for battery and other low-power applications.
Various methods exist to wake-up the microcontroller,
one of which is to change the logic condition on one of
the port pins from high to low. After a HALT instruction
forces the microcontroller into entering the Power Down
Mode, the processor will remain in a low-power state until the logic condition of the selected wake-up pin on the
port pin changes from high to low. This function is especially suitable for applications that can be woken up via
external switches. Each pin on PA, PB, PC, PD and
PE0~PE1 has the capability to wake-up the device on
an external falling edge. Note that some pins can only
be setup nibble wide whereas other can be bit selected
to have a wake-up function.
B a n k P o in te r
B P 0
0
1
D a ta M e m o ry
B a n k 0
B a n k 1
N o t u s e d , m u s t b e re s e t to "0 "
Bank Pointer
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins,
the user is provided with an I/O structure to meet the
needs of a wide range of application possibilities.
I/O Port Control Registers
Each I/O port has its own control register PAC, PBC,
PCC, PDC and PEC, to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be
reconfigured dynamically under software control. Each of
the I/O ports is directly mapped to a bit in its associated
port control register. Note that several pins can be setup
to have NMOS outputs using configuration options.
Depending upon which package is chosen, the
microcontroller provides up to 34 bidirectional input/output lines labeled with port names PA, PB, PC, PD and
PE0~PE1.
These I/O ports are mapped to the Data Memory with
addresses as shown in the Special Purpose Data Memory table. For input operation, these ports are non-latching, which means the inputs must be ready at the T2
rising edge of instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data
is latched and remains unchanged until the output latch
is rewritten.
For the I/O pin to function as an input, the corresponding
bit of the control register must be written as a ²1². This
will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit
of the control register is written as a ²0², the I/O pin will
be setup as an output. If the pin is currently setup as an
output, instructions can still be used to read the output
register. However, it should be noted that the program
will in fact only read the status of the output data latch
and not the actual logic status of the output pin.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, I/O pins, when configured as an input have the
capability of being connected to an internal pull-high resistor. The pull-high resistors are selectable via configuration options and are implemented using weak PMOS
transistors. A pin or nibble option on the I/O ports can be
selected to select pull-high Resistors.
Rev. 1.70
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November 5, 2014
HT82B40R/HT82B40A
Pin-shared Functions
Programming Considerations
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
Within the user program, one of the first things to consider is port initialisation. After a reset, all of the data and
port control register will be set high. This means that all
I/O pins will default to an input state, the level of which
depends on the other connected circuitry and whether
pull-high options have been selected. If the PAC, PBC,
PCC, PDC and PEC port control register, are then programmed to setup some pins as outputs, these output
pins will have an initial high output value unless the associated PA, PB, PC, PD and PE port data registers are
first programmed. Selecting which pins are inputs and
which are outputs can be achieved byte-wide by loading
the correct value into the port control register or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions. Note
that when using these bit control instructions, a
read-modify-write operation takes place. The
microcontroller must first read in the data on the entire
port, modify it to the required new bit values and then rewrite this data back to the output ports.
· External Timer0 Clock Input
The external timer pin TMR0 is pin-shared with the I/O
pin PA6. To configure this pin to operate as timer input,
the corresponding control bits in the timer control register must be correctly set. For applications that do not
require an external timer input, this pin can be used as
a normal I/O pin. Note that if used as a normal I/O pin
the timer mode control bits in the timer control register
must select the timer mode, which has an internal
clock source, to prevent the input pin from interfering
with the timer operation.
· External Timer1 Clock Input
The external timer pin TMR1 is pin-shared with the I/O
pin PA7. To configure this pin to operate as timer input,
the corresponding control bits in the timer control register must be correctly set. For applications that do not
require an external timer input, this pin can be used as
a normal I/O pin. Note that if used as a normal I/O pin
the timer mode control bits in the timer control register
must select the timer mode, which has an internal
clock source, to prevent the input pin from interfering
with the timer operation
T 1
S y s te m
T 2
T 3
W r ite to P o r t
P u ll- H ig h
O p tio n
C o n tr o l B it
Q
W r ite D a ta R e g is te r
S y s te m
R e a d fro m
P o rt
D D
/V 3 3 O
(P B )
W e a k
P u ll- u p
S
I/O
p in
D a ta B it
Q
D
C K
Q
S
R e a d D a ta R e g is te r
T 4
Q
C K
C h ip R e s e t
R e a d C o n tr o l R e g is te r
T 3
All pins have the additional capability of providing
wake-up functions. When the device is in the Power
Down Mode, various methods are available to wake the
device up. One of these is a high to low transition of any
of the Port pins. Single or multiple pins can be setup to
have this function.
V
W r ite C o n tr o l R e g is te r
T 2
Read/Write Timing
The diagram illustrates a generic I/O pin internal structures. As the exact logical construction of the I/O pin will
differ and as the pin-shared structures are not illustrated
this diagram is supplied as a guide only to assist with the
functional understanding of the I/O pins.
D
T 1
P o rt D a ta
I/O Pin Structures
D a ta B u s
T 4
C lo c k
M
U
X
W a k e -u p
W a k e - u p O p tio n
Input/Output Ports
Rev. 1.70
15
November 5, 2014
HT82B40R/HT82B40A
Timer/Event Counters
curs on the external timer pin. The timer will count from
the initial value loaded by the preload register to the full
count of FFH for the 8-bit timer or FFFFH for the 16-bit
timer at which point the timer overflows and an internal
interrupt signal is generated. The timer value will then
be reset with the initial preload register value and continue counting.
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. This device contains two
count-up timers of 8-bit and 16-bit capacities respectively. As each timer has three different operating
modes, they can be configured to operate as a general
timer, an external event counter or as a pulse width
measurement device.
To achieve a maximum full range count of FFH for the
8-bit timer or FFFFH for the 16-bit timer, the preload registers must first be cleared to all zeros. It should be
noted that after power-on, the preload register will be in
an unknown condition. Note that if the Timer/Event
Counter is switched off and data is written to its preload
registers, this data will be immediately written into the
actual timer registers. However, if the Timer/Event
Counter is enabled and counting, any new data written
into the preload data registers during this period will remain in the preload registers and will only be written into
the timer registers the next time an overflow occurs.
There are two types of registers related to the
Timer/Event Counters. The first is the register that contains the actual value of the Timer/Event Counter and
into which an initial value can be preloaded, and is
known as TMR0, TMR1H or TMR1L. Reading from this
register retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer
Control Register, which defines the timer options and
determines how the Timer/Event Counter is to be used,
and has the name TMR0C or TMR1C. This device can
have the timer clocks configured to come from the internal clock sources. In addition, the timer clock source can
also be configured to come from the external timer pins.
For the 16-bit Timer/Event Counter which has both low
byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be note
when using instructions to preload data into the low byte
timer register, namely TMR1L, the data will only be
placed in a low byte buffer and not directly into the low
byte timer register. The actual transfer of the data into
the low byte timer register is only carried out when a
write to its associated high byte timer register, namely
TMR1H, is executed. On the other hand, using instructions to preload data into the high byte timer register will
result in the data being directly written to the high byte
timer register. At the same time the data in the low byte
buffer will be transferred into its associated low byte
timer register. For this reason, the low byte timer register
should be written first when preloading data into the
16-bit timer registers. It must also be noted that to read
the contents of the low byte timer register, a read to the
high byte timer register must be executed first to latch
the contents of the low byte timer register into its associated low byte buffer. After this has been done, the low
byte timer register can be read in the normal way. Note
that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer
and not the actual contents of the low byte timer register.
The external clock source is used when the Timer/Event
Counter is in the event counting mode, the clock source
being provided on the external timer pin. The pin has the
name TMR0 or TMR1 and is pin-shared with an I/O pin.
Depending upon the condition of the T0E or T1E bit in
the Timer Control Register, each high to low, or low to
high transition on the external timer input pin will increment the Timer/Event Counter by one.
Configuring the Timer/Event Counter Input Clock
Source
The Timer/Event Counter¢s clock can originate from various sources. The system clock source is used when the
Timer/Event Counter 0 is in the timer mode or in the
pulse width measurement mode. The instruction clock
source (system clock source divided by 4) is used when
the Timer/Event Counter 1 is in the timer mode or in the
pulse width measurement mode. The external clock
source is used when the Timer/Event Counter is in the
event counting mode, the clock source being provided
on the external timer pin, TMR0 or TMR1. Depending
upon the condition of the T0E or T1E bit, each high to
low, or low to high transition on the external timer pin will
increment the counter by one.
Timer Control Register - TMR0C/TMR1C
Timer Register - TMR0, TMR1L/TMR1H
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their respective control register. For devices are two timer control registers known as TMR0C,
TMR1C . It is the timer control register together with its
corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can
be used, it is essential that the appropriate timer control
The timer registers are special function registers located
in the Special Purpose RAM Data Memory and are the
places where the actual timer values are stored. For
8-bit Timer/Event Counter 0, this register is known as
TMR0. For 16-bit Timer/Event Counter 1, the timer registers are known as TMR1L and TMR1H. The value in
the timer registers increases by one each time an internal clock pulse is received or an external transition ocRev. 1.70
16
November 5, 2014
HT82B40R/HT82B40A
D a ta B u s
P r e lo a d R e g is te r
T 0 M 1
fS
T M R 0
Y S
/4
R e lo a d
T 0 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T 0 E
T im e r /E v e n t
C o u n te r
T 0 O N
O v e r flo w
to In te rru p t
8 - B it T im e r /E v e n t C o u n te r
8-bit Timer/Event Counter 0 Structure
D a ta B u s
L o w B y te
B u ffe r
T 1 M 1
fS
T M R 1
Y S
/4
1 6 - B it
P r e lo a d R e g is te r
T 1 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T 1 E
H ig h B y te
T 1 O N
L o w B y te
1 6 - B it T im e r /E v e n t C o u n te r
R e lo a d
O v e r flo w
to In te rru p t
16-bit Timer/Event Counter 1 Structure
b 7
T 0 M 1
b 0
T 0 M 0
T 0 O N
T 0 E
T M R 0 C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
E v
0
1
P u
0
1
e n t C o u n te r a c tiv e e d g e
: c o u n t o n r is in g e d g e
: c o u n t o n fa llin g e d g e
ls e W id th C a p tu r e a c tiv e
: s ta r t c o u n tin g o n fa llin g
: s ta r t c o u n tin g o n r is in g
s e le c tio n
e d g e s e le c tio n
e d g e , s to p o n r is in g e d g e
e d g e , s to p o n fa llin g e d g e
T im e r /E v e n t C o u n te r 0 C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g M o d e S e le c
T 0 M 0
T 0 M 1
n o
0
0
e v
1
0
tim
0
1
1
1
p u
t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 0 Control Register
b 7
T 1 M 1
b 0
T 1 M 0
T 1 O N
T 1 E
T M R 1 C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
E v e n t C o u n te r a c tiv e e d g e
0 : c o u n t o n r is in g e d g e
1 : c o u n t o n fa llin g e d g e
P u ls e W id th C a p tu r e a c tiv e
0 : s ta r t c o u n tin g o n fa llin g
1 : s ta r t c o u n tin g o n r is in g
s e le c tio n
e d g e s e le c tio n
e d g e , s to p o n r is in g e d g e
e d g e , s to p o n fa llin g e d g e
T im e r /E v e n t C o u n te r 1 c o u n tin g e n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g m o d e s e le c
T 1 M 0
T 1 M 1
n o
0
0
e v
1
0
tim
0
1
1
1
p u
t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 1 Control Register
Rev. 1.70
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November 5, 2014
HT82B40R/HT82B40A
value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in
the Interrupt Control Register, INTC, is reset to zero.
register is fully programmed with the right data to ensure
its correct operation, a process that is normally carried
out during program initialization.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode
or the pulse width measurement mode, bits 7 and 6 of
the Timer Control Register, which are known as the bit
pair T0M1/T0M0 or T1M1/T1M0 respectively, depending upon which timer is used, must be set to the required
logic levels. The timer-on bit, which is bit 4 of the Timer
Control Register and known as T0ON or T1ON, depending upon which timer is used, provides the basic on/off
control of the respective timer. Setting the bit high allows
the counter to run, clearing the bit stops the counter. If
the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control
Register which is known as T0E or T1E, depending
upon which timer is used.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be recorded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair, T0M1/T0M0
or T1M1/T1M0, in the Timer Control Register must be
set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Event Counter Mode
In this mode, the Timer/Event Counter can be utilised to
measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode
Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer
Control Register must be set to the correct value as
shown.
Bit7 Bit6
1
0
1
In this mode, the external timer pin, TMR0 or TMR1, is
used as the Timer/Event Counter clock source, however
it is not divided by the internal prescaler. After the other
bits in the Timer Control Register have been setup, the
enable bit T0ON or T1ON, which is bit 4 of the Timer
Control Register, can be set high to enable the
Timer/Event Counter to run. If the Active Edge Select bit
T0E or T1E, which is bit 3 of the Timer Control Register,
is low, the Timer/Event Counter will increment each time
the external timer pin receives a low to high transition. If
the Active Edge Select bit is high, the counter will increment each time the external timer pin receives a high to
low transition. When it is full and overflows, an interrupt
signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register
and continue counting. The interrupt can be disabled by
ensuring that the Timer/Event Counter Interrupt Enable
bit in the Interrupt Control Register, INTC, is reset to
zero.
Configuring the Timer Mode
Control Register Operating Mode
Select Bits for the Timer Mode
Bit7 Bit6
0
In this mode the internal clock, fSYS/4 is used as the internal clock for the Timer/Event Counters. After the
other bits in the Timer Control Register have been
setup, the enable bit T0ON or T1ON, which is bit 4 of the
Timer Control Register, can be set high to enable the
Timer/Event Counter to run.Each time an internal clock
cycle occurs, the Timer/Event Counter increments by
one. When it is full and overflows, an interrupt signal is
generated and the Timer/Event Counter will reload the
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an event
counter input pin, two things have to happen. The first is
to ensure that the Operating Mode Select bits in the
Timer Control Register place the Timer/Event Counter in
the Event Counting Mode, the second is to ensure that
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
Rev. 1.70
18
November 5, 2014
HT82B40R/HT82B40A
turns to its original low level. As before, the enable bit
will be automatically reset to zero and the Timer/Event
Counter will stop counting. It is important to note that in
the Pulse Width Measurement Mode, the enable bit is
automatically reset to zero when the external control
signal on the external timer pin returns to its original
level, whereas in the other two modes the enable bit can
only be reset to zero under program control.
the port control register configures the pin as an input. It
should be noted that in the event counting mode, even if
the microcontroller is in the Power Down Mode, the
Timer/Event Counter will continue to record externally
changing logic events on the timer input pin. As a result
when the timer overflows it will generate a timer interrupt
and corresponding wake-up source.
Configuring the Pulse Width Measurement Mode
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the external timer
pin. As the enable bit has now been reset, any further
transitions on the external timer pin will be ignored. Not
until the enable bit is again set high by the program can
the timer begin further pulse width measurements. In
this way, single shot pulse measurements can be easily
made.
In this mode, the Timer/Event Counter can be utilised to
measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating
Mode Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the
Timer Control Register must be set to the correct
valueas shown.
Bit7 Bit6
Control Register Operating Mode Select
Bits for the Pulse Width Measurement Mode 1
1
It should be noted that in this mode the Timer/Event
Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the
Timer/Event Counter is full and overflows, an interrupt
signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register
and continue counting. The interrupt can be disabled by
ensuring that the Timer/Event Counter Interrupt Enable
bit in the Interrupt Control Register, INTC, is reset to
zero.
In this mode the internal clock, fSYS/4 is used as the internal clock for the Timer/Event Counters. After the
other bits in the Timer Control Register have been
setup, the enable bit T0ON or T1ON, which is bit 4 of the
Timer Control Register, can be set high to enable the
Timer/Event Counter, however it will not actually start
counting until an active edge is received on the external
timer pin.
If the Active Edge Select bit T0E or T1E, which is bit 3 of
the Timer Control Register, is low, once a high to low
transition has been received on the external timer pin,
TMR0 or TMR1, the Timer/Event Counter will start
counting until the external timer pin returns to its original
high level. At this point the enable bit will be automatically reset to zero and the Timer/Event Counter will stop
counting. If the Active Edge Select bit is high, the
Timer/Event Counter will begin counting once a low to
high transition has been received on the external timer
pin and stop counting when the external timer pin re-
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse
width measurement pin, two things have to happen. The
first is to ensure that the Operating Mode Select bits in
the Timer Control Register place the Timer/Event Counter in the Pulse Width Measurement Mode, the second
is to ensure that the port control register configures the
pin as an input.ot by the logic level.
E x te r n a l T im e r
P in In p u t
T 0 O N o r T 1 O N
( w ith T 0 E o r T 1 E = 0 )
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
+ 1
T im e r
+ 2
+ 3
+ 4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart
Rev. 1.70
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HT82B40R/HT82B40A
I/O Interfacing
associated with the timer will remain inactive. The edge
select, timer mode and clock source control bits in timer
control register must also be correctly set to ensure the
timer is properly configured for the required application.
It is also important to ensure that an initial value is first
loaded into the timer registers before the timer is
switched on; this is because after power-on the initial
values of the timer registers are unknown. After the
timer has been initialised the timer can be turned on and
off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the
timer on, should only be executed after the timer mode
bits have been properly setup. Setting the timer enable
bit high together with a mode bit modification, may lead
to improper timer operation if executed as a single timer
control register byte write instruction.
The Timer/Event Counter, when configured to run in the
event counter or pulse width measurement mode, require the use of the external TMR0 and TMR1 pins for
correct operation. As these pins are shared pins they
must be configured correctly to ensure they are setup
for use as Timer/Event Counter inputs and not as a normal I/O pins. This is implemented by ensuring that the
mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the Port Control Register
bits for these pins must be set high to ensure that the pin
is setup as an input. Any pull-high resistor configuration
option on these pins will remain valid even if the pin is
used as a Timer/Event Counter input.
Programming Considerations
When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control
register will be set. If the timer interrupt is enabled this
will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a
Timer/Event counter overflow will also generate a
wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter
is in the Event Counting Mode and if the external signal
continues to change state. In such a case, the
Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be
woken up from its Power-down condition. To prevent
such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the
²HALT² instruction to enter the Power Down Mode.
When configured to run in the timer mode, the internal
system clock is used as the timer clock source and is
therefore synchronised with the overall operation of the
microcontroller. In this mode when the appropriate timer
register is full, the microcontroller will generate an internal
interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as
the timer clock source but the timer will only run when the
correct logic condition appears on the external timer input
pin. As this is an external event and not synchronised
with the internal timer clock, the microcontroller will only
see this external event when the next timer clock pulse
arrives. As a result, there may be small differences in
measured values requiring programmers to take this into
account during programming. The same applies if the
timer is configured to be in the event counting mode,
which again is an external event and not synchronised
with the internal system or timer clock.
Timer Program Example
This program example shows how the Timer/Event
Counter registers are setup, along with how the interrupts are enabled and managed. Note how the
Timer/Event Counter is turned on, by setting bit 4 of the
Timer Control Register. The Timer/Event Counter can
be turned off in a similar way by clearing the same bit.
This example program sets the Timer/Event Counter to
be in the timer mode, which uses the internal system
clock as the clock source.
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid
errors, however as this may result in a counting error,
this should be taken into account by the programmer.
Care must be taken to ensure that the timers are properly initialised before using them for the first time. The
associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt
Rev. 1.70
20
November 5, 2014
HT82B40R/HT82B40A
org 04h
; USB interrupt vector
reti
org 08h
; Timer/Event Counter interrupt vector
jmp tmr0int
; jump here when Timer0 overflows
:
org 20h
; main program
;internal Timer/Event Counter 0 interrupt routine
Tmr0int:
:
; Timer/Event Counter 0 main program placed here
:
reti
:
:
begin:
;setup Timer registers
mov a,09bh
; setup Timer preload value
mov tmr0,a;
mov a,080h
; setup Timer control register
mov tmr0c,a
; timer mode
; setup interrupt register
mov a,005h
; enable master interrupt and timer interrupt
mov intc,a
set tmr0c.4
; start Timer/Event Counter - note mode bits must be previously setup
Interrupts
this interrupt vector. The instruction at this vector will
usually be a JMP statement which will jump to another
section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be
terminated with a RETI statement, which retrieves the
original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred.
Interrupts are an important part of any microcontroller
system. When an internal function such as a Timer/Event
Counter overflow or a USB interrupt occur, their corresponding interrupt will enforce a temporary suspension of
the main program allowing the microcontroller to direct
attention to their respective needs. while the internal interrupts are controlled by the Timer/Event Counter overflow, USB interrupt or reception.
Interrupt Register
The various interrupt enable bits, together with their associated request flags, are shown in the accompanying
diagram with their order of priority.
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by an interrupt
control register. By controlling the appropriate enable
bits in this register each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the
corresponding request flag will be set by the
microcontroller. The global enable flag if cleared to zero
will disable all interrupts.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Operation
When a USB interrupt occurs or one of the Timer/Event
Counters overflow, if their appropriate interrupt enable
bit is set, the Program Counter, which stores the address of the next instruction to be executed, will be
transferred onto the stack. The Program Counter will
then be loaded with a new address which will be the
value of the corresponding interrupt vector. The
microcontroller will then fetch its next instruction from
Rev. 1.70
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November 5, 2014
HT82B40R/HT82B40A
b 7
b 0
T 1 F
T 0 F
U S B F
E T 1 I
E T 0 I
E U I
E M I
IN T C
R e g is te r
M a s te r in te r r u p t g lo b a l e n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
U S B in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 0 in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 1 in te r r u p t e n a b le
1 : e n a b le
0 : d is a b le
U S B in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 0 in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 1 in te r r u p t r e q u e s t fla g
1 : a c tiv e
0 : in a c tiv e
F o r te s t m o d e u s e d o n ly
M u s t b e w r itte n a s " 0 " ; o th e r w is e m a y r e s u lt in u n p r e d ic ta b le o p e r a tio n
INTC Register
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
P r io r ity
U S B In te rru p t
R e q u e s t F la g U S B F
E U I
T im e r /E v e n t C o u n te r 0 O v e r flo w
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
T im e r /E v e n t C o u n te r 1 O v e r flo w
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
E M I
H ig h
In te rru p t
P o llin g
L o w
Interrupt Structure
Interrupt Priority
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the interrupt
registers can prevent simultaneous occurrences.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
USB Interrupt
1
0004H
Timer/Event Counter 0 Overflow
Interrupt
2
0008H
Timer/Event Counter 1 Overflow
Interrupt
3
000CH
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ET0I/ET1I, must first be set. An actual Timer/Event Counter interrupt will take place when
the Timer/Event Counter interrupt request flag,
T0F/T1F, is set, a situation that will occur when the
Timer/Event Counter overflows. When the interrupt is
enabled, the stack is not full and a Timer/Event Counter
overflow occurs, a subroutine call to the timer interrupt
vector at location 08H/0CH, will take place. When the interrupt is serviced, the timer interrupt request flag,
T0F/T1F, will be automatically reset and the EMI bit will
be automatically cleared to disable other interrupts.
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always
Rev. 1.70
22
November 5, 2014
HT82B40R/HT82B40A
Programming Considerations
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt control register until the corresponding interrupt is serviced or until the request flag is
cleared by a software instruction.
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode.
Only the Program Counter is pushed onto the stack. If
the contents of the accumulator or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents
should be saved in advance.
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
USB Interrupt
The USB interrupts are triggered by the following USB
events causing the related interrupt request flag, USBF,
to be set.
Reset Functions
· Access of the corresponding USB FIFO from PC
· A USB resume signal from the PC
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
· A USB Reset signal
· Power-on Reset
· A USB suspend signal from the PC
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing a
proper reset operation. In such cases it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
When the interrupt is enabled, the stack is not full and
the USB interrupt is active, a subroutine call to location
04H will occur. The interrupt request flag, USBF, and the
EMI bit will be cleared to disable other interrupts.
When the PC Host accesses the FIFO of the device, the
corresponding request bit, USR, is set, and a USB interrupt is triggered. So the user can easy determine which
FIFO has been accessed. When the interrupt has been
served, the corresponding bit should be cleared by firmware. When the device receive a USB Suspend signal
from Host PC, the suspend line (bit0 of USC) is set and a
USB interrupt is also triggered.
Also when device receive a Resume signal from Host
PC, the resume line (bit3 of USC) is set and a USB interrupt is triggered.
Reset and Initialisation
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
Rev. 1.70
23
November 5, 2014
HT82B40R/HT82B40A
V D D
0 .9 V
R E S
tR
· Low Voltage Reset - LVR
D D
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration
option. If the supply voltage of the device drops to
within a range of 0.9V~VLVR such as might occur when
changing the battery, the LVR will automatically reset
the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR
will ignore the low supply voltage and will not perform
a reset function. The actual VLVR value can be selected via configuration options.
S T D
S S T T im e - o u t
In te rn a l R e s e t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
L V R
V D D
tR
1 0 0 k W
S T D
S S T T im e - o u t
R E S
In te rn a l R e s e t
0 .1 m F
V S S
Low Voltage Reset Timing Chart
Basic Reset Circuit
· Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F
W D T T im e - o u t
V D D
tS
1 0 0 k W
R E S
WDT Time-out Reset during Power Down
Timing Chart
1 0 k W
0 .1 m F
· Watchdog Time-out Reset during Power Down
V S S
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
Enhanced Reset Circuit
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
W D T T im e - o u t
· RES Pin Reset
tR
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point. Note that as the external reset pin
is also pin-shared with PA7, if it is to be used as a reset
pin, the correct reset configuration option must be selected.
R E S
S T
S S T T im e - o u t
0 .4 V
0 .9 V
S T D
S S T T im e - o u t
In te rn a l R e s e t
WDT Time-out Reset during Normal Operation
Timing Chart
D D
D D
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
RES Reset Timing Chart
Rev. 1.70
24
November 5, 2014
HT82B40R/HT82B40A
Reset Initial Conditions
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled by
various microcontroller operations, such as the Power
Down function or Watchdog Timer. The reset flags are
shown in the table:
TO PDF
Item
RESET Conditions
0
0
RES reset during power-on
0
0
RES wake-up during Power Down
0
0
RES or LVR reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer/Event
Counter
Timer Counter will be turned off
Prescaler
The Timer Counter Prescaler will
be cleared
Input/Output Ports I/O ports will be setup as inputs
Note: ²u² stands for unchanged
Stack Pointer
Stack Pointer will point to the top
of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller internal registers.
Reset
(Power-on)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
MP0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
MP1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
BP
0000 0000
0000 0000
0000 0000
0000 0000
00u0 00uu
0000 0000
0000 0000
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000H
0000H
0000H
0000H
0000H
0000H
0000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
1000 0111
1000 0111
1000 0111
1000 0111
uuuu uuuu
1000 0111
1000 0111
STATUS
--00 xxxx
--1u uuuu
--00 uuuu
--00 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
TMR0C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
uu-u u---
uu-u u---
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
uu-u u---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
Register
Rev. 1.70
25
USB Reset USB Reset
(Normal)
(HALT)
November 5, 2014
HT82B40R/HT82B40A
Reset
(Power-on)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
USB Reset USB Reset
(Normal)
(HALT)
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PE
---- --11
---- --11
---- --11
---- --11
---- --uu
---- --11
---- --11
PEC
---- --11
---- --11
---- --11
---- --11
---- --uu
---- --11
---- --11
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
USC
1000 0000
uuuu xuux
1000 0000
1000 0000
uuuu xuux
1uuu 0100
1uuu 0100
USR
---- 0000
---- uuuu
---- 0000
---- 0000
---- uuuu
---- 0000
---- 0000
SCC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0uu0 u000
0uu0 u000
USB_STAT
--xx 0000
--xx 0000
--xx 0000
--xx 0000
--xx 0000
--xx 0000
--xx 0000
PIPE_CTRL
0000 0110
uuuu uuuu
0000 0110
0000 0110
uuuu uuuu
0000 0110
0000 0110
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
---- 0000
---- uuuu
---- 0000
---- 0000
---- uuuu
---- 0000
---- 0000
PIPE
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
SIES
00-0 0000
uu-x xuuu
00-0 0000
00-0 0000
uu-x xuuu
00-0 0000
00-0 0000
MISC
0x00 0000
uuuu uuuu
0x00 0000
0x00 0000
uuuu uuuu
0x00 0000
0x00 0000
ENDPT_EN
0000 0111
uuuu uuuu
0000 0111
0000 0111
uuuu uuuu
0000 0111
0000 0111
FIFO0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
FIFO1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
FIFO2
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Register
STALL
Note:
²*² means ²warm reset²
²-² not implemented
²u² means ²unchanged²
²x² means ²unknown²
Oscillator
The clock source for these devices is provided by an integrated oscillator requiring no external components.
This oscillator has two fixed frequencies of either 6MHz,
or 12MHz, the selection of which is made by the
SYSCLK bit in the SCC register.
Rev. 1.70
Watchdog Timer Oscillator
The WDT oscillator is a fully self-contained free running
on-chip RC oscillator with a typical period of 32ms at 5V
requiring no external components. When the device enters the Power Down Mode, the system clock will stop
running but the WDT oscillator continues to free-run and
to keep the watchdog active. However, to preserve
power in certain applications the WDT oscillator can be
disabled via a configuration option.
26
November 5, 2014
HT82B40R/HT82B40A
Power Down Mode and Wake-up
If the configuration options have enabled the Watchdog
Timer internal oscillator then this will continue to run
when in the Power Down Mode and will thus consume
some power. For power sensitive applications it may be
therefore preferable to use the system clock source for
the Watchdog Timer.
Power Down Mode
All of the Holtek microcontrollers have the ability to enter
a Power Down Mode. When the device enters this mode,
the normal operating current, will be reduced to an extremely low standby current level. This occurs because
when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device
maintains its present internal condition, it can be woken
up at a later stage and continue running, without requiring
a full reset. This feature is extremely important in application areas where the microcontroller must have its power
supply constantly maintained to keep the device in a
known condition but where the power supply capacity is
limited such as in battery applications.
Wake-up
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
· An external reset
· An external falling edge on Port
· A system interrupt
· A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Entering the Power Down Mode
There is only one way for the device to enter the Power
Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is
executed, the following will occur:
· The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
· The Data Memory contents and registers will maintain
their present condition.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
or RTC oscillator. The WDT will stop if its clock source
originates from the system clock.
Each pin can be setup via an individual configuration option to permit a negative transition on the pin to wake-up
the system. When a pin wake-up occurs, the program
will resume execution at the instruction following the
²HALT² instruction.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the microcontroller
to as low a value as possible, perhaps only in the order
of several micro-amps, there are other considerations
which must also be taken into account by the circuit designer if the power consumption is to be minimised.
Special attention must be made to the I/O pins on the
device. All high-impedance input pins must be connected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. Care must also be
taken with the loads, which are connected to I/O pins,
which are setup as outputs. These should be placed in a
condition in which minimum current is drawn or connected only to external circuits that do not draw current,
such as other CMOS inputs.
Rev. 1.70
27
November 5, 2014
HT82B40R/HT82B40A
Once the internal WDT oscillator (RC oscillator normally
with a period of 32ms) is selected, it is first divided by 256
(8-stages) to get the nominal time-out period of approximately 8.19ms. This time-out period may vary with temperature, VDD and process variations. By using the
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bit 2, 1, 0 of the
WDTS) can give different time-out periods. If WS2,
WS1, WS0 are all equal to ²1², the division ratio is up to
1:128, and the maximum time-out period is 1.048s.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal system operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
If the WDT oscillator is disabled, the WDT clock source
may still come from the instruction clock and operate in
the same manner except that in the Power down Mode
state the WDT may stop counting and lose its protecting
purpose. In this situation the WDT logic can be restarted
by external logic. The high nibble and bit 3 of the WDTS
are reserved for user defined flags, which can be used
to indicate some specified status.
Watchdog Timer
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), enabled using a configuration
option. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location
with unpredictable results. If the Watchdog Timer is disabled, all the executions related to the WDT results in no
operation.
C L R
W D T 1 F la g
C L R
W D T 2 F la g
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS
Y S
/4
W D T O s c illa to r
C L R
W D T C lo c k S o u r c e
C o n fig u r a tio n O p tio n
C L R
8 - b it C o u n te r
(
¸
7 - b it P r e s c a le r
2 5 6 )
W D T C lo c k S o u r c e
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Bit No.
Label
Function
0
1
2
WS0
WS1
WS2
Watchdog Timer division ratio selection bits
Bit 2,1,0 = 000, division ratio = 1:1
Bit 2,1,0 = 001, division ratio = 1:2
Bit 2,1,0 = 010, division ratio = 1:4
Bit 2,1,0 = 011, division ratio = 1:8
Bit 2,1,0 = 100, division ratio = 1:16
Bit 2,1,0 = 101, division ratio = 1:32
Bit 2,1,0 = 110, division ratio = 1:64
Bit 2,1,0 = 111, division ratio = 1:128
3
WS3
Bit3=1, USBPDP, and USBPDN connected to 300kW pull-high resistor
Bit3=0, No pull-high - default at MCU reset
¾
Not used
WS7
Bit7=1, USB reset signal can reset MCU and set URST_FLAG (bit 2 of 1AH) (default on
at MCU reset)
Bit7=0, USB reset signal cannot reset MCU
4~6
7
WDTS Register
Rev. 1.70
28
November 5, 2014
HT82B40R/HT82B40A
Suspend Wake-Up and Remote Wake-Up
To Configure as PS2 Device
If there is no signal on the USB bus for over 3ms, the device will go into a suspend mode. The Suspend line (bit
0 of the USC register) will be set to ²1² and a USB interrupt is triggered to indicate that the devices should jump
to the suspend state to meet the 500mA USB suspend
current spec.
The devices can also be configured as a USB interface
or PS2 interface device, by configuring SPS2 (bit 4 of
the USR register) and SUSB (bit 5 of the USR register).
If SPS2=1, and SUSB=0, the device will be configured
as a PS2 interface, pin USBPDN is configured as a PS2
Data pin and USBPDP is configured as a PS2 Clk pin.
The user can read or write to the PS2 Data or PS2 Clk
pin by accessing the corresponding bit PS2DAI (bit 4 of
the USC register), PS2CKI (bit 5 of the USC register),
PS2DAO (bit 6 of the USC register) and PS2CKO (bit 7
of the USC register) respectively.
In order to meet the 500mA suspend current, the firmware should disable the USB clock by clearing the
USBCKEN bit which is bit3 of the SCC register to ²0².
The suspend current is 400mA.
The user can further decrease the suspend current to
250mA by setting the SUSP2 bit which is bit4 of the SCC
register. If in the USB mode set this bit LVR OPT must
disable.
The user should make sure that in order to read the data
properly, the corresponding output bit must be set to ²1².
For example, if it is desired to read the PS2 Data by
reading PS2DAI, then PS2DAO should set to ²1². Otherwise it is always read as ²0².
When the resume signal is sent out by the host, the devices will wake up the MCU with a USB interrupt and the
Resume line (bit 3 of the USC register) is set. In order to
make the device function properly, the firmware must
set the USBCKEN (bit 3 of the SCC register) to ²1² and
clear the SUSP2 (bit4 of the SCC register). Since the
Resume signal will be cleared before the Idle signal is
sent out by the host, the Suspend line (bit 0 of the USC
register) will be set to ²0². So when the MCU is detecting
the Suspend line (bit0 of USC register), the Resume line
condition should be noted and taken into consideration.
If SPS2=0, and SUSB=1, the device is configured as a
USB interface. Both the USBPDN and USBPDP is
driven by the SIE of the HT82B40R/ HT82B40A . The
user can only write or read the USB data through the
corresponding FIFO. Both the SPS2 and SUSB default
is ²0².
USB Interface
There are eleven registers used for the USB function.
The AWR register contains the current address and a
remote wake up function control bit. The initial value of
AWR is ²00H². The address value extracted from the
USB command is not to be loaded into this register until
the SETUP stage is completed.
After finishing the resume signal, the suspend line will
go inactive and a USB interrupt will be triggered. The following is the timing diagram.
S U S P E N D
U S B R e s u m e S ig n a l
U S B _ IN T
Bit No.
Label
R/W
Function
0
WKEN
W
Remote wake-up
enable/disable
7~1
AD6~AD0
W
USB device address
AWR (42H) Register
As the device has a remote wake up function it can
wake-up the USB Host by sending a wake-up pulse
through RMWK (bit 1 of the USC register). Once the
USB Host receives a wake-up signal from the devices, it
will send a Resume signal to the device. The timing is as
follows:
S U S P E N D
M in . 1
U S B C L K
R M W K
U S B R e s u m e S ig n a l
M in . 2 .5 m s
U S B _ IN T
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Bit No.
Label
R/W
Function
0
SUSPEND
R
Read only, USB suspend indication. When this bit is set to ²1² (set by the SIE), it indicates that the USB bus has entered the suspend mode. The USB interrupt is also triggered on any change of this bit.
1
RMOT_ WK
W
USB remote wake up command. Set by the MCU to force the USB host to leave the
suspend mode. When this bit is set to ²1², a 2ms delay for clearing this bit to ²0² is
needed to insure the RMWK command is accepted by SIE.
2
USB reset indication. This bit is set/cleared by the USB SIE. This bit is used to detect
URST_ FLAG R/W which bus (PS2 or USB) is attached. When the URST is set to ²1², this indicates that
a USB reset has occurred (the attached bus is USB) and a USB interrupt will be initialised.
3
RESUME_O
R
USB resume indication. When the USB leaves the suspend mode, this bit is set to ²1²
(set by the SIE). This bit will appear for 20ms waiting for the MCU to detect. When the
RESUME is set by the SIE, an interrupt will be generated to wake-up the MCU. In order to detect the suspend state, the MCU should set the USBCKEN and clear SUSP2
(in the SCC register) to enable the SIE detect function. The RESUME will be cleared
while SUSP is going to ²0². When the MCU is detecting the SUSP, the condition of
RESUME (which wakes-up the MCU ) should be noted and taken into consideration.
4
PS2_DAI
R
Read only, USBPDN/DATA input
5
PS2_CKI
R
Read only, USBPDP/CLK input
6
PS2_DAO
W
Data for driving the USBPDN/DATA pin when working under 3D PS2 mouse function.
(Default=²1²)
7
PS2_CKO
W
Data for driving the USBPDP/CLK pin when working under 3D PS2 mouse function.
(Default=²1²)
USC (20H) Register
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select
the serial bus, PS2 or USB. The endpoint request flags, EP0IF, EP1IF and EP2IF, are used to indicate which endpoints
are accessed. If an endpoint is accessed, the related endpoint request flag will be set to ²1² and the USB interrupt will
occur, if the USB interrupt is enabled and the stack is not full. When the active endpoint request flag is served, the endpoint request flag has to be cleared to ²0².
Bit No.
Label
0
EP0_INT
When this bit is set to ²1² (set by the SIE), it indicates that endpoint 0 is accessed
R/W and a USB interrupt will occur. When the interrupt has been served, this bit should
be cleared by firmware.
1
EP1_INT
When this bit is set to ²1² (set by the SIE), it indicates that endpoint 1 is accessed
R/W and a USB interrupt will occur. When the interrupt has been served, this bit should
be cleared by firmware.
2
EP2_INT
When this bit is set to ²1² (set by the SIE), it indicates that endpoint 2 is accessed
R/W and a USB interrupt will occur. When the interrupt has been served, this bit should
be cleared by firmware.
3, 6
¾
4
5
7
R/W
¾
Function
Reserved
00 : Non-USB mode, turn-off V33O, both USBPDP and USBPDN can be read and
write - default
01 : Non-USB mode, has 200W between VDD and V33O, both USBPDP and
MODE_CTRL0
USBPDN can be read and write
R/W
MODE_CTRL1
10 : USB mode, 1.5kW between USBPDN and V33O, V33O output 3.3V,
both USBPDP and USBPDN are read only
11 : Non-USB mode, V33O output 3.3V, both USBPDP and USBPDN can be read
and write
USB_flag
R/W
This flag is used to indicate that the MCU is in the USB mode - Bit=1
This bit is R/W by FW and will be cleared to ²0² after power-on reset - Default=²0²
USR (21H) Register
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There is a system clock control register implemented to select the clock used in the MCU. This register consists of the
USB clock control bit, USBCKEN, second suspend mode control bit, SUSP2, and a system clock selection bit,
SYSCLK. The PS2 mode indicate bit, PS2_flag, and a system clock adjust control bit, CLK_adj.
Bit No.
Label
R/W
0, 1, 2
¾
¾
USBCKEN R/W
3
Function
Reserved bit set ²0²
USB clock control bit. When this bit is set to ²1², it indicates that the USB clock is enabled. Otherwise, the USB clock is turned-off. (Default=²0²)
When set to 1, turn-off Band-gap circuit. Default value is 0.
In the Power-down Mode this bit should be set high to reduce power consumption.The
LVR has no function. In the USB mode this bit cannot be set high.
4
SUSP2
¾
5
PS2_flag
R/W
6
SYSCLK
This bit is used to specify the system oscillator frequency used by the MCU. If an InteR/W grated 6MHz oscillator is used, this bit should be set to ²1². If an Integrated 12MHz oscillator is used, this bit should be cleared to ²0². (default).
CLK_adj
This bit is used to adjust the system clock for the USB mode for temperature changes.
In the Power-down Mode this bit should be set high to reduce power consumption.
R/W
0: enable (default)
1: disable
7
This flag is used to indicate that the MCU is in the PS2 mode. (Bit=1)
This bit is R/W by FW and will be cleared to ²0² after power-on reset. (Default=²0²)
SCC (22H) Register
STALL and PIPE, PIPE_CTRL, Endpt_EN Registers
The PIPE register represents whether the corresponding endpoint is accessed by the host or not. After an ACT_EN signal has been sent out, the MCU can check which endpoint had been accessed. This register is set only after the a time
when the host is accessing the corresponding endpoint.
The STALL register shows whether the corresponding endpoint works or not. As soon as the endpoint works improperly, the corresponding bit must be set.
The PIPE_CTRL Register is used for configuring the IN (Bit=1) or OUT (Bit=0) Pipe. The default is define IN pipe. Bit0
(DATA0) of the PIPE_CTRL Register is used to set the data toggle of any endpoint (except endpoint 0) using data toggles to the value DATA0. Once the user wants any endpoint (except endpoint 0) using data toggles to the value DATA0.
the user can output a LOW pulse to this bit. The LOW pulse period must at least 10 instruction cycles.
The Endpt_EN Register is used to enable or disable the corresponding endpoint (except endpoint 0) Enable Endpoint
(Bit=1) or disable Endpoint (Bit=0)
The bitmaps are list are shown in the following table:
Register
Name
R/W
Register
Address
Bit7~Bit3
Reserved
Bit 2
Bit 1
Bit 0
Default
Value
PIPE_CTRL
R/W
01000001B
¾
SETIO2
SETIO1
DATA0
00000111
STALL
R/W
01000011B
¾
STL2
STL1
STL0
00000111
R
01000100B
¾
Pipe 2
Pipe 1
Pipe 0
00000000
R/W
01000111B
¾
EP2EN
EP1EN
EP0EN
00000111
PIPE
Endpt_EN
PIPE_CTRL (41H), STALL (43H), PIPE (44H) and Endpt_EN (47H) Registers
The USB_STAT Register (40H) is used to indicate the present USB signal state.
Bit No.
Function
Read/Write
0
EOP
R/W
1
J_state
R/W
2
K_state
R/W
3
SE0
R/W
4
SE1
R/W
5~7
¾
¾
Register Address
01000000B
USB_STAT (40H) Register Table
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Func. Name
R/W
Description
EOP
R/W
This bit is used to indicate the SIE has detected a EOP USB signal in the USB Bus. This bit is
set by SIE and cleared by F/W.
J_state
R/W
This bit is used to indicate the SIE has detected a J_state USB signal in the USB Bus. This bit
is set by SIE and cleared by F/W.
K_state
R/W
This bit is used to indicate the SIE has detected a K_state USB signal in the USB Bus. This bit
is set by SIE and cleared by F/W.
¾
¾
SE0
R/W
This bit is used to indicate the SIE has detected a SE0 noise in the USB Bus. This bit is set by
SIE and cleared by F/W.
SE1
R/W
This bit is used to indicate the SIE has detected a SE1 noise in the USB Bus. This bit is set by
SIE and cleared by F/W.
Unused bit, read as ²0²
USB_STAT Function Table
The SIES Register is used to indicate the present signal state in which the SIE receives and also defines whether the
SIE has to change the device address automatically.
Bit No.
Function
Read/Write
0
Adr_set
R/W
1
F0_ERR
R/W
2~6
¾
¾
7
NMI
R/W
Register Address
01000001B
SIES (45H) Register Table
Func. Name
R/W
Description
ADR_ SET
R/W
This bit is used to configure the SIE to automatically change the device address with the value
of the Address+Remote_WakeUp Register.
When this bit is set to ²1² by F/W, the SIE will update the device address with the value of the
Address+Remote_WakeUp Register after the PC Host has successfully read the data from
the device by the IN operation. The SIE will clear the bit after updating the device address.
Otherwise, when this bit is cleared to ²0², the SIE will update the device address immediately
after an address is written to the Address+Remote_WakeUp Register. Default 0.
F0_ERR
R/W
This bit is used to indicate that some errors have occurred when accessing the FIFO0.
This bit is set by SIE and cleared by F/W. Default 0
¾
¾
NMI
R/W
Unused bit, read as ²0²
This bit is used to control whether the USB interrupt is output to the MCU in a NAK response
to the PC Host IN or OUT token. Only for Endpoint0
1: has only USB interrupt, data is transmitted to the PC host or data is received from the PC
Host
0: always has USB interrupt if the USB accesses FIFO0
Default 0
SIES Function Table
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The MISC register combines a command and status to control desired endpoint FIFO action and to show the status of
the desired endpoint FIFO. The MISC will be cleared by the USB reset signal.
Bit No.
Label
REQ
0
R/W
Function
R/W
After setting the other status of the desired one in the MISC, endpoint FIFO can be
requested by setting this bit to ²1². After the task is completed, this bit must be
cleared to ²0².
1
TX
R/W
This bit defines the direction of data transferring between the MCU and endpoint
FIFO. When the TX is set to ²1², this means that the MCU wants to write data to the
endpoint FIFO. After the task is completed, this bit must be cleared to ²0² before terminating the request to represent the end of transferring. For a read action, this bit
has to be cleared to ²0² to represent that MCU wants to read data from the endpoint
FIFO and has to be set to ²1² after completion.
2
CLEAR
R/W
Clear the requested endpoint FIFO, even if the endpoint FIFO is not ready.
4
3
SELP1
SELP0
R/W
Defines which endpoint FIFO is selected, SELP1,SELP0:
00: endpoint FIFO0
01: endpoint FIFO1
10: endpoint FIFO2
11: reserved
5
SCMD
R/W
Used to show that the data in the endpoint FIFO is a SETUP command. This bit has
to be cleared by firmware. That is to say, even if the MCU is busy, the device will not
miss any SETUP commands from the host.
6
READY
R
Read only status bit, this bit is used to indicate that the desired endpoint FIFO is
ready for operation.
7
LEN0
R/W
Used to indicate that a 0-sized packet has been sent from a host to the MCU. This bit
should be cleared by firmware.
MISC (46H) Register
The MCU can communicate with the endpoint FIFO by setting the corresponding registers, of which the address is
listed in the following table. After reading the current data, the next data will show after 2ms, this is used to check the
endpoint FIFO status and response to the MISC register, if the read/write action is still going on.
Registers
R/W
Bank
Address
Bit7~Bit0
FIFO0
R/W
1
48H
Data7~Data0
FIFO1
R/W
1
49H
Data7~Data0
FIFO2
R/W
1
4AH
Data7~Data0
There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform reading, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing and clearing.
Actions
MISC Setting Flow and Status
Read FIFO0 sequence
00H®01H®delay 2ms, check 41H®read* from FIFO0 register and
check not ready (01H)®03H®02H
Write FIFO1 sequence
0AH®0BH®delay 2ms, check 4BH®write* to FIFO1 register and
check not ready (0BH)®09H®08H
Check whether FIFO0 can be read or not
00H®01H®delay 2ms, check 41H (ready) or 01H (not ready)®00H
Check whether FIFO1 can be written or not
0AH®0BH®delay 2ms, check 4BH (ready) or 0BH (not ready)®0AH
Read 0-sized packet sequence form FIFO0
00H®01H®delay 2ms, check 81H®read once (01H)®03H®02H
Write 0-sized packet sequence to FIFO1
0AH®0BH®delay 2ms, check 4BH®09H®08H
Note:
*: There is a 2ms time between 2 read actions or between 2 write actions.
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Table High Byte Pointer for Current Table Read TBHP (Address 0X1F)
Register
TBHP (0X1F)
Bits
Read/Write
3~0
R/W
Functions
Store current table read bit11~bit8 data
Configuration Options
No.
Options
1
PA0~7 Pull-high by bit (default Pull-high)
2
PB, PC, PD wake-up by nibble (default Pull-high)
3
PB, PC, PD Pull-high by nibble (default Pull-high)
4
LVR enable/disable (default enable)
5
WDT function: enable, disable for normal mode (default enable)
6
WDT clock source: RC; fSYS/4 (default T1)
7
CLRWDT instruction is by 1 or 2
8
PA output mode (CMOS/NMOS/PMOS) by bit (default CMOS)
9
PA0~7 wake-up by bit, (default enable)
10
TBHP enable /disable (default disable)
11
PE0, PE1 Pull-high by bit
12
PE0, PE1 wake-up by bit
13
PB0~7 Power source: VDD (default) or V33O regulator output
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Application Circuits
P A 0 ~ P A 7
V D D
U S B -
V D D
1 0 m F
1 0 0 k W
0 .1 m F
P B 0 ~ P B 7
P C 0 ~ P C 7
U S B +
P D 0 ~ P D 7
V S S
P E 0 ~ P E 1
V 3 3 O
1 0 k W
R E S
0 .1 m F
0 .1 m F
U S B P D N /D A T A
V S S
U S B P D P /C L K
H T 8 2 B 4 0 R /H T 8 2 B 4 0 A
Note:
The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the
VDD is stable and remains within a valid operating voltage range before bringing RES high.
Components with * are used for EMC issue.
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.70
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
2Note
2Note
2Note
None
None
None
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m](4) Read ROM code (locate by TBLP and TBHP) to data memory and TBLH
TABRDC [m](5) Read ROM code (current page) to data memory and TBLH
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
4. Configuration option ²TBHP option² is enabled
Rev. 1.70
38
November 5, 2014
HT82B40R/HT82B40A
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev. 1.70
39
November 5, 2014
HT82B40R/HT82B40A
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.70
40
November 5, 2014
HT82B40R/HT82B40A
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.70
41
November 5, 2014
HT82B40R/HT82B40A
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.70
42
November 5, 2014
HT82B40R/HT82B40A
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.70
43
November 5, 2014
HT82B40R/HT82B40A
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.70
44
November 5, 2014
HT82B40R/HT82B40A
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.70
45
November 5, 2014
HT82B40R/HT82B40A
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.70
46
November 5, 2014
HT82B40R/HT82B40A
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDC [m]
Move the ROM code (locate by TBLP and TBHP) to TBLH and data memory (ROM code
TBHP is enabled)
Description
The low byte of ROM code addressed by the table pointers (TBLP and TBHP) is moved to
the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.70
47
November 5, 2014
HT82B40R/HT82B40A
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.70
48
November 5, 2014
HT82B40R/HT82B40A
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the Package/Carton Information.
Additional supplementary information with regard to packaging is listed below. Click on the
relevant section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.70
49
November 5, 2014
HT82B40R/HT82B40A
28-pin SSOP (150mil) Outline Dimensions
1 5
2 8
A
B
1
1 4
C
C '
G
H
D
E
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
¾
0.236 BSC
¾
B
¾
0.154 BSC
¾
C
0.008
¾
0.012
C¢
¾
0.390 BSC
¾
D
¾
¾
0.069
E
¾
0.025 BSC
¾
F
0.004
¾
0.010
G
0.016
¾
0.050
H
0.004
¾
0.010
a
0°
¾
8°
Symbol
Rev. 1.70
a
F
Dimensions in mm
Min.
Nom.
Max.
A
¾
6.000 BSC
¾
B
¾
3.900 BSC
¾
C
0.20
¾
0.30
C¢
¾
9.900 BSC
¾
D
¾
¾
1.75
E
¾
0.635 BSC
¾
F
0.10
¾
0.25
G
0.41
¾
1.27
H
0.10
¾
0.25
a
0°
¾
8°
50
November 5, 2014
HT82B40R/HT82B40A
48-pin SSOP (300mil) Outline Dimensions
4 8
2 5
A
B
1
2 4
C
C '
G
H
D
E
Symbol
A
F
Dimensions in inch
Min.
Nom.
Max.
0.395
¾
0.420
B
0.291
0.295
0.299
C
0.008
¾
0.014
C¢
0.620
0.625
0.630
D
0.095
0.102
0.110
E
¾
0.025 BSC
¾
F
0.008
0.012
0.016
G
0.020
¾
0.040
H
0.005
¾
0.010
a
0°
¾
8°
Symbol
Rev. 1.70
a
Dimensions in mm
Min.
Nom.
Max.
A
10.03
¾
10.67
B
7.39
7.49
7.59
C
0.20
¾
0.34
C¢
15.75
15.88
16.00
D
2.41
2.59
2.79
E
¾
0.64 BSC
¾
F
0.20
0.30
0.41
G
0.51
¾
1.02
H
0.13
¾
0.25
a
0°
¾
8°
51
November 5, 2014
HT82B40R/HT82B40A
SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions
D
D 2
2 5
3 2
2 4
b
1
E
E 2
e
1 7
8
1 6
A 1
A 3
L
9
K
A
Symbol
Nom.
Max.
A
0.028
0.030
0.031
A1
0.000
0.001
0.002
A3
¾
0.008 BSC
¾
b
0.007
0.010
0.012
D
0.193
0.197
0.201
E
0.193
0.197
0.201
e
¾
0.020 BSC
¾
D2
0.122
0.126
0.130
E2
0.122
0.126
0.130
L
0.014
0.016
0.018
K
0.008
¾
¾
Symbol
Rev. 1.70
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
0.700
0.750
0.800
A1
0.000
0.020
0.050
A3
¾
0.203 BSC
¾
b
0.180
0.250
0.300
D
4.900
5.000
5.100
E
4.900
5.000
5.100
e
¾
0.500 BSC
¾
D2
3.100
3.200
3.30
E2
3.00
3.200
3.30
L
0.35
0.40
0.45
K
0.20
¾
¾
52
November 5, 2014
HT82B40R/HT82B40A
48-pin LQFP (7mm´7mm) Outline Dimensions
C
H
D
3 6
G
2 5
I
3 7
2 4
F
A
B
E
4 8
1 3
K
a
J
1
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
¾
0.354 BSC
¾
B
¾
0.276 BSC
¾
C
¾
0.354 BSC
¾
D
¾
0.276 BSC
¾
E
¾
0.020 BSC
¾
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
¾
¾
0.063
I
0.002
¾
0.006
J
0.018
0.024
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
A
Rev. 1.70
1 2
Dimensions in mm
Min.
Nom.
Max.
¾
9.00 BSC
¾
B
¾
7.00 BSC
¾
C
¾
9.00 BSC
¾
D
¾
7.00 BSC
¾
E
¾
0.50 BSC
¾
F
0.17
0.22
0.27
G
1.35
1.40
1.45
H
¾
¾
1.60
I
0.05
¾
0.15
J
0.45
0.60
0.75
K
0.09
¾
0.20
a
0°
¾
7°
53
November 5, 2014
HT82B40R/HT82B40A
Copyright Ó 2014 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and
Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a
risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use
as critical components in life support devices or systems. Holtek reserves the right to alter its
products without prior notification. For the most up-to-date information, please visit our web
site at http://www.holtek.com.tw.
Rev. 1.70
54
November 5, 2014