ATMEL AT28C040-20FI 4-megabit 512k x 8 paged e2prom Datasheet

Features
• Read Access Time - 200 ns
• Automatic Page Write Operation
•
•
•
•
•
•
•
•
– Internal Address and Data Latches for 256 Bytes
– Internal Control Timer
Fast Write Cycle Time
– Page Write Cycle Time - 10 ms Maximum
– 1 to 256 Byte Page Write Operation
Low Power Dissipation
– 80 mA Active Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 10,000 Cycles
– Data Retention: 10 Years
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-Wide Pinout
4-Megabit
(512K x 8)
Paged E2PROM
AT28C040
Description
The AT28C040 is a high-performance electrically erasable and programmable read
only memory (E2PROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device
offers access times to 200 ns with power dissipation of just 440 mW.
(continued)
Pin Configurations
Pin Name
Function
A0 - A18
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
LCC
Top View
SIDE BRAZE,
FLATPACK
Top View
AT28C040 4Megabit (512K x
8) Paged
E2PROM
Rev. 0542B–04/98
1
The AT28C040 is accessed like a static RAM for the read
or write cycle without the need for external components.
The device contains a 256-byte page register to allow writing of up to 256 bytes simultaneously. During a write cycle,
the address and 1 to 256 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will
automatically write the latched data using an internal control timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has
been detected, a new access for a read or write can begin.
Atmel's AT28C040 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved data
retention characteristics. An optional software data protection mechanism is available to guard against inadvertent
writes. The device also includes an extra 256 bytes of
E2PROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
2
AT28C040
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
AT28C040
Device Operation
READ: The AT28C040 is accessed like a static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their systems.
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cycle.
The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising
edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated and for the duration
of tWC, a read operation will effectively be a polling operation.
PAGE WRITE: The page write operation of the AT28C040
allows 1 to 256 bytes of data to be written into the device
during a single internal programming period. A page write
operation is initiated in the same manner as a byte write;
the first byte written can then be followed by 1 to 255 additional bytes. Each successive byte must be written within
150 µs (t BLC ) of the previous byte. If the t BLC limit is
exceeded, the AT28C040 will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A8 - A18 inputs. For
each WE high to low transition during the page write operation, A8 - A18 must be the same.
The A0 to A7 inputs specify which bytes within the page are
to be written. The bytes may be loaded in any order and
may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary
cycling of other bytes within the page does not occur.
DATA POLLING: The AT28C040 features DATA Polling to
indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write
cycle.
TOGGLE BIT: In addition to DATA Polling, the AT28C040
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling
between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28C040 in the following
ways: (a) VCC sense - if VCC is below 3.8V (typical) the write
function is inhibited; (b) V CC power-on delay - once VCC has
reached 3.8V the device will automatically time out 5 ms
(typical) before allowing a write: (c) write inhibit - holding
any one of OE low, CE high or WE high inhibits write
cycles; (d) noise filter - pulses of less than 15 ns (typical)
on the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28C040. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28C040 is
shipped from Atmel with SDP disabled.
SDP is enabled when the host system issues a series of
three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command
sequence and after tWC, the entire AT28C040 will be protected against inadvertent write operations. It should be
noted that once protected, the host can still perform a byte
or page write to the AT28C040. To do so, the same 3-byte
command sequence used to enable SDP must precede the
data to be written.
Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable
SDP, and SDP will protect the AT28C040 during power-up
and power-down conditions. All command sequences must
conform to the page write timing specifications. The data in
the enable and disable command sequences is not written
to the device, and the memory addresses used in the
sequence may be written with data in either a byte or page
write operation.
After setting SDP, any attempt to write to the device without
the 3-byte command sequence will start the internal write
timers. No data will be written to the device; however, for
the duration of tWC, read operations will effectively be polling operations.
DEVICE IDENTIFICATION: An extra 256 bytes of
E2PROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address
locations 7FF80H to 7FFFFH, the bytes may be written to
or read from in the same manner as the regular memory
array.
OPTIONAL CHIP ERASE MODE: The entire device can
be erased using a 6-byte software erase code. Please see
Software Chip Erase application note for details.
3
DC and AC Operating Range
AT28C040-20
AT28C040-25
Operation
Operation
Read
Program
Read
Program
0°C - 70°C
0°C - 70°C
0°C - 70°C
0°C - 70°C
Industrial
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
Extended
-55°C - 125°C
-40°C - 85°C
-55°C - 125°C
-40°C - 85°C
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
Mode
CE
OE
WE
I/O
Read
VIL
VIL
VIH
DOUT
VIL
VIH
VIL
DIN
High Z
Operating
Temperature
(Case)
Commercial
VCC Power Supply
Operating Modes
Write
(2)
Standby/Write Inhibit
(1)
VIH
X
X
Write Inhibit
X
X
VIH
Write Inhibit
X
VIL
X
Output Disable
X
VIH
X
Notes:
High Z
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
DC Characteristics
4
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Min
Max
Units
VIN = 0V to VCC + 1V
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC + 1V
3
mA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC + 1V
3
mA
ICC
VCC Active Current
f = 5 MHz; IOUT = 0 mA
80
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
2.4
V
VOH2
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
4.2
V
2.0
AT28C040
V
0.45
V
AT28C040
AC Read Characteristics
Symbol
Parameter
tACC
AT28C040-20
AT28C040-25
Min
Min
Max
Max
Units
Address to Output Delay
200
250
ns
(1)
CE to Output Delay
200
250
ns
(2)
OE to Output Delay
0
55
0
55
ns
tDF(3)(4)
CE or OE to Output Float
0
55
0
55
ns
tOH
Output Hold from OE, CE or Address, whichever occurred first
0
tCE
tOE
0
ns
AC Read Waveforms(1)(2)(3)(4)
Note:
1.
CE May be delayed up to tACC - tCE after the address transition wihtout impact on tACC.
2.
OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3.
tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4.
This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
Max
Units
CIN
4
10
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
Conditions
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol
Parameter
Min
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
100
ns
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE Hold Time
0
ns
AC Write Waveforms
WE Controlled
CE Controlled
6
AT28C040
Max
Units
AT28C040
Page Mode Characteristics
Symbol
Parameter
Min
Max
Units
tWC
Write Cycle Time
10
ms
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
100
ns
tBLC
Byte Load Cycle Time
tWPH
Write Pulse Width High
150
50
µs
ns
Page Mode Write Waveforms(1)(2)
Notes:
1.
A8 through A18 must specify the page address during each high to low transition of WE (or CE).
2.
OE must be high only when WE and CE are both low.
7
Software Data
Protection Enable Algorithm(1)
Software Data
Protection Disable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES
ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS (4)
LOAD LAST BYTE
TO
LAST ADDRESS
Notes:
1.
LOAD DATA AA
TO
ADDRESS 5555
ENTER DATA
PROTECT STATE
Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2.
Write Protect state will be activated at end of write
even if no other data is loaded.
3.
Write Protect state will be deactivated at end of write
period even if no other data is loaded.
4.
LOAD DATA 80
TO
ADDRESS 5555
1 to 25 bytes of data are loaded.
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
LOAD DATA XX
TO
ANY ADDRESS (4)
LOAD LAST BYTE
TO
LAST ADDRESS
Software Protected Program Cycle Waveform(1)(2)(3)
Notes:
8
1.
A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above.
2.
After the command sequence has been issued and a page write operation follows, the page address inputs (A8 - A18) must
be the same for each high to low transition of WE (or CE).
3.
OE must be high only when WE and CE are both low.
AT28C040
AT28C040
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
Max
OE to Output Delay
tWR
Write Recovery Time
Units
10
ns
10
ns
(2)
tOE
Notes:
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay(2)
tOEHP
OE High Pulse
tWR
Write Recovery Time
Notes:
Min
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes:
1.
Toggling either OE or CE or both OE and CE will operate toggle bit.
2.
Beginning and ending state of I/O6 will vary.
3.
Any address location may be used but the address should not vary.
9
Ordering Information(1)
Active
Standby
Ordering Code
Package
200
80
3
AT28C040-20BC
AT28C040-20FC
AT28C040-20LC
32B
32F
44L
Commercial
(0° to 70°C)
80
3
AT28C040-20BI
AT28C040-20FI
AT28C040-20LI
32B
32F
44L
Industrial
(-40° to 85°C)
80
3
AT28C040-20BI SL703
AT28C040-20FI SL703
AT28C040-20LI SL703
32B
32F
44L
Extended
(See DC and AC Operating
Range Table)
80
3
AT28C040-25BC
AT28C040-25FC
AT28C040-25LC
32B
32F
44L
Commercial
(0° to 70°C)
80
3
AT28C040-25BI
AT28C040-25FI
AT28C040-25LI
32B
32F
44L
Industrial
(-40° to 85°C)
80
3
AT28C040-25BI SL703
AT28C040-25FI SL703
AT28C040-25LI SL703
32B
32F
44L
Extended
(See DC and AC Operating
Range Table)
250
Note:
10
ICC (mA)
tACC
(ns)
1. See Valid Part Numbers on next page.
AT28C040
Operation Range
AT28C040
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
Speed
Package and Temperature Combinations
AT28C040
20
BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703
AT28C040
25
BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703
Package Type
32B
32-Lead, 0.600" Wide, Ceramic Side Braze Dual Inline (Side Braze)
32F
32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
44L
44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
Options
Blank
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
11
Packaging Information
32B, 32-Lead, 0.600” Wide, Ceramic Side Braze
Dual Inline (Side Braze)
Dimensions in Inches and (Millimeters)
32F, 32-Lead, Non-Windowed, Ceramic BottomBrazed Flat Package (Flatpack)
Dimension in Inches and (Millimeters)
JEDEC OUTLINE MO-115
PIN #1 ID
.370(9.40)
.270(6.86)
.019(.482)
.015(.381)
.829(21.1)
.811(20.6)
.050(1.27) BSC
.045(1.14) MAX
.488(12.4)
.472(12.0)
.120(3.05)
.098(2.49)
.006(.152)
.004(.101)
.408(10.4)
.355(9.02)
.045(1.14)
.026(.660)
.072(1.82)
.030(0.76)
44L, 44-Pad, Non-Windowed, Ceramic Leadless
Chip Carrier (LCC)
Dimensions in Inches and (Millimeters)*
MIL-STD-1835 C-5
*Ceramic lid standard unless specified.
12
AT28C040
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