AD AD629BR-REEL7 High common-mode voltage, difference amplifier Datasheet

High Common-Mode Voltage,
Difference Amplifier
AD629
FUNCTIONAL BLOCK DIAGRAM
Improved replacement for: INA117P and INA117KU
±270 V common-mode voltage range
Input protection to
±500 V common mode
±500 V differential mode
Wide power supply range (±2.5 V to ±18 V)
±10 V output swing on ±12 V supply
1 mA maximum power supply current
–IN
380kΩ
21.1kΩ
REF(–) 1
380kΩ
2
7 +VS
380kΩ
+IN 3
6 OUTPUT
20kΩ
–VS 4
8 NC
AD629
5 REF(+)
00783-001
FEATURES
NC = NO CONNECT
Figure 1.
GENERAL DESCRIPTION
HIGH ACCURACY DC PERFORMANCE
3 ppm maximum gain nonlinearity (AD629B)
20 μV/°C maximum offset drift (AD629A)
10 μV/°C maximum offset drift (AD629B)
10 ppm/°C maximum gain drift
The AD629 is a difference amplifier with a very high input,
common-mode voltage range. It is a precision device that allows
the user to accurately measure differential signals in the
presence of high common-mode voltages up to ±270 V.
The AD629 can replace costly isolation amplifiers in
applications that do not require galvanic isolation. The device
operates over a ±270 V common-mode voltage range and has
inputs that are protected from common-mode or differential
mode transients up to ±500 V.
EXCELLENT AC SPECIFICATIONS
77 dB minimum CMRR @ 500 Hz (AD629A)
86 dB minimum CMRR @ 500 Hz (AD629B)
500 kHz bandwidth
The AD629 has low offset, low offset drift, low gain error drift,
low common-mode rejection drift, and excellent CMRR over a
wide frequency range.
APPLICATIONS
High voltage current sensing
Battery cell voltage monitors
Power supply current monitors
Motor controls
Isolation
The AD629 is available in low cost, 8-lead PDIP and 8-lead
SOIC packages. For all packages and grades, performance is
guaranteed over the industrial temperature range of −40°C to
+85°C.
2mV/DIV
95
OUTPUT ERROR (2mV/DIV)
90
85
80
75
70
65
55
50
20
100
1k
FREQUENCY (Hz)
10k
20k
00783-003
60
00783-002
COMMON-MODE REJECTION RATIO (dB)
100
60V/DIV
–240
–120
0
120
COMMON-MODE VOLTAGE (V)
240
Figure 2. Common-Mode Rejection Ratio vs. Frequency
Figure 3. Error Voltage vs. Input Common-Mode Voltage
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1999-2007 Analog Devices, Inc. All rights reserved.
Rev. B
AD629
TABLE OF CONTENTS
Features .............................................................................................. 1
Basic Connections...................................................................... 10
Applications....................................................................................... 1
Single-Supply Operation ........................................................... 10
Functional Block Diagram .............................................................. 1
System-Level Decoupling and Grounding.............................. 10
General Description ......................................................................... 1
Using a Large Sense Resistor..................................................... 11
Revision History ............................................................................... 2
Output Filtering.......................................................................... 11
Specifications..................................................................................... 3
Output Current and Buffering.................................................. 12
Absolute Maximum Ratings............................................................ 4
A Gain of 19 Differential Amplifier......................................... 12
ESD Caution.................................................................................. 4
Error Budget Analysis Example 1 ............................................ 12
Typical Performance Characteristics ............................................. 5
Error Budget Analysis Example 2 ............................................ 13
Theory of Operation ........................................................................ 9
Outline Dimensions ....................................................................... 14
Applications..................................................................................... 10
Ordering Guide............................................................................... 15
REVISION HISTORY
3/07—Rev. A to Rev. B
Updated Format and Layout .............................................Universal
Changes to Ordering Guide .......................................................... 15
3/00—Rev. 0 to Rev. A
10/99—Revision 0: Initial Version
Rev. B | Page 2 of 16
AD629
SPECIFICATIONS
TA = 25°C, VS = ±15 V, unless otherwise noted.
Table 1.
Parameter
GAIN
Nominal Gain
Gain Error
Gain Nonlinearity
Gain vs. Temperature
OFFSET VOLTAGE
Offset Voltage
vs. Temperature
vs. Supply (PSRR)
INPUT
Common-Mode Rejection Ratio
Operating Voltage Range
Input Operating Impedance
OUTPUT
Operating Voltage Range
Output Short-Circuit Current
Capacitive Load
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
Slew Rate
Full Power Bandwidth
Settling Time
OUTPUT NOISE VOLTAGE
0.01 Hz to 10 Hz
Spectral Density, ≥100 Hz 1
POWER SUPPLY
Operating Voltage Range
Quiescent Current
TEMPERATURE RANGE
For Specified Performance
1
Condition
VOUT = ±10 V, RL = 2 kΩ
Min
RL = 10 kΩ
TA = TMIN to TMAX
VS = ±5 V
TA = TMIN to TMAX
VS = ±5 V to ± 15 V
84
VCM = ±250 V dc
TA = TMIN to TMAX
VCM = 500 V p-p, dc to 500 Hz
VCM = 500 V p-p, dc to 1 kHz
Common mode
Differential
Common mode
Differential
77
73
77
RL = 10 kΩ
RL = 2 kΩ
VS = ±12 V, RL = 2 kΩ
±13
±12.5
±10
AD629A
Typ
Max
Min
1
0.01
4
1
3
10
1
0.01
4
1
3
0.2
1
0.1
6
100
20
0.05
10
90
88
86
82
86
88
96
±270
±13
±13
±12.5
±10
1000
500
2.1
28
15
12
5
1.7
±2.5
0.9
1.2
−40
See Figure 19.
Rev. B | Page 3 of 16
±18
1
±2.5
+85
−40
Unit
V/V
%
ppm
ppm
ppm/°C
mV
mV
μV/°C
dB
dB
dB
dB
dB
V
V
kΩ
kΩ
V
V
V
mA
pF
±25
15
550
VOUT = 0 V
TMIN to TMAX
0.5
1
10
200
800
1000
VOUT = 20 V p-p
0.01%, VOUT = 10 V step
0.1%, VOUT = 10 V step
0.01%, VCM = 10 V step, VDIFF = 0 V
0.03
10
3
10
90
200
800
1.7
TA = TMIN to TMAX
3
110
±270
±13
±25
Stable operation
AD629B
Typ
Max
500
2.1
28
15
12
5
kHz
V/μs
kHz
μs
μs
μs
15
550
μV p-p
nV/√Hz
0.9
1.2
±18
1
V
mA
mA
+85
°C
AD629
ABSOLUTE MAXIMUM RATINGS
1
Rating
±18 V
See Figure 4
See Figure 4
±300 V
±500 V
Indefinite
–VS − 0.3 V to +VS + 0.3 V
150°C
−55°C to +125°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2.0
TJ = 150°C
Specification is for device in free air:
8-Lead PDIP, θJA = 100°C/W;
8-Lead SOIC, θJA = 155°C/W.
8-LEAD PDIP
1.5
1.0
8-LEAD SOIC
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60
AMBIENT TEMPERATURE (°C)
00783-004
Parameter
Supply Voltage, VS
Internal Power Dissipation 1
8-Lead PDIP (N)
8-Lead SOIC (R)
Input Voltage Range, Continuous
Common-Mode and Differential, 10 sec
Output Short-Circuit Duration
Pin 1 and Pin 5
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
MAXIMUM POWER DISSIPATION (W)
Table 2.
70
80
90
Figure 4. Maximum Power Dissipation vs. Temperature for SOIC and PDIP
ESD CAUTION
Rev. B | Page 4 of 16
AD629
TYPICAL PERFORMANCE CHARACTERISTICS
100
400
90
360
80
320
COMMON-MODE VOLTAGE (±V)
60
50
40
30
10
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
120
80
0
10M
2
4
6
8
10
12
14
16
POWER SUPPLY VOLTAGE (±V)
18
20
RL = 2kΩ
VS = ±18V
OUTPUT ERROR (2mV/DIV)
VS = ±15V
4V/DIV
VS = ±10V
–8
–4
0
4
VOUT (V)
8
12
16
VS = ±15V
VS = ±12V
00783-007
VS = ±12V
–12
0
Figure 8. Common-Mode Operating Range vs. Power Supply Voltage
VS = ±18V
OUTPUT ERROR (2mV/DIV)
160
RL = 10kΩ
2mV/DIV
–16
TA = –40°C
200
40
Figure 5. Common-Mode Rejection Ratio vs. Frequency
–20
TA = +85°C
240
00783-006
20
280
00783-009
70
TA = +25°C
VS = ±10V
–20
20
Figure 6. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage, RL = 10 kΩ (Curves Offset for Clarity)
–16
–12
–8
–4
4V/DIV
0
4
VOUT (V)
8
12
16
00783-010
COMMON-MODE REJECTION RATIO (dB)
TA = 25°C, VS = ±15 V, unless otherwise noted.
20
Figure 9. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage, RL = 2 kΩ (Curves Offset for Clarity)
RL = 1kΩ
VS = ±5V, RL = 10kΩ
OUTPUT ERROR (2mV/DIV)
VS = ±15V
VS = ±10V
–20
–16
–12
–8
–4
4V/DIV
0
4
VOUT (V)
8
12
16
VS = ±5V, RL = 1kΩ
00783-008
VS = ±12V
VS = ±5V, RL = 2kΩ
1V/DIV
VS = ±2.5V, RL = 1kΩ
–20
20
Figure 7. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage, RL = 1 kΩ (Curves Offset for Clarity)
–16
–12
–8
–4
0
4
VOUT (V)
8
12
16
00783-011
OUTPUT ERROR (2mV/DIV)
VS = ±18V
20
Figure 10. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage
Operating Range vs. Supply Voltage (Curves Offset for Clarity)
Rev. B | Page 5 of 16
AD629
20µV/DIV
40µV/DIV
VS = ±15V
RL = 2kΩ
2.5V/DIV
–10
–5
0
VOUT (V)
5
00783-015
00783-012
ERROR (2ppm/DIV)
ERROR (0.8ppm/DIV)
VS = ±15V
RL = 10kΩ
2V/DIV
10
–10
Figure 11. Gain Nonlinearity; VS = ±15 V, RL = 10 kΩ
–8
–6
–4
–2
0
2
VOUT (V)
4
6
8
10
Figure 14. Gain Nonlinearity; VS = ±15 V, RL = 2kΩ
14.0
20µV/DIV
–40°C
VS = ±12V
RL = 10kΩ
13.0
–40°C
11.0
VS= ±15V
–10
–8
–6
–4
–2
0
2
VOUT (V)
4
6
8
9.0
–11.5
–12.0
–40°C
00783-013
–13.0
–13.5
10
+25°C
+85°C
0
2
4
6
8
10
12
14
OUTPUT CURRENT (mA)
16
11.5
VS = ±5V
RL = 1kΩ
–40°C
–40°C
OUTPUT VOLTAGE (V)
ERROR (6.67ppm/DIV)
9.5
8.5
VS= ±12V
+25°C
7.5
+85°C
6.5
–9.0
–9.5
–40°C
–1.8
–1.2
–0.6
0
0.6
VOUT (V)
1.2
1.8
2.4
Figure 13. Gain Nonlinearity; VS = ±5 V, RL = 1 kΩ
+25°C
–10.5
–11.0
3.0
00783-017
00783-014
–10.0
–2.4
20
+85°C
10.5
0.6V/DIV
–3.0
18
Figure 15. Output Voltage Operating Range vs. Output Current; VS = ±15 V
Figure 12. Gain Nonlinearity; VS = ±12 V, RL =10 kΩ
40µV/DIV
+25°C
10.0
–12.5
2V/DIV
+85°C
00783-016
ERROR (1ppm/DIV)
OUTPUT VOLTAGE (V)
12.0
+85°C
0
2
4
6
8
10
12
14
OUTPUT CURRENT (mA)
16
18
20
Figure 16. Output Voltage Operating Range vs. Output Current; VS = ±12 V
Rev. B | Page 6 of 16
AD629
4.5
+85°C
–40°C
3.5
+85°C
1.5
0.5
VS= ±5V
+25°C
+85°C
–2.0
–2.5
–40°C
–3.0
–3.5
–4.0
+85°C
+25°C
0
2
4
6
8
10
12
14
OUTPUT CURRENT (mA)
16
18
25mV/DIV
Figure 17. Output Voltage Operating Range vs. Output Current; VS = ±5 V
+VS
100
G = +1
RL = 2kΩ
CL = 1000pF
–VS
90
80
70
60
50
30
1.0
10
100
FREQUENCY (Hz)
1k
25mV/DIV
4µs/DIV
10k
Figure 18. Power Supply Rejection Ratio vs. Frequency
00783-022
40
0.1
Figure 21. Small Signal Pulse Response
5.0
4.5
G = +1
RL = 2kΩ
CL = 1000pF
4.0
3.5
3.0
2.5
2.0
1.5
1.0
00783-020
VOLTAGE NOISE SPECTRAL DENSITY (µV/ Hz)
Figure 20. Small Signal Pulse Response
110
00783-019
POWER SUPPLY REJECTION RATIO (dB)
120
4µs/DIV
20
00783-021
00783-018
+25°C
0.5
0.01
0.1
1.0
10
100
FREQUENCY (Hz)
1k
10k
5V/DIV
5µs/DIV
100k
Figure 19. Voltage Noise Spectral Density vs. Frequency
Figure 22. Large Signal Pulse Response
Rev. B | Page 7 of 16
00783-023
OUTPUT VOLTAGE (V)
G = +1
RL = 2kΩ
CL = 1000pF
–40°C
2.5
AD629
5V/DIV
5V/DIV
0V
+10V
VOUT
VOUT
–10V
OUTPUT
ERROR
OUTPUT
ERROR
1mV/DIV
10µs/DIV
00783-024
1mV = 0.01%
1mV/DIV
Figure 23. Settling Time to 0.01%, for 0 V to 10 V Output Step; G = −1, RL = 2 kΩ
300
200
150
100
150
100
0
150
–900
–600
–300
0
300
OFFSET VOLTAGE (µV)
600
900
Figure 27. Typical Distribution of Offset Voltage; Package Option N-8
400
400
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
350
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
300
250
200
150
250
200
150
100
50
50
00783-026
100
–400
–200
0
200
–1 GAIN ERROR (ppm)
400
0
–600
600
00783-029
NUMBER OF UNITS
300
0
–600
00783-028
00783-025
–100
–50
0
50
100
COMMON-MODE REJECTION RATIO (ppm)
Figure 24. Typical Distribution of Common-Mode Rejection; Package Option N-8
NUMBER OF UNITS
200
50
50
350
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
250
NUMBER OF UNITS
NUMBER OF UNITS
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
250
0
–150
10µs/DIV
Figure 26. Settling Time to 0.01% for 0 V to −10 V Output Step; G = −1, RL = 2kΩ
350
300
1mV = 0.01%
00783-027
0V
–400
–200
0
200
+1 GAIN ERROR (ppm)
400
600
Figure 28. Typical Distribution of +1 Gain Error; Package Option N-8
Figure 25. Typical Distribution of −1 Gain Error; Package Option N-8
Rev. B | Page 8 of 16
AD629
THEORY OF OPERATION
To achieve high common-mode voltage range, an internal
resistor divider (Pin 3 or Pin 5) attenuates the noninverting
signal by a factor of 20. Other internal resistors (Pin 1, Pin 2,
and the feedback resistor) restore the gain to provide a differential
gain of unity. The complete transfer function equals
To reduce output drift, the op amp uses super beta transistors
in its input stage. The input offset current and its associated
temperature coefficient contribute no appreciable output
voltage offset or drift, which has the added benefit of reducing
voltage noise because the corner where 1/f noise becomes
dominant is below 5 Hz. To reduce the dependence of gain
accuracy on the op amp, the open-loop voltage gain of the op
amp exceeds 20 million, and the PSRR exceeds 140 dB.
REF(–) 1
VOUT = V (+IN) − V (−IN)
–IN 2
Laser wafer trimming provides resistor matching so that
common-mode signals are rejected while differential input
signals are amplified.
+IN 3
–VS 4
21.1kΩ
380kΩ
380kΩ
380kΩ
20kΩ
AD629
8
NC
7
+VS
6
OUTPUT
5
REF(+)
NC = NO CONNECT
Figure 29. Functional Block Diagram
Rev. B | Page 9 of 16
00783-001
The AD629 is a unity gain, differential-to-single-ended
amplifier (diff amp) that can reject extremely high commonmode signals (in excess of 270 V with 15 V supplies). It consists
of an operational amplifier (op amp) and a resistor network.
AD629
APPLICATIONS
BASIC CONNECTIONS
REF (–)
1
+VS
REF (–)
1
–IN
RSHUNT
2
+IN
3
–VS
(SEE
TEXT)
AD629
380kΩ
380kΩ
+3V TO +18V
8
380kΩ
7
NC
+VS
6
20kΩ
4
5
0.1µF
(SEE
TEXT)
VOUT = ISHUNT × RSHUNT
REF (+)
0.1µF
NC = NO CONNECT
–VS
–3V TO –18V
00783-030
ISHUNT
21.1kΩ
–IN
ISHUNT
RSHUNT
2
+IN
3
AD629
380kΩ
380kΩ
VX
380kΩ
VY
–VS
+VS
8
7
NC
+VS
0.1µF
6
20kΩ
4
5
REF (+)
OUTPUT = VOUT – VREF
NC = NO CONNECT
VREF
00783-031
Figure 30 shows the basic connections for operating the AD629
with a dual supply. A supply voltage of between ±3 V and ±18 V
is applied between Pin 7 and Pin 4. Both supplies should be
decoupled close to the pins using 0.1 μF capacitors. Electrolytic
capacitors of 10 μF, also located close to the supply pins, may be
required if low frequency noise is present on the power supply.
While multiple amplifiers can be decoupled by a single set of
10 μF capacitors, each in amp should have its own set of 0.1 μF
capacitors so that the decoupling point can be located right at
the IC’s power pins.
21.1kΩ
Figure 31. Operation with a Single Supply
Applying a reference voltage to REF(+) and REF(–) and
operating on a single supply reduces the input common-mode
range of the AD629. The new input common-mode range
depends upon the voltage at the inverting and noninverting
inputs of the internal operational amplifier, labeled VX and VY
in Figure 31. These nodes can swing to within 1 V of either rail.
Therefore, for a (single) supply voltage of 10 V, VX and VY can
range between 1 V and 9 V. If VREF is set to 5 V, the permissible
common-mode range is +85 V to –75 V. The common-mode
voltage ranges can be calculated by
Figure 30. Basic Connections
VCM (±) = 20 VX/VY(±) − 19 VREF
The differential input signal, which typically results from a load
current flowing through a small shunt resistor, is applied to
Pin 2 and Pin 3 with the polarity shown to obtain a positive
gain. The common-mode range on the differential input signal
can range from −270 V to +270 V, and the maximum differential
range is ±13 V. When configured as shown in Figure 30, the
device operates as a simple gain-of-1, differential-to-singleended amplifier; the output voltage being the shunt resistance
times the shunt current. The output is measured with respect to
Pin 1 and Pin 5.
Pin 1 and Pin 5 (REF(–) and REF(+)) should be grounded for a
gain of unity and should be connected to the same low impedance
ground plane. Failure to do this results in degraded commonmode rejection. Pin 8 is a no connect pin and should be left open.
SINGLE-SUPPLY OPERATION
Figure 31 shows the connections for operating the AD629 with
a single supply. Because the output can swing to within only
about 2 V of either rail, it is necessary to apply an offset to the
output. This can be conveniently done by connecting REF(+)
and REF(–) to a low impedance reference voltage (some ADCs
provide this voltage as an output), which is capable of sinking
current. Therefore, for a single supply of 10 V, VREF may be set
to 5 V for a bipolar input signal. This allows the output to swing
±3 V around the central 5 V reference voltage. Alternatively, for
unipolar input signals, VREF can be set to about 2 V, allowing the
output to swing from 2 V (for a 0 V input) to within 2 V of the
positive rail.
SYSTEM-LEVEL DECOUPLING AND GROUNDING
The use of ground planes is recommended to minimize the
impedance of ground returns (and therefore the size of dc
errors). Figure 32 shows how to work with grounding in a
mixed-signal environment, that is, with digital and analog
signals present. To isolate low level analog signals from a noisy
digital environment, many data acquisition components have
separate analog and digital ground returns. All ground pins
from mixed-signal components, such as ADCs, should return
through a low impedance analog ground plane. Digital ground
lines of mixed-signal converters should also be connected to the
analog ground plane. Typically, analog and digital grounds
should be separated; however, it is also a requirement to
minimize the voltage difference between digital and analog
grounds on a converter, to keep them as small as possible
(typically <0.3 V). The increased noise, caused by the
converter’s digital return currents flowing through the analog
ground plane, is typically negligible. Maximum isolation
between analog and digital is achieved by connecting the ground
planes back at the supplies. Note that Figure 32 suggests a “star”
ground system for the analog circuitry, with all ground lines
being connected, in this case, to the ADC’s analog ground.
However, when ground planes are used, it is sufficient to
connect ground pins to the nearest point on the low impedance
ground plane.
Rev. B | Page 10 of 16
AD629
Table 3 shows some sample error voltages generated by a
common-mode voltage of 200 V dc with shunt resistors from
20 Ω to 2000 Ω. Assuming that the shunt resistor is selected to
use the full ±10 V output swing of the AD629, the error voltage
becomes quite significant as RSHUNT increases.
DIGITAL
POWER SUPPLY
GND +5V
0.1µF
0.1µF
7
–IN
2
AD629
OUTPUT 6
REF(–) REF(+)
1
14
VDD AGND DGND
+VS
–VS
3
6
4
VIN1
3
VIN2
AD7892-2
Table 3. Error Resulting from Large Values of RSHUNT
(Uncompensated Circuit)
VDD
GND
12
MICROPROCESSOR
RS (Ω)
20
1000
2000
00783-032
4
+IN
1
5
Figure 32. Optimal Grounding Practice for a Bipolar Supply Environment
with Separate Analog and Digital Supplies
POWER SUPPLY
GND
+5V
0.1µF
0.1µF
–IN
2
+VS
AD629
VDD
–VS
VIN1
OUTPUT 6
VIN2
REF(–) REF(+)
1
REF (–)
AGND DGND
VDD
ADC
1
GND
MICROPROCESSOR
00783-033
+IN
3
4
Error Indicated (mA)
0.5
0.498
0.5
To measure low current or current near zero in a high commonmode environment, an external resistor equal to the shunt
resistor value can be added to the low impedance side of the
shunt resistor, as shown in Figure 34.
0.1µF
7
Error VOUT (V)
0.01
0.498
1
5
ISHUNT
RCOMP
–IN
RSHUNT
+IN
2
21.1kΩ
AD629
380kΩ
380kΩ
380kΩ
3
Figure 33. Optimal Ground Practice in a Single-Supply Environment
–VS
If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 33 shows how to
minimize interference between the digital and analog circuitry.
In this example, the ADC’s reference is used to drive Pin REF(+)
and Pin REF(–). This means that the reference must be capable
of sourcing and sinking a current equal to VCM/200 kΩ. As in
the previous case, separate analog and digital ground planes
should be used (reasonably thick traces can be used as an
alternative to a digital ground plane). These ground planes
should connect at the power supply’s ground pin. Separate
traces (or power planes) should run from the power supply to
the supply pins of the digital and analog circuits. Ideally, each
device should have its own power supply trace, but these can be
shared by a number of devices, as long as a single trace is not
used to route current to both digital and analog circuitry.
7
6
20kΩ
4
0.1µF
–VS
+VS
8
5
NC
0.1µF
+VS
VOUT
REF (+)
NC = NO CONNECT
Figure 34. Compensating for Large Sense Resistors
OUTPUT FILTERING
A simple 2-pole, low-pass Butterworth filter can be implemented
using the OP177 after the AD629 to limit noise at the output, as
shown in Figure 35. Table 4 gives recommended component
values for various corner frequencies, along with the peak-topeak output noise for each case.
REF (–)
1
USING A LARGE SENSE RESISTOR
–IN
2
+IN
3
AD629
380kΩ
380kΩ
+VS
8
380kΩ
7
+VS
C1
0.1µF
+VS
R1
6
4
0.1µF
NC
0.1µF
R2
OP177
0.1µF
VOUT
C2
20kΩ
–VS
Insertion of a large value shunt resistance across the input pins,
Pin 2 and Pin 3, will imbalance the input resistor network,
introducing a common-mode error. The magnitude of the error
will depend on the common-mode voltage and the magnitude
of RSHUNT.
21.1kΩ
5
REF (+)
–VS
00783-035
0.1µF 0.1µF
00783-034
ANALOG POWER
SUPPLY
–5V
+5V
GND
NC = NO CONNECT
Figure 35. Filtering of Output Noise Using a 2-Pole Butterworth Filter
Table 4. Recommended Values for 2-Pole Butterworth Filter
Corner Frequency
R1
R2
C1
C2
Output Noise (p-p)
No Filter
50 kHz
5 kHz
500 Hz
50 Hz
2.94 kΩ ± 1%
2.94 kΩ ± 1%
2.94 kΩ ± 1%
2.7 kΩ ± 10%
1.58 kΩ ± 1%
1.58 kΩ ± 1%
1.58 kΩ ± 1%
1.5 kΩ ± 10%
2.2 nF ± 10%
22 nF ± 10%
220 nF ± 10%
2.2 μF ± 20%
1 nF ± 10%
10 nF ± 10%
0.1 μF ± 10%
1 μF ± 20%
3.2 mV
1 mV
0.32 mV
100 μV
32 μV
Rev. B | Page 11 of 16
AD629
OUTPUT CURRENT AND BUFFERING
ERROR BUDGET ANALYSIS EXAMPLE 1
The AD629 is designed to drive loads of 2 kΩ to within 2 V of
the rails but can deliver higher output currents at lower output
voltages (see Figure 15). If higher output current is required, the
output of the AD629 should be buffered with a precision op amp,
such as the OP113, as shown in Figure 36. This op amp can swing
to within 1 V of either rail while driving a load as small as 600 Ω.
In the dc application that follows, the 10 A output current from
a device with a high common-mode voltage (such as a power
supply or current-mode amplifier) is sensed across a 1 Ω shunt
resistor (see Figure 38). The common-mode voltage is 200 V,
and the resistor terminals are connected through a long pair of
lead wires located in a high noise environment, for example,
50 Hz/60 Hz, 440 V ac power lines. The calculations in Table 5
assume an induced noise level of 1 V at 60 Hz on the leads, in
addition to a full-scale dc differential voltage of 10 V. The error
budget table quantifies the contribution of each error source.
Note that the dominant error source in this example is due to
the dc common-mode voltage.
1
–IN
+IN
2
3
21.1kΩ
AD629
380kΩ
380kΩ
+VS
8
380kΩ
NC
0.1µF
7
0.1µF
6
OP113
0.1µF
4
5
REF (+)
VOUT
0.1µF
–VS
NC = NO CONNECT
OUTPUT
CURRENT
00783-036
–VS
20kΩ
Figure 36. Output Buffering Application
–IN
2
+IN
3
VREF
AD629
380kΩ
380kΩ
380kΩ
380kΩ
8
NC
+VS
7
0.1µF
+IN
60Hz
POWER LINE
–VS
380kΩ
6
20kΩ
4
5
VOUT
REF (+)
0.1µF
NC = NO CONNECT
Figure 38. Error Budget Analysis Example 1: VIN = 10 V Full-Scale,
VCM = 200 V DC, RSHUNT = 1 Ω, 1 V p-p, 60 Hz Power-Line Interference
7
NC
+VS
0.1µF
VOUT
6
20kΩ
4
AD629
+VS
8
380kΩ
2
21.1kΩ
5
REF (+)
00783-037
THERMOCOUPLE
21.1kΩ
–IN
3
While low level signals can be connected directly to the –IN and
+IN inputs of the AD629, differential input signals can also be
connected, as shown in Figure 37, to give a precise gain of 19.
However, large common-mode voltages are no longer permissible.
Cold junction compensation can be implemented using a
temperature sensor, such as the AD590.
1
1
1Ω
SHUNT
A GAIN OF 19 DIFFERENTIAL AMPLIFIER
REF (–)
REF (–)
10 AMPS
200V CMDC
TO GROUND
00783-038
REF (–)
NC = NO CONNECT
Figure 37. A Gain of 19 Thermocouple Amplifier
Table 5. AD629 vs. INA117 Error Budget Analysis Example 1 (VCM = 200 V dc)
Error Source
ACCURACY, TA = 25°C
Initial Gain Error
Offset Voltage
DC CMR (Over Temperature)
AD629
INA117
Error, ppm of FS
AD629
INA117
(0.0005 × 10)/10 V × 106
(0.001 V/10 V) × 106
(224 × 10-6 × 200 V)/10 V × 106
(0.0005 × 10)/10 V × 106
(0.002 V/10 V) × 106
(500 × 10-6 × 200 V)/10 V × 106
Total Accuracy Error
500
100
4480
5080
500
200
10,000
10,700
TEMPERATURE DRIFT (85°C)
Gain
Offset Voltage
10 ppm/°C × 60°C
(20 μV/°C × 60°C) × 106/10 V
10 ppm/°C × 60°C
(40 μV/°C × 60°C) × 106/10 V
Total Drift Error
600
120
720
600
240
840
RESOLUTION
Noise, Typical, 0.01 Hz to 10 Hz, μV p-p
CMR, 60 Hz
Nonlinearity
15 μV/10 V × 106
(141 × 10-6 × 1 V)/10 V × 106
(10-5 × 10 V)/10 V × 106
25 μV/10 V × 106
(500 × 10-6 × 1 V)/10 V × 106
(10-5 × 10 V)/10 V × 106
Total Resolution Error
Total Error
2
14
10
26
5826
3
50
10
63
11,603
Rev. B | Page 12 of 16
AD629
ERROR BUDGET ANALYSIS EXAMPLE 2
OUTPUT
CURRENT
REF (–)
10 AMPS
±100V AC CM
TO GROUND
1
–IN
2
21.1kΩ
AD629
380kΩ
380kΩ
8
NC
+VS
7
0.1µF
1Ω
SHUNT
+IN
3
60Hz
POWER LINE
380kΩ
6
20kΩ
–VS
4
5
VOUT
REF (+)
00783-039
This application is similar to the previous example except
that the sensed load current is from an amplifier with an ac
common-mode component of ±100 V (frequency = 500 Hz)
present on the shunt (see Figure 39). All other conditions are
the same as before. Note that the same kind of power-line
interference can happen as detailed in Example 1. However,
the ac common-mode component of 200 V p-p coming from
the shunt is much larger than the interference of 1 V p-p;
therefore, this interference component can be neglected.
0.1µF
NC = NO CONNECT
Figure 39. Error Budget Analysis Example 2: VIN = 10 V Full-Scale,
VCM = ±100 V at 500 Hz, RSHUNT =1 Ω
Table 6. AD629 vs. INA117 AC Error Budget Example 2 (VCM = ±100 V @ 500 Hz)
Error Source
ACCURACY, TA = 25°C
Initial Gain Error
Offset Voltage
AD629
INA117
Error, ppm of FS
AD629
INA117
(0.0005 × 10)/10 V × 106
(0.001 V/10 V) × 106
(0.0005 × 10)/10 V × 106
(0.002 V/10 V) × 106
Total Accuracy Error
500
100
600
500
200
700
TEMPERATURE DRIFT (85°C)
Gain
Offset Voltage
10 ppm/°C × 60°C
(20 μV/°C × 60°C) × 106/10 V
10 ppm/°C × 60°C
(40 μV/°C × 60°C) × 106/10 V
Total Drift Error
600
120
720
600
240
840
RESOLUTION
Noise, Typical, 0.01 Hz to 10 Hz, μV p-p
CMR, 60 Hz
Nonlinearity
AC CMR @ 500 Hz
15 μV/10 V × 106
(141 × 10-6 × 1 V)/10 V × 106
(10-5 × 10 V)/10 V × 106
(141 × 10-6 × 200 V)/10 V × 106
25 μV/10 V × 106
(500 × 10-6 × 1 V)/10 V × 106
(10-5 × 10 V)/10 V × 106
(500 × 10-6 × 200 V)/10 V × 106
Total Resolution Error
Total Error
2
14
10
2820
2846
4166
3
50
10
10,000
10,063
11,603
Rev. B | Page 13 of 16
AD629
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
1
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070606-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 40. 8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
⋅ 45°
0.25 (0.0099)
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 41. 8-Lead Standard Small Outline Package [SOIC_N]
(R-8)
Dimensions shown in millimeters and (inches)
Rev. B | Page 14 of 16
012407-A
4.00 (0.1574)
3.80 (0.1497)
AD629
ORDERING GUIDE
Model
AD629AN
AD629ANZ 1
AD629AR
AD629AR-REEL
AD629AR-REEL7
AD629ARZ1
AD629ARZ-RL1
AD629ARZ-R71
AD629BN
AD629BNZ1
AD629BR
AD629BR-REEL
AD629BR-REEL7
AD629BRZ1
AD629BRZ-RL1
AD629BRZ-R71
AD629-EVAL
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
8-Lead PDIP
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces
8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces
8-Lead PDIP
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces
8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces
8-Lead SOIC_N
8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces
8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces
Evaluation Board
Z = RoHS compliant part.
Rev. B | Page 15 of 16
Package Option
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
AD629
NOTES
©1999-2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00783-0-2/07(B)
Rev. B | Page 16 of 16