ON MC74HCT245AN Octal 3-state noninverting bus transceiver with lsttl compatible input Datasheet

MC74HCT245A
Octal 3-State Noninverting
Bus Transceiver with LSTTL
Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT245A is identical in pinout to the LS245. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High Speed CMOS inputs.
The MC74HCT245A is a 3–state noninverting transceiver that is
used for 2–way asynchronous communication between data buses.
The device has an active–low Output Enable pin, which is used to
place the I/O ports into high–impedance states. The Direction control
determines whether data flows from A to B or from B to A.
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 304 FETs or 76 Equivalent Gates
A2
A3
A
DATA
PORT
A4
A5
A6
A7
A8
DIRECTION
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
1
Design Criteria
20
MC74HCT245AN
AWLYYWW
1
20
1
20
1
SOIC WIDE–20
DW SUFFIX
CASE 751D
HCT245A
AWLYYWW
1
HCT
245A
ALYW
TSSOP–20
DT SUFFIX
CASE 948G
20
B2
B3
B
DATA
PORT
B4
B5
B6
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
B7
DIRECTION
1
20
VCC
B8
A1
2
19
OUTPUT ENABLE
A2
3
18
B1
A3
4
17
B2
A4
5
16
B3
A5
6
15
B4
Value
Units
Internal Gate Count*
76
ea
A6
7
14
B5
Internal Gate Propagation Delay
1.0
ns
A7
8
13
B6
5.0
µW
A8
9
12
B7
0.005
pJ
GND
10
11
B8
Internal Gate Power Dissipation
Speed Power Product
20
1
PIN 20 = VCC
PIN 10 = GND
19
20
PDIP–20
N SUFFIX
CASE 738
B1
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OUTPUT ENABLE
MARKING
DIAGRAMS
1
LOGIC DIAGRAM
A1
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*Equivalent to a two–input NAND gate.
FUNCTION TABLE
ORDERING INFORMATION
Control Inputs
Device
Output
Enable
Direction
L
L
L
H
X = Don’t Care
Operation
MC74HCT245AN
Package
Shipping
PDIP–20
1440 / Box
Data Transmitted from Bus B to Bus A
MC74HCT245ADW
H
Data Transmitted from Bus A to Bus B
MC74HCT245ADWR2 SOIC–WIDE
X
Buses Isolated (High–Impedance State)
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 8
1
SOIC–WIDE
38 / Rail
1000 / Reel
MC74HCT245ADT
TSSOP–20
75 / Rail
MC74HCT245ADTR2
TSSOP–20
2500 / Reel
Publication Order Number:
MC74HCT245A/D
MC74HCT245A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
VIH
Minimum High–Level Input
Voltage
VIL
Maximum Low–Level Input
Voltage
VCC
V
– 55 to
25_C
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL
|Iout|
6.0 mA
4.5
5.5
Test Conditions
85_C
125_C
2.0
2.0
2.0
2.0
2.0
2.0
V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Unit
VOH
Minimum High–Level Output
Voltage
4.5
3.98
3.84
3.7
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.4
Iin
ICC
Maximum Input Leakage Current
Vin = VIH or VIL
|Iout|
6.0 mA
Vin = VCC or GND, Pins 1 or 19
5.5
± 0.1
± 1.0
± 1.0
µA
5.5
4.0
40
160
µA
IOZ
Maximum Three–State
Leakage Current
5.5
± 0.5
± 5.0
± 10
µA
∆ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND, I/O Pins
V
Vin = 2.4 V, Any One Input
≥ –55_C
25_C to 125_C
Vin = VCC or GND,
GND Other In
Inputs
uts
lout = 0 µA
5.5
mA
2.9
2.4
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
Additional Quiescent Supply
Current
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2
MC74HCT245A
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AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
– 55 to
25_C
Parameter
85_C
125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, A to B or B to A
(Figures 1 and 3)
22
28
33
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Direction or Output Enable to A or B
(Figures 2 and 4)
30
36
42
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to A or 8
(Figures 2 and 4)
30
36
42
ns
tTLH,
tTHL
Maximum Output Transition Time. any Output
(Figures 1 and 3)
12
15
18
ns
Maximum Input Capacitance (Pin 1 or 19)
10
10
10
pF
Maximum Three–State I/O Capacitance, (I/O in High–Impedance
State)
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Enabled Output)*
97
pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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3
MC74HCT245A
SWITCHING WAVEFORMS
3.0 V
DIRECTION
1.3 V
1.3 V
GND
3.0 V
tr
tf
INPUT
A OR B
3.0 V
2.7 V
1.3 V
0.3 V
OUTPUT
ENABLE
GND
tPZL
tPLZ
HIGH
IMPEDANCE
GND
tPLH
tPHL
A OR B
90%
1.3 V
10%
OUTPUT
B OR A
1.3 V
1.3 V
tPZH
A OR B
tTHL
tTLH
10%
VOL
90%
VOH
1.3 V
Figure 1.
HIGH
IMPEDANCE
Figure 2.
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
tPHZ
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
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4
MC74HCT245A
EXPANDED LOGIC DIAGRAM
A1
2
18
A2
3
17
A3
A4
B
DATA
PORT
OUTPUT ENABLE
B7
9
11
DIRECTION
B6
8
12
A8
B5
7
13
A7
B4
6
14
A6
B3
5
15
A5
B2
4
16
A
DATA
PORT
B1
1
19
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5
B8
MC74HCT245A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
T B
M
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
q
A
20
X 45 _
M
E
h
0.25
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
DIM
A
A1
B
C
D
E
e
H
h
L
q
C
T
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6
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74HCT245A
PACKAGE DIMENSIONS
20X
0.15 (0.006) T U
TSSOP–20
DT SUFFIX
CASE 948E–02
ISSUE A
K REF
0.10 (0.004)
S
M
T U
S
V
S
K
K1
2X
L/2
20
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
–U–
L
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
M
A
–V–
N
F
DETAIL E
–W–
C
D
G
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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7
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
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MC74HCT245A
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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