IRF IRF7811APBF Hexfet power mosfet Datasheet

PD - 95264A
IRF7811APbF
HEXFET® Power MOSFET
Applications
High Frequency Synchronous Buck
Converters for Computer Processor Power
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
l 100% RG Tested
l Lead-Free
l
VDSS
l
l
l
Very Low RDS(on) at 4.5V VGS
Ultra-Low Gate Impedance
Fully Characterized Avalanche Voltage
and Current
Qg
12mΩ
17nC
28V
1
8
S
2
7
S
3
6
4
5
S
Benefits
RDS(on) max
G
A
A
D
D
D
D
SO-8
Top View
Absolute Maximum Ratings
Symbol
Parameter
ID @ TA = 25°C
Continuous Drain Current, VGS @ 10V
ID @ TA = 70°C
IDM
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
PD @TA = 25°C
Power Dissipation
PD @TA = 70°C
Power Dissipation
VGS
Linear Derating Factor
Gate-to-Source Voltage
TJ
Operating Junction and
TSTG
Storage Temperature Range
f
f
Max
c
Smoldering Temperature, for 10 seconds
Units
f
9.1 f
11
A
91
2.5
W
1.6
0.02
±12
W/°C
V
-55 to + 150
°C
300 (1.6mm from case)
Thermal Resistance
Symbol
RθJL
RθJA
Parameter
g
Junction-to-Ambient fg
Junction-to-Drain Lead
Notes  through
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Typ
Max
–––
20
–––
50
Units
°C/W
are on page 10
1
1/11/05
IRF7811APbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
BV DSS
Drain-to-Source Breakdown Voltage
∆ΒV DSS/∆T J
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
28
–––
–––
–––
0.025
–––
–––
8.7
10
–––
10
12
V
Conditions
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, I D = 1mA
mΩ
f
f
VGS = 10V, ID = 11A
VGS = 4.5V, ID = 9.0A
VGS(th)
Gate Threshold Voltage
1.0
–––
3.0
V
∆V GS(th)
Gate Threshold Voltage Coefficient
–––
-4.0
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
VDS = VGS , ID = 250µA
VDS = 28V, V GS = 0V
–––
–––
150
VDS = 24V, V GS = 0V, T J = 100°C
Gate-to-Source Forward Leakage
–––
–––
100
VGS = 12V
Gate-to-Source Reverse Leakage
–––
–––
-100
gfs
Forward Transconductance
28
–––
–––
Qg
Total Gate Charge
–––
17
26
Qgs1
Pre-Vth Gate-Source Charge
–––
3.3
–––
VDS = 15V
Qgs2
Post-Vth Gate-Source Charge
–––
1.3
–––
VGS = 4.5V
Qgd
Gate-to-Drain Charge
–––
4.7
–––
ID = 9.0A
Qgodr
Gate Charge Overdrive
–––
7.2
–––
See Fig. 16
Qsw
Switch Charge (Qgs2 + Qgd )
–––
6.0
–––
Qoss
Output Charge
–––
24
–––
nC
RG
Gate Resistance
0.9
–––
3.7
Ω
td(on)
Turn-On Delay Time
–––
7.5
–––
VDD = 15V, V GS = 4.5V
tr
Rise Time
–––
4.1
–––
ID = 9.0A
td(off)
Turn-Off Delay Time
–––
19
–––
tf
Fall Time
–––
6.5
–––
Ciss
Input Capacitance
–––
1760
–––
Coss
Output Capacitance
–––
960
–––
Crss
Reverse Transfer Capacitance
–––
54
–––
IGSS
nA
S
nC
ns
VGS = -12V
VDS = 15V, I D = 9.0A
VDS = 16V, V GS = 0V
f
Clamped Inductive Load
VGS = 0V
pF
VDS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
Symbol
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
c
d
Typ.
Max.
Units
–––
58
mJ
–––
9.0
A
Diode Characteristics
Symbol
Parameter
Continuous Source Current
IS
Min. Typ. Max. Units
–––
–––
11
(Body Diode)
ISM
A
Pulsed Source Current
(Body Diode)
c
–––
–––
91
–––
0.8
1.0
–––
0.66
–––
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 9.0A, V GS = 0V
e
e
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
–––
72
110
ns
TJ = 125°C, IS = 9.0A, V GS = 0V
TJ = 25°C, IF = 9.0A, V R = 15V
Qrr
trr
Reverse Recovery Charge
–––
93
140
nC
di/dt = 100A/µs
Reverse Recovery Time
–––
73
110
ns
TJ = 125°C, IF = 9.0A, V R = 15V
Qrr
Reverse Recovery Charge
–––
100
150
nC
di/dt = 100A/µs
2
V
e
e
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IRF7811APbF
100
10
1
0.1
20µs PULSE WIDTH
Tj = 25°C
1.5V
0.01
0.1
1
10
10
1
1.5V
20µs PULSE WIDTH
Tj = 150°C
0.1
0.1
100
1
10
100
VDS , Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100.00
2.0
T J = 150°C
10.00
1.00
T J = 25°C
0.10
VDS = 15V
20µs PULSE WIDTH
0.01
ID = 11A
VGS = 10V
1.5
(Normalized)
RDS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current (Α)
VGS
10V
4.5V
3.5V
2.7V
2.5V
2.0V
1.8V
BOTTOM 1.5V
TOP
10V
4.5V
3.5V
2.7V
2.5V
2.0V
1.8V
BOTTOM 1.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
100
VGS
1.0
0.5
1.4
1.8
2.2
2.6
3.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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3.4
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF7811APbF
12
100000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
C, Capacitance (pF)
VGS , Gate-to-Source Voltage (V)
Coss
10000
ID= 9.0A
= Cds + Cgd
Ciss
1000
Coss
100
Crss
VDS=1 5V
10
8
6
4
2
0
10
0
1
10
100
10
20
30
40
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100.0
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100
10.0
T J = 150°C
T J = 25°C
1.0
10
1msec
1
VGS = 0V
0.1
0.1
0.2
0.4
0.6
0.8
1.0
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1.2
100µsec
10msec
Tc = 25°C
Tj = 150°C
Single Pulse
0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF7811APbF
12
VDS
ID , Drain Current (A)
10
VGS
D.U.T.
RG
8
RD
+
-V DD
10V
6
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
4
Fig 10a. Switching Time Test Circuit
2
VDS
90%
0
25
50
75
100
125
150
T J , Junction Temperature (°C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Ambient Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJA )
100
D = 0.50
0.20
10
0.10
0.05
PDM
0.02
1
t1
0.01
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJA + TA
SINGLE PULSE
(THERMAL RESPONSE)
0.1
0.00001
0.0001
0.001
0.01
0.1
1
10
100
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
R DS(on) , Drain-to -Source On Resistance ( Ω)
RDS (on) , Drain-to-Source On Resistance ( Ω)
IRF7811APbF
0.013
0.011
VGS = 4.5V
0.009
VGS = 10V
0.007
0.005
0
10
20
30
40
50
0.03
0.02
ID = 9.0A
0.01
0.00
2.0
60
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
VGS, Gate -to -Source Voltage (V)
ID , Drain Current (A)
Fig 12. On-Resistance Vs. Drain Current
Fig 13. On-Resistance Vs. Gate Voltage
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
140
EAS, Single Pulse Avalanche Energy (mJ)
+
V
- DS
D.U.T.
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 14. Basic Gate Charge Test Circuit
15V
V(BR)DSS
tp
L
VDS
DRIVER
TOP
120
BOTTOM
ID
4.0A
7.2A
9.0A
100
80
60
40
20
0
D.U.T
RG
IAS
20V
I AS
tp
+
V
- DD
0.01Ω
Fig 15a&b. Unclamped Inductive Test circuit
and Waveforms
6
25
50
75
100
125
150
A
Starting TJ , Junction Temperature (°C)
Fig 15c. Maximum Avalanche Energy
Vs. Drain Current
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IRF7811APbF
D.U.T
Driver Gate Drive
P.W.
+
ƒ
+
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
D=
Period
VDD
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRF7811APbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgs 2
⎞
⎞ ⎛
Qgd
+⎜I ×
× Vin × f ⎟ + ⎜ I ×
× Vin × f ⎟
ig
ig
⎠ ⎝
⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRF7811APbF
SO-8 Package Outline
Dimensions are shown in millimeters (inches)
D
5
A
8
7
6
5
6
H
0.25 [.010]
1
2
3
A
4
MAX
MIN
.0532
.0688
1.35
1.75
A1 .0040
.0098
0.10
0.25
b
.013
.020
0.33
0.51
c
.0075
.0098
0.19
0.25
D
.189
.1968
4.80
5.00
E
.1497
.1574
3.80
4.00
e
.050 BASIC
e1
6X
e
e1
C
1.27 BASIC
.025 BASIC
0.635 B ASIC
H
.2284
.2440
5.80
6.20
K
.0099
.0196
0.25
0.50
L
.016
.050
0.40
1.27
y
0°
8°
0°
8°
y
0.10 [.004]
0.25 [.010]
MAX
K x 45°
A
8X b
MILLIMETERS
MIN
A
E
INCHES
DIM
B
A1
8X L
8X c
7
C A B
F OOTPRINT
NOT ES :
1. DIMENS IONING & TOLERANCING PER ASME Y14.5M-1994.
8X 0.72 [.028]
2. CONT ROLLING DIMENS ION: MILLIMET ER
3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES].
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS -012AA.
5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .
MOLD PROTRUS IONS NOT TO EXCEED 0.15 [.006].
6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .
MOLD PROTRUS IONS NOT TO EXCEED 0.25 [.010].
6.46 [.255]
7 DIMENS ION IS T HE LENGT H OF LEAD FOR SOLDERING TO
A S UBST RAT E.
3X 1.27 [.050]
8X 1.78 [.070]
SO-8 Part Marking
EXAMPLE: T HIS IS AN IRF7101 (MOSFET )
INT ERNAT IONAL
RECT IFIER
LOGO
XXXX
F7101
DAT E CODE (YWW)
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
Y = LAS T DIGIT OF T HE YEAR
WW = WEEK
A = AS S EMBLY S IT E CODE
LOT CODE
PART NUMBER
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9
IRF7811APbF
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 1.4mH
RG = 25Ω, I AS = 9.0A.
ƒ Pulse width ≤ 300µs; duty cycle ≤ 2%.
„ When mounted on 1 inch square copper board
Rθ is measured at TJ approximately at 90°C
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 01/05
10
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