IDT ICS580-01 Glitch-free clock mulitplexer Datasheet

DATASHEET
ICS580-01
GLITCH-FREE CLOCK MULITPLEXER
Description
Features
The ICS580-01 is a clock multiplexer (mux) designed to
switch between two clock sources with no glitches or short
pulses. The operation of the mux is controlled by an input
pin but the part can also be configured to switch
automatically if one of the input clocks stops. The part also
provides clock detection by reporting when an input clock
has stopped.
•
•
•
•
•
•
•
•
•
For a clock mux with zero delay and smooth switching, see
either the ICS581-01 or the ICS581-02.
•
16-pin SOIC and 16-pin TSSOP packages available
Pb (lead) free package
No short pulses or glitches on output
Operates from 2 to 220 MHz
Low skew outputs
Clock detect feature
Ideal for systems with back-up or redundant clocks
Selectable timeouts for clock detection
Separate supply voltages allow power supply voltage
translation
Operates from 2.5 V to 5 V
Block Diagram
VDDC
VDDI
CLK1
INB
1
OE1
0
INA
CLK2
OE2
SELB
Transition
Detector
NO_INB
OE4
Transition
Detector
NO_INA
OE3
DIV
Timer
GND
IDT™ / ICS™ GLITCH-FREE CLOCK MULITPLEXER
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GLITCH-FREE CLOCK MULITPLEXER
CLOCK MULTIPLEXER
Pin Assignment
Timeout Selection
SELB
1
16
OE1
DIV
2
15
VDDC
VDDI
3
14
CLK1
INA
4
13
CLK2
INB
5
12
NO_INA
GND
6
11
NO_INB
OE4
7
10
GND
OE3
8
9
OE2
DIV
Nominal Timeout
0
600 ns
1
75 ns
16 pin (150 mil) SOIC
SELB
1
16
OE1
DIV
2
15
VDDC
VDDI
3
14
CLK1
INA
4
13
CLK2
INB
5
12
NO_INA
GND
6
11
NO_INB
OE4
7
10
GND
OE3
8
9
OE2
16-pin TSSOP
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CLOCK MULTIPLEXER
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
SELB
Input
Mux select. Selects INB when high. Internal pull-up.
2
DIV
Input
Time out select. See table above. Internal pull-up.
3
VDDI
Power
Supply for input clocks only. Can be higher than VDDC.
4
INA
Input
Input Clock A.
5
INB
Input
Input Clock B.
6
GND
Power
Connect to ground.
7
OE4
Input
Output enable. Tri-states NO_INB when low. Internal pull-up.
8
OE3
Input
Output enable. Tri-states NO_INA when low. Internal pull-up.
9
OE2
Input
Output enable. Tri-states CLK2 when low. Internal pull-up.
10
GND
Power
Connect to ground.
11
NO_INB
Output
Goes high when clock on INB stops.
12
NO_INA
Output
Goes high when clock on INA stops.
13
CLK2
Output
Clock 2 output. Low skew compared to CLK1.
14
CLK1
Output
Clock 1 output. Low skew compared to CLK2.
15
VDDC
Power
Main chip supply. Output clocks amplitude will match this VDD.
16
OE1
Input
Output enable. Tri-states CLK1 when low. Internal pull-up.
IDT™ / ICS™ GLITCH-FREE CLOCK MULITPLEXER
Pin Description
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GLITCH-FREE CLOCK MULITPLEXER
CLOCK MULTIPLEXER
Device Operation
The ICS580-01 consists of a glitch free mux between INA and INB controlled by SELB. The device is designed to
switch between two clocks, whether running or not. In the first example, clocks are running on both INA and INB.
When SELB changes, the output clock goes low after three cycles of the output clock (nominally). The output then
stays low for three cycles of the new input clock (nominally) and then starts with the new input clock. This is shown
in Figure 1.
Figure 1
INA
INB
SELB
CLK1, 2
In the second example, one of the inputs was selected and running but has since stopped (either high or low). This
is indicated by either NO_INA or NO_INB going high depending on whether INA or INB has stopped. These signals
go high following a selectable time-out period after the clock has stopped. The timeout period is determined by the
DIV input in. The SELB pin is now changed to select the new input clock which is running. The output clock
immediately goes low and stays low for three cycles of the new input clock and then starts with the new input clock.
Figure 2 shows an example of this
Figure 2
INA
INB
SELB
Timeout
NO_INA
CLK1, 2
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CLOCK MULTIPLEXER
Application Example
In the third example, the ICS580-01 is configured to automatically switch clocks when an input stops. The clock that
could stop is connected to INA while the backup clock (always running) is connected to INB. The output NO_INA is
connected to SELB. This means that when the clock on INA stops, NO_INA goes high selecting the clock on INB
which is muxed to the output after three cycles. When the clock on INA restarts, NO_INA immediately goes low,
selecting the clock on INA. The output then switches in the manner described in the first example.
The circuit diagram in Figure 3 shows a typical connection for this example. Note that CLK2 and NO_INB are
unused and are disabled by grounding OE2 and OE4. A 33Ω series termination resistor is used on the clock output
and two decoupling capacitors of 0.01µF are used. All other inputs are left floating and are therefore pulled high by
the on-chip pull-ups.
VDD
SELB
DIV
0.01µF
VDDI
OE1
VDDC
CLK1
Normal Clock
INA
CLK2
Backup Clock
INB
NO_INA
GND
NO_INB
OE4
GND
OE3
OE2
0.01µF
Output Clock
33Ω
Output Enable
Each output has a dedicated output enable pin. If an output is unused, it should be tri-stated by tying the
appropriate output enable pin to ground.
External Components
The ICS580-01 requires two 0.01µF decoupling capacitors, one between VDDI and GND and one between VDDC
and GND. Series termination resistors of 33Ω can be used on CLK1 and CLK2.
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CLOCK MULTIPLEXER
Split Power Supplies
The VDDI pin provides the power for the INA and INB input buffers only. All the other inputs and the rest of the chip
are connected to VDDC. This allows for supply voltage translation. For example, INA and INB could be 5V clocks
(VDDI = 5V) and the rest of the chip could use a 3.3V supply on VDDC giving 3.3V output clocks. For correct
operation VDDI must always be greater than or equal to VDDC.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS580-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
0 to +70° C
Ambient Operating Temperature
-40 to +85° C
Storage Temperature
-65 to +150° C
Junction Temperature
125° C
Soldering Temperature
260° C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
°C
Ambient Operating Temperature
-40
+85
°C
Power Supply Voltage (measured in respect to GND)
+2.5
+5.5
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C
Parameter
Operating Voltage
Symbol
Conditions
Min.
Typ.
Max.
Units
VDDC
2.5
5.5
V
VDDI
VDDC
5.5
V
Supply Current
IDD
50 MHz, no load
Input High Voltage
VIH
Non-clock inputs
Input Low Voltage
VIL
Non-clock inputs
Input High Voltage
VIH
INA and INB only
Note 3
IDT™ / ICS™ GLITCH-FREE CLOCK MULITPLEXER
6
2
(VDDC/2)+1
6
mA
VDDC
V
0.8
V
VDDI
V
ICS580-01
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GLITCH-FREE CLOCK MULITPLEXER
Parameter
CLOCK MULTIPLEXER
Symbol
Conditions
Input Low Voltage
VIL
INA and INB only
Note 3
Input Capacitance
CIN
Output High Voltage
VOH
IOH = -12 mA
Output Low Voltage
VOL
IOL = 12 mA
Short Circuit
Current
IOS
On-chip pull-up
Resistor
RPU
Min.
Typ.
Max.
Units
(VDDC/2)-1
V
4
pF
VDDC-0.5
V
0.5
Non-clock inputs
Pull-up to VDDC
V
±70
mA
250
kΩ
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C
Parameter
Input Frequency
INA and INB, Note 1
Symbol
fIN
Propagation Delay
INA or INB to output
Conditions
Min.
Typ.
Max.
Units
VDDC = 5V
1/timeout
270
MHz
VDDC = 3.3V
1/timeout
220
MHz
VDDC = 2.7V
1/timeout
180
MHz
VDDC = 5V
4
8
ns
VDDC = 3.3V
5
10
ns
VDDC = 2.7V
6
12
ns
VDDI = 5V
175
350
750
ns
VDDI = 3.3V
500
1000
2000
ns
VDDI = 2.7V
750
1500
3000
ns
VDDI = 5V
20
40
80
ns
VDDI = 3.3V
55
110
210
ns
VDDI = 2.7V
100
200
400
ns
Output Clock Rise Time
1.5
ns
Output Clock Fall Time
1.5
ns
250
ps
Transition Detector
Timeout, DIV = 0
Transition Detector
Timeout, DIV = 1
Output Clock Skew
CLK1 to CLK2
Note 2
-250
0
Note 1. Frequencies less than the minimum may cause a timeout which will not guarantee glitch-free switching unless the clock
is actually stopped.
Note 2: Assumes identically loaded outputs with identical rise times, measured at VDD/2.
Note 3: Output duty cycle is set by duty cycle of input clock at VDDC/2.
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CLOCK MULTIPLEXER
Thermal Characteristics (16-pin SOIC)
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Symbol
Conditions
Min.
Typ.
Max. Units
θJA
Still air
120
° C/W
θJA
1 m/s air flow
115
° C/W
θJA
3 m/s air flow
105
° C/W
58
° C/W
θJC
Thermal Characteristics (16-pin TSSOP)
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
IDT™ / ICS™ GLITCH-FREE CLOCK MULITPLEXER
Symbol
Conditions
Min.
Typ.
Max. Units
θJA
Still air
78
° C/W
θJA
1 m/s air flow
70
° C/W
θJA
3 m/s air flow
68
° C/W
37
° C/W
θJC
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CLOCK MULTIPLEXER
Marking Diagram (ICS580M-01LF)
16
Marking Diagram (ICS580G-01LF)
16
9
580G01LF
######
YYWW
580M01LF
######
YYWW
1
8
1
Marking Diagram (ICS580M-01ILF)
16
8
Marking Diagram (ICS580G-01ILF)
16
9
9
580G01IL
######
YYWW
580M01ILF
######
YYWW
1
9
8
1
8
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “LF” or “L” denotes Pb (lead) free package.
4. “I” indicates industrial grade.
4. Bottom marking: country of origin if not USA.
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CLOCK MULTIPLEXER
Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters
Symbol
E
Min
A
A1
B
C
D
E
e
H
h
L
α
H
INDEX
AREA
1 2
D
A
Inches
Max
Min
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
9.80
10.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
Max
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.3859
.3937
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0°
8°
h x 45
A1
C
-Ce
B
SEATING
PLANE
L
.10 (.004)
IDT™ / ICS™ GLITCH-FREE CLOCK MULITPLEXER
C
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CLOCK MULTIPLEXER
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
16
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
INDEX
AREA
1 2
D
Min
Inches
Max
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Min
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
A
A2
A1
c
-Ce
b
SEATING
PLANE
L
aaa C
IDT™ / ICS™ GLITCH-FREE CLOCK MULITPLEXER
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CLOCK MULTIPLEXER
Ordering Information
Part / Order Number
Shipping Packaging
Package
Temperature
580M-01LF
Tubes
16-pin SOIC
0 to +70° C
580M-01LFT
Tape and Reel
16-pin SOIC
0 to +70° C
Tubes
16-pin SOIC
-40 to +85° C
Tape and Reel
16-pin SOIC
-40 to +85° C
580M-01ILF
Marking
see page 9
580M-01ILFT
Tubes
16-pin TSSOP
0 to +70° C
580G-01LFT
Tape and Reel
16-pin TSSOP
0 to +70° C
580G-01ILF
Tubes
16-pin TSSOP
-40 to +85° C
580G-01ILFT
Tape and Reel
16-pin TSSOP
-40 to +85° C
580G-01LF
see page 9
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ GLITCH-FREE CLOCK MULITPLEXER
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CLOCK MULTIPLEXER
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