LTC7106 A 7-Bit Current DAC with PMBus Interface FEATURES DESCRIPTION ±0.8% IDAC Positive Output Current Accuracy (Over Temp) nn ±1.5% I DAC Negative Output Current Accuracy (Over Temp) nn PMBus/I2C Compliant Serial Interface nn Input Voltage Range: 2.5V to 5.5V nn High Impedance at IDAC Output When Disabled nn Wide IDAC Operation Voltage (0.4V to 2.0V) nn 7-Bit Programmable DAC Output Current for DC/DC VOUT Control nn Wide Range IDAC Output Current: ±16μA to ±256μA nn Programmable Slew Rate: 500ns ~ 3ms per Bit nn Available in a 10-Lead (3mm × 2mm) DFN Package The LTC®7106 is a precision, PMBus controlled, bidirectional current digital-to-analog converter that adjusts the output voltage of any conventional VFB referenced regulator. The LTC7106 can work with the vast majority of power management controllers or regulators to enable digital control of the output voltage. Internal power-on reset circuitry keeps the DAC output current at zero (high impedance IDAC) until a valid write takes place. Features include a range bit for easy interfacing to almost any impedance resistor divider, and an open-drain GPO output for controlling the Run or Enable pin of the DC/ DC regulator. For most applications, the current DAC error is significantly attenuated with proper design. See more detail about VOUT accuracy in the Applications Information section of this data sheet. The LTC7106 is supported by the ADI LTpowerPlay® development tool with graphical user interface (GUI). nn APPLICATIONS General Purpose Power Systems Telecom Systems nn Industrial Applications nn All registered trademarks and trademarks are the property of their respective owners. nn TYPICAL APPLICATION Margin High and Margin Low L1 VIN SW VIN RFB1 DC/DC VFB CIRCUIT OF FIGURE 11 VOUT VREF C2 330µF (0.4V to 2V) VOUT 5V/DIV IDAC = –40μA IDAC = 0μA RFB2 RUN VOUT = 24V IDAC = 40μA VDD 2.5V TO 5.5V R4 10k SDA PMBus INTERFACE EN 2V/DIV 0μA TO 63μA C1 1µF SCL ALERT 10k R3 10k R2 10k R1 VDD EN GPO 100ms/DIV 7106 TA01b –64μA TO 0μA SDA SCL LTC7106 ALERT IDAC GND ASEL0 ASEL1 7106 TA01a VDD Rev A Document Feedback For more information www.analog.com 1 LTC7106 ABSOLUTE MAXIMUM RATINGS (Note 1) PIN CONFIGURATION All Pins Except GND................................... –0.3V to 6.0V Operating Junction Temperature Range.... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C TOP VIEW SDA 1 10 ASEL1 SCL 2 9 ASEL0 VDD 3 8 GPO ALERT 4 7 EN GND 5 6 IDAC DDB PACKAGE 10-LEAD (3mm × 2mm) PLASTIC DFN θJA = 55°C/W, θJC = 16.8°C/W ORDER INFORMATION http://www.linear.com/product/LTC7106#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC7106EDDB#PBF LTC7106EDDB#TRPBF LHCG 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC7106IDDB#PBF LTC7106IDDB#TRPBF LHCG 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 Rev A For more information www.analog.com LTC7106 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VDD = 3.3V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX VDD Power Supply IQ Supply Quiescent Current EN High 5.5 V 700 1400 μA ISHUTDOWN Supply Quiescent Current EN = 0V 800 μA VUVLO_R Undervoltage Rising Threshold VDD Rising 2.35 V VUVLO_F Undervoltage Falling Threshold VDD Falling 2.15 V VEN_R Enable Rising Threshold VEN Rising VEN_F Enable Falling Threshold VEN Falling Accuracy Full Scale Positive 0.4 ≤ VIDAC ≤ 2V (Note 3) 2.5 1.35 0.8 UNITS V V IDAC_OUT IDAC Full Scale Negative 0.4 ≤ VIDAC ≤ 2V (Note 3) LSB 0.4 ≤ VIDAC ≤ 2V Range = Normal l 62.5 63 63.5 μA Range = Low l 15.5 15.75 16.0 μA Range = High l Range = Normal (0°C to 85°C) 246.7 252.00 255.3 μA –64.64 –64 –63.36 μA Range = Normal l –64.96 –64 –63.04 μA Range = Low l –16.36 –16 –15.64 μA Range = High l –262.50 –256 –249.50 Range = Normal Range = Low Range = High INL 0.4 ≤ VIDAC ≤ 2V DNL IHZ 0.4 ≤ VIDAC ≤ 2V High-Z Current 0.4 ≤ VIDAC ≤ 2V μA 0.25 μA 4 Range = Normal μA 1 μA –1 1 LSB Range = Low –1.5 1.5 LSB Range = High –1.6 1.6 LSB Range = Normal –0.3 0.3 LSB Range = Low –0.5 0.5 LSB Range = High –0.8 0.8 LSB 20 nA 1.4 V 10 pF 0.4 V VEN = 0 l Digital Input: SDA, SCL VIH VIL CPIN 0.8 Input Capacitance V Open-Drain Outputs: ALERTB, GPO, SDA VOL Output Low Voltage ISINK = 3mA Rev A For more information www.analog.com 3 LTC7106 PMBus INTERFACE TIMING CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VDD = 3.3V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSCL Serial Bus Operating Frequency 10 tBUF Bus Free Time Between Stop and Start Condition 1.3 400 kHz µs tHD_SDA Hold Time After (Repeated) Start Condition 0.6 µs tSU_SDA Repeated Start Condition Setup Time 0.6 µs tSU_STO Stop Condition Setup Time 0.6 µs tHD_DAT(OUT) Data Hold Time 300 tHD_DAT(IN) Input Data Hold Time tSU_DAT 900 ns 0 ns Data Setup Time 100 ns tLOW Clock Low Period 1.3 tHIGH Clock High Period 0.6 tTIMEOUT_SMB Stuck PMBus Timer 3 900 IDAC LEAKAGE (nA) IQ (μA) 850 800 750 700 650 600 PIDAC Full Full-Scale vs Temperature PIDAC Scale VS. Temperature 63.500 VEN = 0, OR VID[6:0] = 0 63.400 63.200 63.100 1 63.000 62.900 62.800 0 62.700 550 62.600 –10 30 70 TEMP (°C) 110 150 7106 G01 4 VID[6:0] = 0111111 63.300 2 IDAC IRANGE = NOMINAL ms TA = 25°C, VDD = 3.3V, VIDAC = 1.0V, Range = Normal unless otherwise noted. IDAC Leakage Current vs Temperature IDAC Leakage Current vs. Temp Quiescent Current vs Temperature 500 –50 µs is derated for junction temperatures greater than 125°C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • 55°C/W). Note 3: IDAC is a bidirectional current DAC, controlled by 2’s complementary logic. Under the setting of Range = Normal, IDAC = 63µA for Code = 0111111 provides the maximum source current and IDAC = –64µA for Code = 1000000 provides the maximum sink current. Max sink current generates the Highest VOUT, while Max source current generates the lowest VOUT. See the Operation section for more details. TYPICAL PERFORMANCE CHARACTERISTICS 950 µs 30 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7106 is tested under pulsed load conditions such that TJ ≈ TA. The LTC7106E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7106I is guaranteed over the –40°C to 125°C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime 1000 10000 –1 –50 –5 40 85 TEMPERATURE (°C) 130 7106 G02 62.500 –50 –10 30 70 TEMPERATURE (°C) 110 150 7106 G03 Rev A For more information www.analog.com LTC7106 TYPICAL PERFORMANCE CHARACTERISTICS NIDAC vs Temperature Differential Nonlinearity Integral Nonlinearity Integral Non–Linearity 0.15 0.06 0.12 –63.70 0.02 0.09 –63.80 –0.02 0.06 –63.90 –0.06 0.03 VID[6:0] = 1000000 DNL (LSB) –63.60 –64.00 –64.10 INL (LSB) 0.10 –63.50 IDAC (µA) TA = 25°C, VDD = 3.3V, Range = Normal unless otherwise noted. –0.10 –0.14 0 –0.03 –64.20 –0.18 –0.06 –64.30 –0.22 –0.09 –64.40 –0.26 –0.12 –64.50 –50 –0.30 0 50 TEMPERATURE (°C) 100 150 1 7 0 10 20 7106 G05 7106 G04 Buck Start-Up with IDAC LTC7106 + LTM4636 VOUT = 1V –0.15 13 20 26 32 38 44 51 57 63 CODE 30 40 CODE 50 60 70 7106 G06 Margin High and Margin Low LTC7106 + LTM4636 VOUT = 1V IDAC = –60µA IDAC = –60μA IDAC = 60µA VOUT 0.3V/DIV VOUT 200mV/DIV IDAC = 0μA IDAC = 0µA GPO 5V/DIV 7106 G07 10mV/DIV EN 2V/DIV 100ms/DIV Boost Start-Up with IDAC LTC7106 + LTC3784 VOUT = 24V VIN = 12V IDAC = 60μA 7106 G08 Margin High and Margin Low IDAC = –40μA LTC7106 + LTC3784 IDAC = 0μA IDAC = 40μA VOUT 10V/DIV VOUT 5V/DIV IDAC = 0μA VOUT = 24V IDAC = –40μA IDAC = 0μA IDAC = 40μA GPO 5V/DIV 2ms/DIV 7106 G09 EN 2V/DIV 100ms/DIV 7106 G10 Rev A For more information www.analog.com 5 LTC7106 PIN FUNCTIONS VDD (Pin 3): Input Supply. Bypass this pin to GND with a capacitor (0.1µF to 1µF). GPO (Pin 8): Open-Drain Digital Output. A pull-up resistor to VDD is required. IDAC (Pin 6): Bidirectional Current DAC Output. ALERT (Pin 4): Open-Drain Digital Output. A pull-up resistor to VDD is required. EN (Pin 7): Chip Enable Pin. Current DAC output is in Hi-Z state when EN is Grounded. Do not leave EN floating. SDA (Pin 1): Serial Bus Data Input and Open-Drain Output. A pull-up resistor to VDD is required in the application. SCL (Pin 2): Serial Bus Clock Input. 6 ASEL1/ASEL0 (Pins 10, 9): Serial Bus Address Select Inputs. Each pin has three states (VDD, FLOATING and GND); these two pins provide 9 addresses. GND (Pin 5): Ground. Rev A For more information www.analog.com LTC7106 BLOCK DIAGRAM EN VDD RANGE SDA SLEW RATE VID[6:0] PMBus INTERFACE SCL IDAC 7-BIT IDAC ALERT VREF + – ASEL0 ASEL1 ADDRESS ADC R1 GPO GND 7106 BD Rev A For more information www.analog.com 7 LTC7106 OPERATION The LTC7106 is a PMBus controlled 7-bit D/A converter current source. Through its PMBus interface, the LTC7106 receives a 7-bit DAC code and converts this value to a bidirectional analog output current through the pin IDAC. By connecting IDAC to the feedback node of a voltage regulator, IDAC can change the output voltage of the regulator with the equation: VOUT = VREF • (1 + RFB1/RFB2) – IDAC • RFB1 where VREF is the reference voltage of the voltage regulator. RFB1 and RFB2 are the resistor divider for the voltage regulator. IDAC is the programmed bidirectional current shown in Table 2. A typical application diagram is shown on the front page. Therefore, the traditional pure analog designed oriented PWM controller can be controlled by a PMBus interface. This illustrates the flexibility of the LTC7106 providing a PMBus interface to conventional analog DC/DC converters. CHIP ENABLE (EN PIN) The LTC7106 is activated by the EN pin. It turns on/off the device with threshold of 1.2V. When EN is low (<1.2V), IDAC is in high impedance (Hi-Z). However, PMBus interface is still active when EN is low which means users can program the device and readback the internal register's value. The device will execute the commands of MFR_IOUT_COMMAND, MFR_IOUT_MARGIN_HIGH, MFR_IOUT_MARGIN_LOW after EN goes high. SLEW RATE CONTROL To prevent abrupt changes in the D/A output current and subsequently the output voltage of the DC/DC regulator, an internal digital programmable slew rate control is included. The slew rate range can be programmed with a 6-bit register from 0.5µs/step to 3.58ms/step with a default value of 3.58ms/step. CURRENT RANGE SETTING AND D/A PROGRAMMING The LTC7106 is a 7-bit bidirectional current DAC with a 1µA LSB as its default setting. The MSB determines the current direction. When MSB is 0, IDAC is sourcing current (reducing VOUT), which is positive current flowing out of the pin, and when MSB is 1, IDAC is sinking current (increasing VOUT), which is negative current flowing into the pin. The LTC7106 also provides range high and range low options through its digital interface to change the LSB value to 4µA expanding the output current range and subsequently widening the programmable output voltage range. Alternately for higher resolution, the low range is provided with a LSB of 0.25µA. Users have additional flexibility of choosing the resistor divider ratio and resistor values to meet the output specification target. However, the design is most accurate using the nominal range which is the recommended setting. Table 1 lists the output current range and Table 2 lists the detailed DAC codes vs IDAC current. Table 1. Output Current Range Range 8 LSB (μA) IMIN (µA) IMAX (µA) Nominal 1 –64 63 Range High 4 –256 252 Range Low 0.25 –16 15.75 Rev A For more information www.analog.com LTC7106 OPERATION Table 2. IDAC Current and Corresponding DAC Codes DAC CODE [6] [5] [4] [3] IDAC (µA) [2] [1] [0] NOMINAL DAC CODE RANGE RANGE HIGH LOW IDAC (µA) [6] [5] [4] [3] [2] [1] [0] NOMINAL RANGE RANGE HIGH LOW 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 38 152 9.5 0 0 0 0 0 0 1 1 4 0.25 0 1 0 0 1 1 1 39 156 9.75 0 0 0 0 0 1 0 2 8 0.5 0 1 0 1 0 0 0 40 160 10 0 0 0 0 0 1 1 3 12 0.75 0 1 0 1 0 0 1 41 164 10.25 0 0 0 0 1 0 0 4 16 1 0 1 0 1 0 1 0 42 168 10.5 0 0 0 0 1 0 1 5 20 1.25 0 1 0 1 0 1 1 43 172 10.75 0 0 0 0 1 1 0 6 24 1.5 0 1 0 1 1 0 0 44 176 11 0 0 0 0 1 1 1 7 28 1.75 0 1 0 1 1 0 1 45 180 11.25 0 0 0 1 0 0 0 8 32 2 0 1 0 1 1 1 0 46 184 11.5 0 0 0 1 0 0 1 9 36 2.25 0 1 0 1 1 1 1 47 188 11.75 0 0 0 1 0 1 0 10 40 2.5 0 1 1 0 0 0 0 48 192 12 0 0 0 1 0 1 1 11 44 2.75 0 1 1 0 0 0 1 49 196 12.25 0 0 0 1 1 0 0 12 48 3 0 1 1 0 0 1 0 50 200 12.5 0 0 0 1 1 0 1 13 52 3.25 0 1 1 0 0 1 1 51 204 12.75 0 0 0 1 1 1 0 14 56 3.5 0 1 1 0 1 0 0 52 208 13 13.25 0 0 0 1 1 1 1 15 60 3.75 0 1 1 0 1 0 1 53 212 0 0 1 0 0 0 0 16 64 4 0 1 1 0 1 1 0 54 216 13.5 0 0 1 0 0 0 1 17 68 4.25 0 1 1 0 1 1 1 55 220 13.75 0 0 1 0 0 1 0 18 72 4.5 0 1 1 1 0 0 0 56 224 14 0 0 1 0 0 1 1 19 76 4.75 0 1 1 1 0 0 1 57 228 14.25 0 0 1 0 1 0 0 20 80 5 0 1 1 1 0 1 0 58 232 14.5 0 0 1 0 1 0 1 21 84 5.25 0 1 1 1 0 1 1 59 236 14.75 0 0 1 0 1 1 0 22 88 5.5 0 1 1 1 1 0 0 60 240 15 15.25 0 0 1 0 1 1 1 23 92 5.75 0 1 1 1 1 0 1 61 244 0 0 1 1 0 0 0 24 96 6 0 1 1 1 1 1 0 62 248 15.5 0 0 1 1 0 0 1 25 100 6.25 0 1 1 1 1 1 1 63 252 15.75 0 0 1 1 0 1 0 26 104 6.5 1 0 0 0 0 0 0 –64 –256 –16 0 0 1 1 0 1 1 27 108 6.75 1 0 0 0 0 0 1 –63 –252 –15.75 0 0 1 1 1 0 0 28 112 7 1 0 0 0 0 1 0 –62 –248 –15.5 0 0 1 1 1 0 1 29 116 7.25 1 0 0 0 0 1 1 –61 –244 –15.25 0 0 1 1 1 1 0 30 120 7.5 1 0 0 0 1 0 0 –60 –240 –15 0 0 1 1 1 1 1 31 124 7.75 1 0 0 0 1 0 1 –59 –236 –14.75 0 1 0 0 0 0 0 32 128 8 1 0 0 0 1 1 0 –58 –232 –14.5 0 1 0 0 0 0 1 33 132 8.25 1 0 0 0 1 1 1 –57 –228 –14.25 0 1 0 0 0 1 0 34 136 8.5 1 0 0 1 0 0 0 –56 –224 –14 0 1 0 0 0 1 1 35 140 8.75 1 0 0 1 0 0 1 –55 –220 –13.75 0 1 0 0 1 0 0 36 144 9 1 0 0 1 0 1 0 –54 –216 –13.5 0 1 0 0 1 0 1 37 148 9.25 1 0 0 1 0 1 1 –53 –212 –13.25 Rev A For more information www.analog.com 9 LTC7106 OPERATION Table 2. IDAC Current and Corresponding DAC Codes (Continued) DAC CODE IDAC (µA) DAC CODE RANGE RANGE HIGH LOW [6] [5] [4] [3] [2] [1] [0] NOMINAL 1 0 0 1 1 0 0 –52 –208 1 0 0 1 1 0 1 –51 1 0 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 IDAC (µA) RANGE RANGE HIGH LOW [6] [5] [4] [3] [2] [1] [0] NOMINAL –13 1 1 0 0 1 1 0 –26 –104 –6.5 –204 –12.75 1 1 0 0 1 1 1 –25 –100 –6.25 –50 –200 –12.5 1 1 0 1 0 0 0 –24 –96 –6 1 –49 –196 –12.25 1 1 0 1 0 0 1 –23 –92 –5.75 0 0 –48 –192 –12 1 1 0 1 0 1 0 –22 –88 –5.5 0 0 1 –47 –188 –11.75 1 1 0 1 0 1 1 –21 –84 –5.25 0 0 1 0 –46 –184 –11.5 1 1 0 1 1 0 0 –20 –80 –5 1 0 0 1 1 –45 –180 –11.25 1 1 0 1 1 0 1 –19 –76 –4.75 0 1 0 1 0 0 –44 –176 –11 1 1 0 1 1 1 0 –18 –72 –4.5 1 0 1 0 1 0 1 –43 –172 –10.75 1 1 0 1 1 1 1 –17 –68 –4.25 1 0 1 0 1 1 0 –42 –168 –10.5 1 1 1 0 0 0 0 –16 –64 –4 1 0 1 0 1 1 1 –41 –164 –10.25 1 1 1 0 0 0 1 –15 –60 –3.75 1 0 1 1 0 0 0 –40 –160 –10 1 1 1 0 0 1 0 –14 –56 –3.5 1 0 1 1 0 0 1 –39 –156 –9.75 1 1 1 0 0 1 1 –13 –52 –3.25 1 0 1 1 0 1 0 –38 –152 –9.5 1 1 1 0 1 0 0 –12 –48 –3 1 0 1 1 0 1 1 –37 –148 –9.25 1 1 1 0 1 0 1 –11 –44 –2.75 1 0 1 1 1 0 0 –36 –144 –9 1 1 1 0 1 1 0 –10 –40 –2.5 1 0 1 1 1 0 1 –35 –140 –8.75 1 1 1 0 1 1 1 –9 –36 –2.25 1 0 1 1 1 1 0 –34 –136 –8.5 1 1 1 1 0 0 0 –8 –32 –2 1 0 1 1 1 1 1 –33 –132 –8.25 1 1 1 1 0 0 1 –7 –28 –1.75 1 1 0 0 0 0 0 –32 –128 –8 1 1 1 1 0 1 0 –6 –24 –1.5 1 1 0 0 0 0 1 –31 –124 –7.75 1 1 1 1 0 1 1 –5 –20 –1.25 1 1 0 0 0 1 0 –30 –120 –7.5 1 1 1 1 1 0 0 –4 –16 –1 1 1 0 0 0 1 1 –29 –116 –7.25 1 1 1 1 1 0 1 –3 –12 –0.75 1 1 0 0 1 0 0 –28 –112 –7 1 1 1 1 1 1 0 –2 –8 –0.5 1 1 0 0 1 0 1 –27 –108 –6.75 1 1 1 1 1 1 1 –1 –4 –0.25 10 Rev A For more information www.analog.com LTC7106 OPERATION GPO Device Addressing GPO is a general purpose open-drain output pin, which can be set by PMBus command. It is designed to turn on/ off the DC/DC regulator by connecting GPO to the RUN pin of the regulator. Once GPO is set high, it stays high even if the EN pin goes low as long as the device is not power cycled. The LTC7106 offers four different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ARA). ADDRESS The PMBus address is selected by ASEL0 and ASEL1 pins. Each pin has three states: high, low and floating. The possible PMBus addresses are shown in Table 3. Table 3. Address Selection ASEL1 ASEL0 PMBus ADDRESS GND GND 2A GND VDD 2C GND FLOAT 2E VDD GND 4A VDD VDD 4C VDD FLOAT 4E FLOAT GND 6A FLOAT VDD 6C FLOAT FLOAT 6E Global addressing provides a means of the PMBus master to address all LTC7106 devices on the bus. The LTC7106 global addresses are fixed 0x5A or 0x5B (7 bit) or 0xB4 or 0xB6 (8 bit) and cannot be disabled. Device addressing provides the standard means of the PMBus master communicating with a single instance of a LTC7106. The value of the device address is set by the ASEL0/ASEL1 configuration pins. Rail addressing provides a means of the PMBus master addressing a set of channels connected to the same output rail, simultaneously. This is similar to global addressing, however, the PMBus address can be dynamically assigned by using the MFR_RAIL_ADDRESS command. It is recommended that rail addressing should be limited to command write operations. All four means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. Fault Status The STATUS_BYTE and ALERT pin provide fault status information of the LTC7106 to the host. PMBus SERIAL INTERFACE The LTC7106 serial interface is a PMBus-compliant slave device and can operate at any frequency between 10kHz and 400kHz. In addition the LTC7106 always responds to the global broadcast address of 0x5A or 0x5B (7-bit). The serial interface supports the following protocols defined in the PMBus specifications: 1) send command, 2) write byte, 3) group, 4) read byte and 5) read word. The PMBus write operations are not acted upon until a complete valid message is received by the LTC7106 including the STOP bit. Communication Failure Attempts to access unsupported commands or writing invalid data to supported commands will result in a CML fault. The CML bit is set in the STATUS_BYTE command and the ALERT pin is pulled low. Bus Timeout Failure The LTC7106 implements a timeout feature to avoid hanging the serial interface. The data packet timer begins at the first START event before the device address write byte. Data packet information must be completed within 25ms or the LTC7106 will tri-state the bus and ignore the given data packet. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), and all data bytes. The user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. The LTC7106 supports the full PMBus frequency range from 10kHz to 400kHz. Rev A For more information www.analog.com 11 LTC7106 OPERATION Similarity Between PMBus, SMBus and I2C 2-Wire Interface The PMBus 2-wire interface is an incremental extension of the SMBus. SMBus is built upon I2C with some minor differences in timing, DC parameters and protocol. The PMBus/SMBus protocols are more robust than simple I2C byte commands because PMBus/SMBus provide timeouts to prevent bus hangs and valid operation commands. In general, a master device that can be configured for I2C communication can be used for PMBus communication with little or no change to hardware or firmware. Repeat start (restart) is not supported by all I2C controllers but is required for SMBus/PMBus reads. If a general purpose I2C controller is used, check that repeat start is supported. For a description of the minor extensions and exceptions PMBus makes to SMBus, refer to PMBus Specification Part 1, Revision 1.1: Paragraph 5: Transport. For a description of the differences between SMBus and I2C, refer to System Management Bus (SMBus) Specification Version 2.0: Appendix B—Differences Between SMBus and I2C. PMBus SERIAL INTERFACE The LTC7106 communicates with a host (master) using the standard PMBus serial bus interface. The Timing Diagram, Figure 1, shows the timing relationship of the signals on the bus. The two-bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The following PMBus protocols are supported: • Write Byte, Send Byte • Read Byte, Read Word • Alert Response Address Figure 3 through Figure 6 illustrate the aforementioned PMBus protocols. All transactions support GCP (group command protocol). Figure 2 is a key to the protocol diagrams in this section. A value shown below a field in the following figures is a mandatory value for that field. The data formats implemented by PMBus are: • Master transmitter transmits to slave receiver. The transfer direction in this case is not changed. • Master reads slave immediately after the first byte. At the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. • Combined format. During a change of direction within a transfer, the master repeats both a start condition and the slave address but with the R/W bit reversed. In this case, the master receiver terminates the transfer by generating a NACK on the last byte of the transfer and a STOP condition. Examples of these formats are shown in Figure 4 and Figure 5. The LTC7106 is a slave device. The master can communicate with the LTC7106 using the following formats: • Master Transmitter, Slave Receiver • Master Receiver, Slave Transmitter 12 Rev A For more information www.analog.com LTC7106 OPERATION SDA tf tLOW tr tSU(DAT) tHD(SDA) tf tSP tr tBUF SCL tHD(STA) tHD(DAT) tSU(STA) tHIGH tSU(STO) 7106 F01 START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. Timing Diagram 1 1 7 8 1 1 DATA BYTE A P 1 S SLAVE ADDRESS Wr A S START CONDITION Sr REPEATED START CONDITION x x Rd READ (BIT VALUE OF 1) Wr WRITE (BIT VALUE OF 0) x SHOWN UNDER A FIELD INDICATES THAT THAT FIELD IS REQUIRED TO HAVE THE VALUE OF x A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0 FOR AN ACK OR 1 FOR A NACK) P STOP CONDITION PEC PACKET ERROR CODE MASTER TO SLAVE SLAVE TO MASTER ... CONTINUATION OF PROTOCOL 7106 F02 Figure 2. PMBus Packet Protocol Diagram Element Key 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 1 DATA BYTE A P 7106 F03 Figure 3. Write Byte Protocol 1 S 1 1 SLAVE ADDRESS Wr A COMMAND CODE A 7 1 1 8 P 7106 F04 Figure 4. Send Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 1 7 1 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 1 1 DATA BYTE HIGH A 8 P 1 Figure 5. Read Word Protocol 1 S 7 1 1 8 1 1 8 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 1 DATA BYTE A P 1 Figure 6. Read Byte Protocol 7106 F05 7106 F06 Rev A For more information www.analog.com 13 LTC7106 REGISTER COMMAND DETAILS Table 4. LTC7106 Supported PMBus Commands PMBus CODE (8 BITS) R/W TYPE COMMAND NAME 0x01 R/W OPERATION 0x78 R/W STATUS_BYTE Read Fault Status: CML, Write 1 to Reset 0x98 Read PMBUS_REVISION Read PMBus Revision = 0x22 for Rev 1.2 0xE2 R/W MFR_CHIP_CTRL [7:4] – Reserved: [7:0] = 0x00 Default [0] = GPO EN, [1] = Reserved, [2] = Write Protect, [3] = Timeout Status 0xE4 R/W MFR_DAC_CTRL [7:6] = Current Step Control, [5:0] = DAC Slew Rate Control 0xE5 R/W MFR_IOUT_MARGIN_HIGH 0xE6 R/W MFR_IOUT_MAX Clamped Value that DAC Cannot Exceed. Default 7-Bit Value of 0x00 = Source Current Only 0xE7 Read MFR_SPECIAL_ID MFR Special ID for LTC7106 = 0x8080 0xE8 R/W MFR_IOUT_COMMAND 0xED R/W MFR_IOUT_MARGIN LOW 0xFA R/W MFR_RAIL_ADDRESS 0xFD Write MFR_RESET DESCRIPTION Default is On: [7:0] = 0x80 Same Format as MFR_IOUT_COMMAND IOUT Margining Command (see Table 5) [5:0] Step Value, Source: [6] = 0, Sink: [6] = 1 Same Format as MFR_IOUT_COMMAND Set Common PMBus Address [6:0], [7] = 0 Enable, [7] = 1 Disable Reset PMBus Interface to Power-On State Write Data is Ignored; 0, 1, 2 Bytes MFR_IOUT_COMMAND MFR_IOUT_MARGIN_LOW The DAC output current command is formatted as a 7-bit 2’s complement value. When the operation register is set to 0x80, DAC takes the value stored in this register. Setting bit[6] to 0 sources the current from the IC and bit[6] to 1 sinks the current into the IC. Default value for this register is 0x00. The valid range of values are from 0x40 to 0x3F. DAC margining register with the same format and rules as MFR_IOUT_COMMAND. The DAC value will take the value stored in this register when the operation register is set to margin low, 0x98. Do not attempt to write values outside of this range or undesired behavior may result. Writes to this register are inhibited when the WPB, bit [2] in MFR_CHIP_CTRL, is set high. Clamping value that DAC cannot exceed. The format is a 7-bit 2’s complement value, the same as the margin registers. Therefore, the DAC value cannot be a smaller 2’s complement value than what is stored in this register. MFR_IOUT_MARGIN_HIGH DAC margining register with the same format and rules as MFR_IOUT_COMMAND. The DAC value will take the value stored in this register when the operation register is set to margin high, 0xA8. 14 MFR_IOUT_MAX The 7-bit default value is 0x00 = cannot sink current. IOUT cannot be set to a higher value unless this value is changed to a negative number, bit [7] = 1. Setting this register to 0x40 allows the LTC7106 to sink the maximum current with no clamping. Rev A For more information www.analog.com LTC7106 REGISTER COMMAND DETAILS MFR_CHIP_CTRL This register is for general chip control and status. Please refer to Table 7 for each bit description. Bits Description [7:4] Reserved [3] Timeout Status: Only a power cycle, POR, will reset this register to prevent unwanted immediate current changes in IDAC. MFR_RESET will not reset this register. In addition, IDAC must be at 0x00 to change the current range selector to prevent unwanted large swings in IDAC current. The time step selector, bits [5:0], can be changed at any time. Table 5. Programmable Delay Per Current Step 0 = No PMBus Timeout Occurred Slew Rate Timer Clock (µs/Step) 1 = A Timeout Occurred [5:0] [5:0] [5:0] Writing a 1 to this bit will clear this bit 000000 = 3584 010000 = 16 100000 = 256 [2] Write Protect for Margin Registers 000001 = 0.5 010001 = 20 100001 = 320 000010 = 1.0 010010 = 24 100010 = 384 000011 = 1.5 010011 = 28 100011 = 448 000100 = 2.0 010100 = 32 100100 = 512 000101 = 2.5 010101 = 40 100101 = 640 000110 = 3.0 010110 = 48 100110 = 768 000111 = 3.5 010111 = 56 100111 = 896 001000 = 4.0 011000 = 64 101000 = 1280* 001001 = 5.0 011001 = 80 101001 = 1280 001010 = 6.0 011010 = 96 101010 = 1536 001011 = 7.0 011011 = 112 101011 = 1792 001100 = 8.0 011100 = 128 101100 = 2560* 001101 = 10 011101 = 160 101101 = 2560 001110 = 12 011110 = 192 101110 = 3584* 001111 = 14 011111 = 224 101111 = 3584 0 = Write Allowed 1 = Writes Inhibited [1] Reserved [0] GPO, General Purpose Output 0 = GPO Pulls Open Drain to GND 1 = Hi-Z on GPO MFR_DAC_CTRL 8-bit register to control the IDAC LSB current value and the timer count for the slew rate control. Default value = 0x40. Bits Description [7:6] Selector Range for IDAC Step Current: b’00 = 0.25µA/Step, Range Low b’01 = 1.0µA/Step, Nominal b’10 = 4.0µA/Step, Range High b’11 = Reserved * Duplicate Encoding [5:0] Selector for Time in µs/Step Default Value 0x00 = Max = 3584µs/Step See Table 6 for Allowable Values Rev A For more information www.analog.com 15 LTC7106 PMBus COMMAND DETAILS MFR_RESET OPERATION This command provides a means by which the user can perform a reset of the LTC7106. All latched faults (ALERT and status register) and register contents will be reset to a power-on condition by this command. VOUT will remain in regulation but may change due to the reset of the margin registers. The OPERATION command is used to turn the unit on/off and for margining the output voltage. This write-only command accepts zero, one, or two data bytes but ignores them. MFR_RAIL_ADDRESS The MFR_RAIL_ADDRESS command allows all devices to share a common address, such as all devices attached to a single power supply rail. The desired 7-bit address value is written to the 7 bits of the data byte. DISABLE The MSB (bit B7) must be set low to enable communication using the MFR_RAIL_ADDRESS address. Setting this bit disables this address. The default for this register is 0x80. B7 The MARGIN_LOW/HIGH bits command the IOUT reference to the offset value stored in either the MFR_IOUT_ MARGIN_HIGH or MFR_IOUT_MARGIN_LOW. This command has one data byte. It will accept one or two but ignores the second byte. Table 6. Supported OPERATION Command Register Values ACTION VALUE Turn Off Immediately 0x00 Turn On 0x80 Margin Low 0x98 Margin High 0xA8 PMBus_REVISION The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTC7106 is PMBus Version 1.2 compliant in both Part I and Part II. 7-BIT ADDRESS B0 CLEAR B7 TO ENABLE RAIL ADDRESS 7106 F07 Figure 7. MFR_RAIL_ADDRESS Data Byte The user should only perform command writes to this address. If a read is performed from this address and the rail devices do not respond with EXACTLY the same value, the LTC7106 will detect bus contention and abort its read command with no CML or ALERTB set. This command accepts one or two data bytes but the second is ignored. 16 The ON bit is automatically reset to ON after a master shutdown (EN), power cycle, or MFR_RESET command. This read-only command has one data byte and will return 0x22. MFR_SPECIAL_ID The 16-bit word representing a unique identification for LTpowerPlay. This read-only command has 2 data bytes and is set to 0x8080. Rev A For more information www.analog.com LTC7106 PMBus COMMAND DETAILS STATUS_BYTE The STATUS_BYTE command returns one byte of information with a summary of the unit’s fault condition. See Table 7 for a list of the status bits that are supported and the conditions in which each bit is set. Certain bits when set in the STATUS_BYTE also cause the ALERT pin to be asserted. Writing a “1” to a particular bit in the status byte will attempt to reset that fault in the status byte and the ALERT pin. If the fault is still present the status byte bit and ALERT will remain asserted. If the ALERT has previously been cleared by an ARA message, the ALERT will be re-asserted. If the fault is no longer present, the ALERT pin will be de-asserted and the fault bit in the status byte will be cleared. All bits in the status byte are also cleared by toggling the RUN_MSTR pin or the ON bit in OPERATION. The bit will immediately be set again if the fault remains. Table 7. Status Byte Bit Descriptions and Conditions BIT DESCRIPTION CONDITION SET ALERT? CLEARABLE BY WRITING ‘1’ TO BIT? 0 (LSB) None of the Above MFR_VOUT_MAX Register Exceeded No Yes 1 Communication Failure (See Note 1) Yes Yes 2 Temperature Fault Not Implemented 3 VIN Undervoltage Fault Not Implemented 4 Output Overcurrent Fault Not Implemented 5 Output Overvoltage Fault Not Implemented 6 OFF Not Implemented 7 Busy Not Implemented Note 1: Communication failure is one of following faults: host sends too few bits, host reads too few bits, host writes too few bytes, improper R/W bit set, unsupported command code, attempt to write to a read-only command. See PMBus Specification v1.2, Part II, Sections 10.8 and 10.9 for more information. Rev A For more information www.analog.com 17 LTC7106 APPLICATIONS INFORMATION IDAC ACCURACY The LTC7106 provides three ranges of IDAC output current. However, only nominal range (LSB = ±1µA) is optimized with the highest accuracy. It is recommended that users design the resistor divider using the nominal range of the IDAC setting. Define ∆VOUT as the VOUT error caused by the IDAC error ∆IDAC, then we can derive the following equation from equation (1) and (2): ∆VOUT ⎛ ∆IDAC / IDAC ⎞ =⎜ ⎟ VOUT ⎝ Ratio – 1 ⎠ Where: VID [6:0] of the LTC7106 is in the format of two’s complementary. From Table 2, it is easy to program the register once the desired output current is known. For example, if output current is 20µA, then set VID [6:0] = 0010100. If the output current is –20µA, then set VID [6:0] = 1101100 for the nominal IDAC setting. VOUT ACCURACY When IDAC = 0, define: (1) Referring to Figure 8, the output voltage is set according to: ⎡ R ⎤ VOUT = VREF ⎢1+ FB1 ⎥ – IDAC • RFB1 ⎣ RFB2 ⎦ (2) It is clear that when Ratio < 0 or Ratio ≥ 2, the VOUT error can be attenuated from the IDAC error: | ∆VOUT VOUT |≤| IDAC | (5) IDAC • R FB1 (6) –1 In the case of margin low, IDAC > 0. So the VOUT error will only be attenuated when: Ratio = VOUT0 IDAC • R FB1 >2 V IDAC • R F B1 < OUT0 2 (7) In other words, as long as VOUT is margining low within 50% of the VOUT default value, VOUT0, the VOUT error won't be larger than the IDAC error. RFB1 LTC7106 VREF ∆IDAC In the case of margin high, IDAC < 0 so Ratio < 0. Therefore, the VOUT error is always smaller than the IDAC error by a factor of: or VOUT (4) IDAC • R FB1 VOUT0 ⎡ R ⎤ VOUT0 = VREF ⎢1+ FB1 ⎥ ⎣ RFB2 ⎦ RFB2 VOUT0 Ratio = TWO’S COMPLEMENTARY CODE (3) IDAC 7106 F08 DESIGN EXAMPLES Figure 8. Setting the Output Voltage Using the LTC7106 18 The LTC7106 can work with almost all the power management controllers or regulators. Figure 9, Figure 10 and Figure 11 show three design examples using the LTC7106 to control the output voltage with a monolithic buck regulator, an μModule® and a boost controller. Rev A For more information www.analog.com LTC7106 APPLICATIONS INFORMATION Case One current amplitude is, the better accuracy the LTC7106 can achieve. So it is easy to choose RTOP = 10kΩ and RBOT = 6.65kΩ. Then IDAC = (1.5V – 1.0V)/10kΩ = + 50μA. Choose MFR_CONTROL [6:5] = 00 (Range = Nominal) to set IDAC LSB =1μA. Assume that the LTC7150S, a monolithic buck regulator, provides a 1.5V output and requires to margin low VOUT from 1.5V to 1.0V (see Figure 9). The VFB is 0.6V and the voltage dividers are external. In order to achieve the best accuracy of the LTC7106, it is recommended to design IDAC in nominal range. Also within certain current range (nominal, high or low), the larger the absolute IDAC VIN 3.1V TO 20V By looking in Table 2, choose DAC [6:0] = 0110010 to set the IDAC = +50μA, which will margin VOUT from 1.5V to 1.0V. PVIN 10k FB LTC7150S SVIN 22µF ×2 0.25µH SW RUN 6.65k VOUT 1.5V/20A 100µF ×2 + 330µF VOUT– PHMODE TRACK/SS CLKOUT 10k MODE/SYNC PGOOD INTVCC 4.7μF SGND RT ITH 162k 10k 22pF 1nF VDD +50µA TO MARGIN LOW VOUT FROM 1.5V TO 1V 2.5V TO 5.5V 1µF 10k 10k 10k 10k VDD SDA PMBus INTERFACE SCL ALERT GPO EN SDA SCL ALERT GPO GND IDAC LTC7106 ASEL0 ASEL1 7106 F09 Figure 9. Using the LTC7106 to Margin Low Monolithic Buck Regulator LTC7150S Providing 1.5V to 1.0V at 20A Rev A For more information www.analog.com 19 LTC7106 APPLICATIONS INFORMATION Case Two In this case, the μModule LTM4636 provides a 1.2V output and requires to margin high VOUT from 1.2V to 2.0V (see Figure 10). The VFB of the LTM4636 is again 0.6V. However, the top voltage divider is internal (RTOP = 4.99kΩ), so the RBOT is also fixed at 4.99kΩ. Then IDAC = (1.2V – 2.0V)/ 4.99kΩ = –160μA. 4.70V TO 15V So we have to choose MFR_CONTROL [6:5] = 10 (Range = High) to set IDAC LSB = 4μA. From Table 3, choose DAC[6:0] = 1011000 to set the IDAC = –160µA, which will margin VOUT from 1.2V to 2.0V. VIN < = 5.5V, TIE VIN, INTVCC AND PVCC TOGETHER, TIE RUNP TO GND, VIN > 5.5V, THEN OPERATE AS SHOWN 22µF 16V ×5 100µF 25V PVCC INTVCC PVCC VIN 115k INTVCC 22pF PVCC RUNC 0.1µF HIZREG LTM4636 470µF ×3 FREQ 34.8k VOUTS1- TRACK/SS 4.7µF 100µF 6.3V x4 VOUTS1+ RUNP INTVCC VOUT 1.2V, 40A VOUT MODE/PLLIN VFB SNSP1 SNSP2 4.99k COMPA COMPB PINS NOT USED IN THIS CIRCUIT: CLKOUT,GMON, PGOOD,PHMODE,PWM, SW,TEST1,TEST2,TEST3,TEST4,TMON TEMP+ TEMP– SGND PGND OPTIONAL TEMP MONITOR VDD 160μA TO MARGIN HIGH VOUT FROM 1.2V TO 2V 2.5V TO 5.5V 1µF 10k 10k 10k 10k VDD SDA SCL PMBus INTERFACE ALERT GPO EN SDA SCL ALERT GPO GND LTC7106 ASEL0 IDAC ASEL1 7106 F10 Figure 10. Using the LTC7106 to Margin High μModule LTM4636 Providing 1.2V to 2.0V at 40A 20 Rev A For more information www.analog.com LTC7106 APPLICATIONS INFORMATION Case Three design criteria in Case One, we can choose RTOP = 200kΩ and RBOT = 8.97kΩ for the best accuracy. Then IDAC = (28V – 18V)/200kΩ = +50µA. Choose MFR_CONTROL [6:5] = 00 (Range Nominal) to set IDAC LSB = 1µA. By looking in Table 2, choose DAC[6:0] = 0001110 to set the IDAC = +50μA, which will margin VOUT from 28V to 18V. The LTC7106 can also work with boost converters. In this case, the LTC3784, a synchronous boost controller, provides a 2-phase 28V/10A output and requires to control VOUT from 28V to 18V (see Figure 11). The VFB is 1.2V and the voltage dividers are external. Based on the same 4mΩ 3.3μH 47µF SENSE1+ SENSE1– VBATT BG1 VBIAS BOOST1 12V DOWN TO 2.3V AFTER START-UP IF VBIAS IS POWERED FROM VOUT 0.1µF VOUT 28V AT 10A SW1 LTC3784 TG1 4mΩ INTVCC 3.3μH 220µF 4.7µF SENSE2+ 100k SENSE2– BG2 PGOOD INTVCC FREQ BOOST2 OVMODE MODE/PLLIN ITH VDD 100pF SS SGND PGND 8.97k 0.1µF 2.5V TO 5.5V 1µF 10k 10k 10k +50µA TO MARGIN LOW VOUT FROM 28V TO 18V 10k VDD SDA PMBus INTERFACE 200k VFB 15nF 8.66k 0.1µF SW2 TG2 SCL ALERT GPO EN SDA SCL ALERT GPO GND LTC7106 ASEL0 IDAC ASEL1 7106 F11 Figure 11. Using the LTC7106 with a Boost Controller to Vary VOUT from 28V to 18V Rev A For more information www.analog.com 21 LTC7106 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC7106#packaging for the most recent package drawings. DDB Package 10-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1722 Rev Ø) 0.64 ±0.05 (2 SIDES) 0.70 ±0.05 2.55 ±0.05 1.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.39 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (2 SIDES) R = 0.05 TYP R = 0.115 TYP 6 0.40 ±0.10 10 2.00 ±0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 0.200 REF 0.75 ±0.05 0 – 0.05 0.64 ±0.05 (2 SIDES) 5 0.25 ±0.05 PIN 1 R = 0.20 OR 0.25 × 45° CHAMFER 1 (DDB10) DFN 0905 REV Ø 0.50 BSC 2.39 ±0.05 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 22 Rev A For more information www.analog.com LTC7106 REVISION HISTORY REV DATE DESCRIPTION A 04/18 Clarified MFG_RAIL_ADDRESS and MFG_SPECIAL_ID paragraphs Changed from “Status Word” to “Status Byte” PAGE NUMBER 15 16 Rev A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 23 LTC7106 TYPICAL APPLICATION 1µH VIN 3.4V TO 22V (42V TRANSIENT) VIN 4.7µF EN/UV BIAS LT8640S RT VDD EXTERNAL SOURCE >3.1V 1µF OR GND 10pF 6.04k 100µF 1210 X5R/X7R FB 17.8k 6.98k GND fSW = 2MHz L: XEL6030 2.5V TO 5.5V VOUT 1.8V 6A SW 0µA TO 50µA 1µF 10k 10k 10k 10k VDD SDA SCL PMBus INTERFACE ALERT GPO EN SDA SCL LTC7106 ALERT GPO GND ASEL0 IDAC ASEL1 7106 F12 Figure 12. Margining a LT8640S from 1.8V to 1.5V at 6A RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3605/LTC3605A 20V, 5A Synchronous Step-Down Regulator 4V < VIN < 20V, 0.6V < VOUT < 20V, 96% Maximum Efficiency, 4mm × 4mm QFN-24 Package LTC3626 20V, 2.5A Synchronous Step-Down Regulator with Current 95% Efficiency, VIN: 3.6V to 20V, VOUT(MIN) = 0.6V, IQ = 300µA, and Temperature Monitoring ISD < 15µA, 3mm × 4mm QFN-20 LTC3636 20V, Dual 6A Synchronous Step-Down Regulator 95% Efficiency, VIN: 3.1V to 17V, VOUT(MIN) = 0.6V, IQ < 8µA (Both Channels Enabled), ISD < 1µA, 3mm × 5mm QFN-24 Package LTC3779 150V VIN and VOUT Synchronous 4-Switch Buck-Boost DC/DC Controller 4.5V ≤ VIN ≤ 150V, Input or Output Average Current Loop, PLL, TSSOP-38 Package LTC3784 Low IQ, Multiphase, Dual Channel Single Output Synchronous Step-Up DC/DC Controller 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, PLL Fixed Frequency 50kHz to 900kHz , IQ = 28µA LTC3807 38V, Low IQ, Synchronous Step-Down Controller with 24V Output Voltage Capability PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA LTC3871 100V Bidirectional PolyPhase® Buck or Boost Controller Dynamic Regulation of VIN, VOUT and Current, PLL, Current Monitor, 48-Lead LQPF Package LTM®4636 40A DC/DC µModule Step-Down Regulator Complete 40A Switch Mode Power Supply, 4.75V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 3.3V, 16mm × 16mm × 7.12mm BGA LTC7150S 20V, 20A Synchronous Step-Down Regulator 93% Efficiency, VIN: 3.1V to 20V, VOUT(MIN) = 0.6V, Output Remote Sense, 42-Lead 6mm × 5mm × 1.3mm BGA Package LT®8640S 42V, 6A Synchronous Step-Down Silent Switcher®2 IQ = 2.5µA, VIN(MIN) = 3.4V, VOUT(MAX) = 42V, VOUT(MIN) = 0 24 Rev A D16851-0-4/18(A) For more information www.analog.com www.analog.com © ANALOG DEVICES, INC. 2017-2018