Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Overview KEMET’s Y5V dielectric features an 85°C maximum operating temperature and is considered “general-purpose.” The Electronics Components, Assemblies & Materials Association (EIA) characterizes Y5V dielectric as a Class III material. Components of this classification are fixed, ceramic dielectric capacitors suited for bypass and decoupling or other applications in which dielectric losses, high insulation resistance and capacitance stability are not of major importance. Y5V exhibits a predictable change in capacitance with respect to time and voltage and displays wide variations in capacitance with reference to ambient temperature. Capacitance change is limited to +22%, −82% from −30°C to +85°C. Benefits Applications • • • • • • • • Typical applications include limited temperature, decoupling and bypass. −30°C to +85°C operating temperature range Lead (Pb)-Free, RoHS and REACH compliant EIA 0402, 0603, 0805, 1206, and 1210 case sizes DC voltage ratings of 6.3 V, 10 V, 16 V, 25 V, and 50 V Capacitance offerings ranging from 0.022 μF to 22 μF Available capacitance tolerance of +80%/−20% Non-polar device, minimizing installation concerns 100% pure matte tin-plated termination finish that allowing for excellent solderability Click image above for interactive 3D content Open PDF in Adobe Reader for full functionality Ordering Information C 1210 Case Size Ceramic (L" x W") 0402 0603 0805 1206 1210 1 C 226 Z Specification/ Series Capacitance Code (pF) Capacitance Tolerance C = Standard Two significant digits + number of zeros Z = +80%/-20% M = ±20% 4 V A C TU Failure Rate/ Rated Voltage Packaging/Grade Termination Finish1 Dielectric Design (C-Spec) (VDC) 9 = 6.3 8 = 10 4 = 16 3 = 25 5 = 50 V = Y5V A = N/A C = 100% Matte Sn See "Packaging C-Spec Ordering Options Table" below Additional termination finish options may be available. Contact KEMET for details. One world. One KEMET © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 1 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Packaging C-Spec Ordering Options Table Packaging/Grade Ordering Code (C-Spec) Packaging Type1 Bulk Bag / Unmarked 7" Reel / Unmarked 13" Reel / Unmarked 7" Reel / Marked 13" Reel / Marked 7" Reel / Unmarked / 2mm pitch2 13" Reel / Unmarked / 2mm pitch2 Not required (Blank) TU 7411 (EIA 0603 and smaller case sizes) 7210 (EIA 0805 and larger case sizes) TM 7040 (EIA 0603 and smaller case sizes) 7215 (EIA 0805 and larger case sizes) 7081 7082 Default packaging is "Bulk Bag". An ordering code C-Spec is not required for "Bulk Bag" packaging. The terms "Marked" and "Unmarked" pertain to laser marking option of capacitors. All packaging options labeled as "Unmarked" will contain capacitors that have not been laser marked. Please contact KEMET if you require a laser marked option. For more information see "Capacitor Marking". 2 The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case size devices. For more information regarding 2 mm pitch option see "Tape & Reel Packaging Information". 1 1 Dimensions – Millimeters (Inches) L W B T S EIA Size Code Metric Size Code B Bandwidth S Separation Minimum Mounting Technique 0402 1005 1.00 (0.040) ±0.05 (0.002) 0.50 (0.020) ±0.05 (0.002) 0.30 (0.012) ±0.10 (0.004) 0.30 (0.012) Solder Reflow Only 0603 1608 1.60 (0.063) ±0.15 (0.006) 0.80 (0.032) ±0.15 (0.006) 0.70 (0.028) 3216 0.35 (0.014) ±0.15 (0.006) See Table 2 2.00 (0.079) ±0.20 (0.008) 1.25 (0.049) ±0.20 (0.008) 0.50 (0.02) ±0.25 (0.010) for Thickness 3.20 (0.126) ±0.20 (0.008) 1.60 (0.063) ±0.20 (0.008) 0.50 (0.02) ±0.25 (0.010) 0805 2012 1206 1210 3225 3.20 (0.126) ±0.20 (0.008) 2.50 (0.098) ±0.20 (0.008) L Length W Width T Thickness 0.50 (0.02) ±0.25 (0.010) 0.75 (0.030) N/A Solder Wave or Solder Reflow Solder Reflow Only Qualification/Certification Commercial Grade products are subject to internal qualification. Details regarding test methods and conditions are referenced in Table 4, Performance & Reliability. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 2 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Environmental Compliance Lead (Pb)-Free, RoHS, and REACH compliant without exemptions. Electrical Parameters/Characteristics Item Parameters/Characteristics Operating Temperature Range Capacitance Change with Reference to +25°C and 0 Vdc Applied (TCC) Aging Rate (Maximum % Capacitance Loss/Decade Hour) 1 2 3 4 Dielectric Withstanding Voltage (DWV) Dissipation Factor (DF) Maximum Limit @ 25°C Insulation Resistance (IR) Minimum Limit @ 25°C -30°C to +85°C +22%, -82% 7.0% 250% of rated voltage (5 ± 1 seconds and charge/discharge not exceeding 50mA) 10% (6.3V & 10V), 7% (16V & 25V) and 5% (50V ) See Insulation Resistance Limit Table (Rated voltage applied for 120 ± 5 secs @ 25°C) Regarding Aging Rate: Capacitance measurements (including tolerance) are indexed to a referee time of 48 or 1,000 hours. Please refer to a part number specific datasheet for referee time details. 2 DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the capacitor. 3 Capacitance and dissipation factor (DF) measured under the following conditions: 1kHz ± 50Hz and 1.0 ± 0.2 Vrms if capacitance ≤10µF 120Hz ± 10Hz and 0.5 ± 0.1 Vrms if capacitance >10µF 4 To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits. Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 & Agilent E4980 have a feature known as Automatic Level Control (ALC). The ALC feature should be switched to "ON". 1 Post Environmental Limits High Temperature Life, Biased Humidity, Moisture Resistance Dielectric Rated DC Voltage Capacitance Value Dissipation Factor (Maximum %) > 25 Y5V 16/25 Capacitance Shift Insulation Resistance ±30% 10% of Initial Limit 7.5 All < 16 10.0 15.0 Insulation Resistance Limit Table EIA Case Size 100 Megohm Microfarads or 10 GΩ 50 Megohm Microfarads or 10 GΩ All ≥ 16 V ≤ 10 V © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 3 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 1 – Capacitance Range/Selection Waterfall (0402 – 1210 Case Sizes) 5 9 8 4 3 5 50 3 16 4 25 8 10 9 6.3 5 50 16 3 25 10 FD FD FD FD FD FD FD FF FH FD FD FD FJ FE FT FG FH FH² FH FT² FD FD FD FD FD FD FD FF FH FD FD FD FJ FE FT FG FH FH² FH FT² FD FD FD FD FD FD FD FF FH FD FD FD FJ FE FT FG FH FH² FH FS FD FD FD FD FD FD FD FF FH FD FD FD FD FD FD FD FF FH C0402C EH FS 50 EH 25 EH EC EB EB EB EC EB EB EB EP 16 EH EC EB EB EB EC EB EB EB EP EC EC ED EC EH EM² EJ 10 EC EB EB EB EC EB EB EB EP EC EC ED EC EH EM² EJ EJ EH 6.3 EC EB EB EB EC EB EB EB DG EP EC EC ED EC EH EM² EJ EJ EH 50 8 DG 25 9 DN DN DN DP DO DP DP DP DN 16 4 DN DN DN DP DO DP DP DP DN DN DN DN DN DN DG DN DG DP DG DG DG 10 8 DN DN DN DP DO DP DP DP DN DN DN DN DN DN DG DN DG DP DP DG DP DN DN DP DG DG DG 6.3 9 DN DN DN DP DO DP DP DP DN DN DN DN DN DN DG DN DG DP DP DG DP DN DN DP DG DL DG DF DG DG 50 Voltage Code DN DN DN DP DO DP DP DP DN DN DN DN DN DN DG DN DG DP DP DG CG CG DP DN DN DP DG DL DG DF DG DG 25 BB CF CF CF CF CF CF CF CF CG CG CG CG CG CG CG 16 BB 10 BB 6.3 BB CF CF CF CF CF CF CF CF CG CG CG CG CG CG CG CG CG 10 BB CF CF CF CF CF CF CF CF CG CG CG CG CG CG CG CG CG CG CG CG CG 6.3 BB CF CF CF CF CF CF CF CF CG CG CG CG CG CG CG CG CG CG CG CG CG 16 BB BB BB BB BB BB BB BB BB 25 BB BB BB BB BB BB BB BB BB Rated Voltage (VDC) Case Size/ Series 4 16 6.3 BB BB BB BB BB BB BB BB BB 16 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 10 Capacitance Code M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M 6.3 Capacitance 223 273 333 393 473 563 683 823 104 124 154 184 224 274 334 394 474 564 684 824 105 125 155 185 225 335 475 565 685 106 156 226 8 C1210C Product Availability and Chip Thickness Codes See Table 2 for Chip Thickness Dimensions Capacitance Tolerance 22,000 pF 27,000 pF 33,000 pF 39,000 pF 47,000 pF 56,000 pF 68,000 pF 82,000 pF 0.10 µF 0.12 µF 0.15 µF 0.18 µF 0.22 µF 0.27 µF 0.33 µF 0.39 µF 0.47 µF 0.56 µF 0.68 µF 0.82 µF 1.0 µF 1.2 µF 1.5 µF 1.8 µF 2.2 µF 3.3 µF 4.7 µF 5.6 µF 6.8 µF 10 µF 15 µF 22 µF 9 10 Rated Voltage (VDC) 3 6.3 4 50 8 25 9 16 4 10 8 C1206C 25 9 C0805C 6.3 Voltage Code 16 C0603C 10 Capacitance Code C0402C 6.3 Capacitance Case Size/ Series 4 3 9 8 4 3 5 9 8 4 3 5 9 8 4 3 5 C0603C C0805C C1206C C1210C xx² Only available in Z tolerance. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 4 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 2A – Chip Thickness/Tape & Reel Packaging Quantities Thickness Code Case Size1 Thickness ± Range (mm) BB CF CG DN DO DP DL DF DG EB EC ED EP EM EH EJ FD FE FF FG FH FJ FT FS 0402 0603 0603 0805 0805 0805 0805 0805 0805 1206 1206 1206 1206 1206 1206 1206 1210 1210 1210 1210 1210 1210 1210 1210 0.50 ± 0.05 0.80 ± 0.07* 0.80 ± 0.10* 0.78 ± 0.10* 0.80 ± 0.10* 0.90 ± 0.10* 0.95 ± 0.10 1.10 ± 0.10 1.25 ± 0.15 0.78 ± 0.10 0.90 ± 0.10 1.00 ± 0.10 1.20 ± 0.20 1.25 ± 0.15 1.60 ± 0.20 1.70 ± 0.20 0.95 ± 0.10 1.00 ± 0.10 1.10 ± 0.10 1.25 ± 0.15 1.55 ± 0.15 1.85 ± 0.20 1.90 ± 0.20 2.50 ± 0.30 Thickness Code Case Size1 Thickness ± Range (mm) Paper Quantity1 Plastic Quantity 7" Reel 13" Reel 7" Reel 13" Reel 7" Reel 13" Reel 7" Reel 13" Reel 10,000 4,000 4,000 4,000 4,000 4,000 0 0 0 4,000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50,000 15,000 15,000 15,000 15,000 15,000 0 0 0 10,000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Paper Quantity1 0 0 0 0 0 0 4,000 2,500 2,500 4,000 4,000 2,500 2,500 2,500 2,000 2,000 4,000 2,500 2,500 2,500 2,000 2,000 2,000 1,000 0 0 0 0 0 0 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 8,000 8,000 10,000 10,000 10,000 10,000 8,000 8,000 8,000 4,000 Plastic Quantity Package quantity based on finished chip thickness specifications. 1 If ordering using the 2 mm Tape and Reel pitch option, the packaging quantity outlined in the table above will be doubled. This option is limited to EIA 0603 (1608 metric) case size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 5 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 2B – Bulk Packaging Quantities Loose Packaging Packaging Type Bulk Bag (default) Packaging C-Spec N/A 2 Case Size Packaging Quantities (pieces/unit packaging) 1 EIA (in) Metric (mm) 0402 0603 0805 1206 1210 1808 1812 1825 2220 2225 1005 1608 2012 3216 3225 4520 4532 4564 5650 5664 Minimum Maximum 50,000 1 20,000 The "Packaging C-Spec" is a 4 to 8 digit code which identifies the packaging type and/or product grade. When ordering, the proper code must be included in the 15th through 22nd character positions of the ordering code. See "Ordering Information" section of this document for further details. Commercial Grade product ordered without a packaging C-Spec will default to our standard "Bulk Bag" packaging. Contact KEMET if you require a bulk bag packaging option for Automotive Grade products. 2 A packaging C-Spec (see note 1 above) is not required for "Bulk Bag" packaging (excluding Anti-Static Bulk Bag and Automotive Grade products). The 15th through 22nd character positions of the ordering code should be left blank. All product ordered without a packaging C-Spec will default to out standard "Bulk Bag" packaging. 1 © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 6 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC-7351 EIA Size Code Metric Size Code 0402 Density Level A: Maximum (Most) Land Protrusion (mm) Density Level B: Median (Nominal) Land Protrusion (mm) Density Level C: Minimum (Least) Land Protrusion (mm) C Y X V1 V2 C Y X V1 V2 C Y X V1 V2 1005 0.50 0.72 0.72 2.20 1.20 0.45 0.62 0.62 1.90 1.00 0.40 0.52 0.52 1.60 0.80 0603 1608 0.90 1.15 1.10 4.00 2.10 0.80 0.95 1.00 3.10 1.50 0.60 0.75 0.90 2.40 1.20 0805 2012 1.00 1.35 1.55 4.40 2.60 0.90 1.15 1.45 3.50 2.00 0.75 0.95 1.35 2.80 1.70 1206 3216 1.60 1.35 1.90 5.60 2.90 1.50 1.15 1.80 4.70 2.30 1.40 0.95 1.70 4.00 2.00 1210 3225 1.60 1.35 2.80 5.65 3.80 1.50 1.15 2.70 4.70 3.20 1.40 0.95 2.60 4.00 2.90 12101 3225 1.50 1.60 2.90 5.60 3.90 1.40 1.40 2.80 4.70 3.30 1.30 1.20 2.70 4.00 3.00 Only for capacitance values ≥ 22 µF Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reflow solder processes. KEMET only recommends wave soldering of EIA 0603, 0805, and 1206 case sizes. Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reflow solder processes. Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform qualification testing based on the conditions outlined in IPC Standard 7351 (IPC–7351). 1 Image below based on Density Level B for an EIA 1210 case size. V1 Y Y X X C C V2 Grid Placement Courtyard © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 7 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Soldering Process Recommended Soldering Technique: • Solder wave or solder reflow for EIA case sizes 0603, 0805 and 1206 • All other EIA case sizes are limited to solder reflow only Recommended Reflow Soldering Profile: KEMET’s families of surface mount multilayer ceramic capacitors (SMD MLCCs) are compatible with wave (single or dual), convection, IR or vapor phase reflow techniques. Preheating of these components is recommended to avoid extreme thermal stress. KEMET’s recommended profile conditions for convection and IR reflow reflect the profile conditions of the IPC/J-STD-020 standard for moisture sensitivity testing. These devices can safely withstand a maximum of three reflow passes at these conditions. Preheat/Soak Temperature Minimum (TSmin) Temperature Maximum (TSmax) Time (tS) from TSmin to TSmax Ramp-Up Rate (TL to TP) Termination Finish SnPb 100% Matte Sn 100°C 150°C 60 – 120 seconds 150°C 200°C 60 – 120 seconds 183°C 217°C Time Above Liquidous (tL) 60 – 150 seconds 60 – 150 seconds Peak Temperature (TP) 235°C 260°C Time Within 5°C of Maximum Peak Temperature (tP) 20 seconds maximum 30 seconds maximum Time 25°C to Peak Temperature TL tP Maximum Ramp Up Rate = 3°C/sec Maximum Ramp Down Rate = 6°C/sec tL Tsmax Tsmin tS 3°C/second maximum 3°C/second maximum Liquidous Temperature (TL) Ramp-Down Rate (TP to TL) TP Temperature Profile Feature 25 25° C to Peak Time 6°C/second maximum 6°C/second maximum 6 minutes maximum 8 minutes maximum Note 1: All temperatures refer to the center of the package, measured on the capacitor body surface that is facing up during assembly reflow. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 8 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 4 – Performance & Reliability: Test Methods and Conditions Stress Reference Test or Inspection Method Terminal Strength JIS–C–6429 Appendix 1, Note: Force of 1.8 kg for 60 seconds. Board Flex JIS–C–6429 Appendix 2, Note: Standard termination system – 2.0 mm (minimum) for all except 3 mm for C0G. Flexible termination system – 3.0 mm (minimum). Magnification 50 X. Conditions: Solderability J–STD–002 a) Method B, 4 hours @ 155°C, dry heat @ 235°C b) Method B @ 215°C category 3 c) Method D, category 3 @ 260°C Temperature Cycling JESD22 Method JA–104 Biased Humidity MIL–STD–202 Method 103 Moisture Resistance MIL–STD–202 Method 106 1,000 Cycles (−55°C to +125°C). Measurement at 24 hours +/- 4 hours after test conclusion. Load Humidity: 1,000 hours 85°C/85% RH and rated voltage. Add 100 K ohm resistor. Measurement at 24 hours +/- 4 hours after test conclusion. Low Volt Humidity: 1,000 hours 85°C/85% RH and 1.5 V. Add 100 K ohm resistor. Measurement at 24 hours +/- 4 hours after test conclusion. t = 24 hours/cycle. Steps 7a and 7b not required. Measurement at 24 hours +/- 4 hours after test conclusion. −55°C/+125°C. Note: Number of cycles required – 300, maximum transfer time – 20 seconds, dwell time – 15 minutes. Air – Air. Thermal Shock MIL–STD–202 Method 107 High Temperature Life MIL–STD–202 Method 108 /EIA–198 Storage Life MIL–STD–202 Method 108 150°C, 0 VDC for 1,000 hours. Vibration MIL–STD–202 Method 204 5 g's for 20 min., 12 cycles each of 3 orientations. Note: Use 8" X 5" PCB 0.031" thick 7 secure points on one long side and 2 secure points at corners of opposite sides. Parts mounted within 2" from any secure point. Test from 10 – 2,000 Hz Mechanical Shock MIL–STD–202 Method 213 Figure 1 of Method 213, Condition F. Resistance to Solvents MIL–STD–202 Method 215 Add aqueous wash chemical, OKEM Clean or equivalent. 1,000 hours at 125°C (85°C for X5R, Z5U and Y5V) with 2 X rated voltage applied. Storage and Handling Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in other environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres, and long term storage. In addition, packaging materials will be degraded by high temperature– reels may soften or warp and tape peel force may increase. KEMET recommends that maximum storage temperature not exceed 40ºC and maximum storage humidity not exceed 70% relative humidity. Temperature fluctuations should be minimized to avoid condensation on the parts and atmospheres should be free of chlorine and sulfur bearing compounds. For optimized solderability chip stock should be used promptly, preferably within 1.5 years of receipt. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 9 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Construction (Typical) Detailed Cross Section Dielectric Material (BaTiO3) Dielectric Material (BaTiO3) Barrier Layer (Ni) Termination Finish (100% Matte Sn) End Termination/ External Electrode (Cu) Inner Electrodes (Ni) End Termination/ External Electrode (Cu) Barrier Layer (Ni) Termination Finish (100% Matte Sn) Inner Electrodes (Ni) Capacitor Marking (Optional): Laser marking option is not available on: • • • • C0G, Ultra Stable X8R and Y5V dielectric devices EIA 0402 case size devices EIA 0603 case size devices with Flexible Termination option. KPS Commercial and Automotive grade stacked devices. These capacitors are supplied unmarked only. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 10 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Tape & Reel Packaging Information KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with EIA Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for details on reeling quantities for commercial chips. Bar Code Label Anti-Static Reel ® Embossed Plastic* or Punched Paper Carrier. ET KEM Chip and KPS Orientation in Pocket (except 1825 Commercial, and 1825 and 2225 Military) Sprocket Holes Embossment or Punched Cavity 8 mm, 12 mm or 16 mm Carrier Tape 178 mm (7.00") or 330 mm (13.00") Anti-Static Cover Tape (.10 mm (.004") Maximum Thickness) *EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only. Table 5 – Carrier Tape Configuration, Embossed Plastic & Punched Paper (mm) EIA Case Size Tape Size (W)* Embossed Plastic 7" Reel 13" Reel Punched Paper 7" Reel Pitch (P1)* 13" Reel Pitch (P1)* 01005 – 0402 8 2 2 0603 8 2/4 2/4 0805 8 4 4 4 4 1206 – 1210 8 4 4 4 4 1805 – 1808 12 4 4 ≥ 1812 12 8 8 KPS 1210 12 8 8 KPS 1812 & 2220 16 12 12 Array 0508 & 0612 8 4 4 *Refer to Figures 1 & 2 for W and P1 carrier tape reference locations. *Refer to Tables 6 & 7 for tolerance specifications. New 2 mm Pitch Reel Options* Packaging Ordering Code (C-Spec) C-3190 C-3191 C-7081 C-7082 Packaging Type/Options Automotive grade 7" reel unmarked Automotive grade 13" reel unmarked Commercial grade 7" reel unmarked Commercial grade 13" reel unmarked * 2 mm pitch reel only available for 0603 EIA case size. 2 mm pitch reel for 0805 EIA case size under development. Benefits of Changing from 4 mm to 2 mm Pitching Spacing • Lower placement costs • Double the parts on each reel results in fewer reel changes and increased efficiency • Fewer reels result in lower packaging, shipping and storage costs, reducing waste © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 11 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Figure 1 – Embossed (Plastic) Carrier Tape Dimensions P2 T T2 ØDo [10 pitches cumulative tolerance on tape ± 0.2 mm] Po E1 Ao F Ko B1 E2 Bo S1 W P1 T1 Center Lines of Cavity ØD 1 Cover Tape B 1 is for tape feeder reference only, including draft concentric about B o. Embossment For cavity size, see Note 1 Table 4 User Direction of Unreeling Table 6 – Embossed (Plastic) Carrier Tape Dimensions Metric will govern Constant Dimensions — Millimeters (Inches) Tape Size D0 8 mm 12 mm 1.5 +0.10/-0.0 (0.059 +0.004/-0.0) 16 mm D1 Minimum Note 1 1.0 (0.039) 1.5 (0.059) E1 P0 1.75 ±0.10 (0.069 ±0.004) 4.0 ±0.10 (0.157 ±0.004) R Reference S1 Minimum Note 2 Note 3 25.0 (0.984) 2.0 ±0.05 0.600 (0.079 ±0.002) (0.024) 30 (1.181) P2 T Maximum T1 Maximum 0.600 (0.024) 0.100 (0.004) Variable Dimensions — Millimeters (Inches) Tape Size Pitch 8 mm Single (4 mm) 12 mm Single (4 mm) & Double (8 mm) 16 mm Triple (12 mm) B1 Maximum Note 4 4.35 (0.171) 8.2 (0.323) 12.1 (0.476) E2 Minimum 6.25 (0.246) 10.25 (0.404) 14.25 (0.561) F P1 3.5 ±0.05 (0.138 ±0.002) 5.5 ±0.05 (0.217 ±0.002) 7.5 ±0.05 (0.138 ±0.002) 4.0 ±0.10 (0.157 ±0.004) 8.0 ±0.10 (0.315 ±0.004) 12.0 ±0.10 (0.157 ±0.004) T2 Maximum 2.5 (0.098) 4.6 (0.181) 4.6 (0.181) W Maximum 8.3 (0.327) 12.3 (0.484) 16.3 (0.642) A0,B0 & K0 Note 5 1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment location and hole location shall be applied independent of each other. 2. The tape with or without components shall pass around R without damage (see Figure 6). 3. If S1 < 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b). 4. B1 dimension is a reference dimension for tape feeder clearance only. 5. The cavity defined by A0, B0 and K0 shall surround the component with sufficient clearance that: (a) the component does not protrude above the top surface of the carrier tape. (b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed. (c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3). (d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see Figure 4). (e) for KPS Series product, A0 and B0 are measured on a plane 0.3 mm above the bottom of the pocket. (f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 12 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Figure 2 – Punched (Paper) Carrier Tape Dimensions P2 T Po ØDo [10 pitches cumulative tolerance on tape ± 0.2 mm] A0 F P1 T1 T1 Top Cover Tape W E2 B0 Bottom Cover Tape E1 G Cavity Size, See Note 1, Table 7 Center Lines of Cavity Bottom Cover Tape User Direction of Unreeling Table 7 – Punched (Paper) Carrier Tape Dimensions Metric will govern Constant Dimensions — Millimeters (Inches) Tape Size D0 E1 P0 P2 8 mm 1.5 +0.10 -0.0 (0.059 +0.004 -0.0) 1.75 ±0.10 (0.069 ±0.004) 4.0 ±0.10 (0.157 ±0.004) 2.0 ±0.05 (0.079 ±0.002) G Minimum 0.10 (0.004) Maximum R Reference Note 2 0.75 (0.030) 25 (0.984) T Maximum W Maximum A0 B 0 1.1 (0.098) 8.3 (0.327) 8.3 (0.327) T1 Maximum Variable Dimensions — Millimeters (Inches) Tape Size Pitch 8 mm Half (2 mm) 8 mm Single (4 mm) E2 Minimum 6.25 (0.246) F 3.5 ±0.05 (0.138 ±0.002) P1 2.0 ±0.05 (0.079 ±0.002) 4.0 ±0.10 (0.157 ±0.004) Note 1 1. The cavity defined by A0, B0 and T shall surround the component with sufficient clearance that: a) the component does not protrude beyond either surface of the carrier tape. b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed. c) rotation of the component is limited to 20° maximum (see Figure 3). d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4). e) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements. 2. The tape with or without components shall pass around R without damage (see Figure 6). © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 13 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Packaging Information Performance Notes 1. Cover Tape Break Force: 1.0 Kg minimum. 2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be: Tape Width Peel Strength 8 mm 0.1 to 1.0 Newton (10 to 100 gf) 12 and 16 mm 0.1 to 1.3 Newton (10 to 130 gf) The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be 165° to 180° from the plane of the carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of 300 ±10 mm/minute. 3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA Standards 556 and 624. Figure 3 – Maximum Component Rotation ° T Maximum Component Rotation Top View Maximum Component Rotation Side View Typical Pocket Centerline Tape Width (mm) 8,12 16 – 200 Bo Maximum Rotation ( 20 10 ° T) Typical Component Centerline Ao Figure 4 – Maximum Lateral Movement 8 mm & 12 mm Tape 0.5 mm maximum 0.5 mm maximum 16 mm Tape ° s Tape Maximum Width (mm) Rotation ( 8,12 20 16 – 56 10 72 – 200 5 ° S) Figure 5 – Bending Radius Embossed Carrier Punched Carrier 1.0 mm maximum 1.0 mm maximum R Bending Radius © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com R C1005_Y5V_SMD • 2/29/2016 14 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Figure 6 – Reel Dimensions Full Radius, See Note W3 (Includes Access Hole at Slot Location (Ø 40 mm minimum) flange distortion at outer edge) W2 (Measured at hub) D A (See Note) N C (Arbor hole diameter) B (see Note) W1 (Measured at hub) If present, tape slot in core for tape start: 2.5 mm minimum width x 10.0 mm minimum depth Note: Drive spokes optional; if used, dimensions B and D shall apply. Table 8 – Reel Dimensions Metric will govern Constant Dimensions — Millimeters (Inches) Tape Size A B Minimum C D Minimum 8 mm 178 ±0.20 (7.008 ±0.008) or 330 ±0.20 (13.000 ±0.008) 1.5 (0.059) 13.0 +0.5/-0.2 (0.521 +0.02/-0.008) 20.2 (0.795) 12 mm 16 mm Variable Dimensions — Millimeters (Inches) Tape Size N Minimum W1 W2 Maximum W3 50 (1.969) 8.4 +1.5/-0.0 (0.331 +0.059/-0.0) 12.4 +2.0/-0.0 (0.488 +0.078/-0.0) 16.4 +2.0/-0.0 (0.646 +0.078/-0.0) 14.4 (0.567) 18.4 (0.724) 22.4 (0.882) Shall accommodate tape width without interference 8 mm 12 mm 16 mm © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 15 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Figure 7 – Tape Leader & Trailer Dimensions Embossed Carrier Carrier Tape Punched Carrier 8 mm & 12 mm only END Round Sprocket Holes START Top Cover Tape Elongated Sprocket Holes (32 mm tape and wider) Trailer 160 mm Minimum Components 100 mm Minimum Leader 400 mm Minimum Top Cover Tape Figure 8 – Maximum Camber Elongated sprocket holes (32 mm & wider tapes) Carrier Tape Round Sprocket Holes 1 mm Maximum, either direction Straight Edge 250 mm © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 16 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) KEMET Corporation World Headquarters Europe Asia Southern Europe Sasso Marconi, Italy Tel: 39-051-939111 Northeast Asia Hong Kong Tel: 852-2305-1168 Mailing Address: P.O. Box 5928 Greenville, SC 29606 Skopje, Macedonia Tel: 389-2-55-14-623 Shenzhen, China Tel: 86-755-2518-1306 www.kemet.com Tel: 864-963-6300 Fax: 864-963-6521 Central Europe Landsberg, Germany Tel: 49-8191-3350800 Corporate Offices Fort Lauderdale, FL Tel: 954-766-2800 Kamen, Germany Tel: 49-2307-438110 North America Northern Europe Wyboston, United Kingdom Tel: 44-1480-273082 Taipei, Taiwan Tel: 886-2-27528585 Espoo, Finland Tel: 358-9-5406-5000 Southeast Asia Singapore Tel: 65-6701-8033 2835 KEMET Way Simpsonville, SC 29681 Northeast Wilmington, MA Tel: 978-658-1663 Southeast Lake Mary, FL Tel: 407-855-8886 Central Novi, MI Tel: 248-994-1030 Beijing, China Tel: 86-10-5877-1075 Shanghai, China Tel: 86-21-6447-0707 Seoul, South Korea Tel: 82-2-6294-0550 Penang, Malaysia Tel: 60-4-6430200 Bangalore, India Tel: 91-806-53-76817 Irving, TX Tel: 972-915-6041 West Milpitas, CA Tel: 408-433-9950 Mexico Guadalajara, Jalisco Tel: 52-33-3123-2141 Note: KEMET reserves the right to modify minor details of internal and external construction at any time in the interest of product improvement. KEMET does not assume any responsibility for infringement that might result from the use of KEMET Capacitors in potential circuit designs. KEMET is a registered trademark of KEMET Electronics Corporation. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 17 Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Disclaimer All product specifications, statements, information and data (collectively, the “Information”) in this datasheet are subject to change. The customer is responsible for checking and verifying the extent to which the Information contained in this publication is applicable to an order at the time the order is placed. All Information given herein is believed to be accurate and reliable, but it is presented without guarantee, warranty, or responsibility of any kind, expressed or implied. Statements of suitability for certain applications are based on KEMET Electronics Corporation’s (“KEMET”) knowledge of typical operating conditions for such applications, but are not intended to constitute – and KEMET specifically disclaims – any warranty concerning suitability for a specific customer application or use. The Information is intended for use only by customers who have the requisite experience and capability to determine the correct products for their application. Any technical advice inferred from this Information or otherwise provided by KEMET with reference to the use of KEMET’s products is given gratis, and KEMET assumes no obligation or liability for the advice given or results obtained. Although KEMET designs and manufactures its products to the most stringent quality and safety standards, given the current state of the art, isolated component failures may still occur. Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards (such as installation of protective circuitry or redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or property damage. Although all product–related warnings, cautions and notes must be observed, the customer should not assume that all safety measures are indicted or that other measures may not be required. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com C1005_Y5V_SMD • 2/29/2016 18