AD AD8363ACPZ-R7 50 hz to 6 ghz, 50 db trupwrâ ¢ detector Datasheet

50 Hz to 6 GHz,
50 dB TruPwr™ Detector
AD8363
FEATURES
APPLICATIONS
Power amplifier linearization/control loops
Transmitter power controls
Transmitter signal strength indication (TSSI)
RF instrumentation
FUNCTIONAL BLOCK DIAGRAM
VTGT
VREF
VPOS
COMM
12
11
10
9
AD8363
8
TEMP
7
VSET
INLO 15
6
VOUT
TCM1 16
5
CLPF
NC 13
X2
INHI 14
X2
1
2
3
4
TCM2/PWDN
CHPF
VPOS
COMM
07368-001
Accurate rms-to-dc conversion from 50 Hz to 6 GHz
Single-ended input dynamic range of >50 dB
No balun or external input tuning required
Waveform and modulation independent, such as
GSM/CDMA/W-CDMA/TD-SCDMA/WiMAX/LTE
Linear-in-decibels output, scaled: 52 mV/dB
Log conformance error: <±0.15 dB
Temperature stability: <±0.5 dB
Voltage supply range: 4.5 V to 5.5 V
Operating temperature range: −40°C to +125°C
Power-down capability to 1.5 mW
Small footprint, 4 mm × 4 mm, LFCSP
Figure 1.
GENERAL DESCRIPTION
The AD8363 is a true rms responding power detector that can
be directly driven with a single-ended 50 Ω source. This feature
makes the AD8363 frequency versatile by eliminating the need
for a balun or any other form of external input tuning for operation
up to 6 GHz.
The AD8363 provides an accurate power measurement,
independent of waveform, for a variety of high frequency
communication and instrumentation systems. Requiring only
a single supply of 5 V and a few capacitors, it is easy to use and
provides high measurement accuracy. The AD8363 can operate
from arbitrarily low frequencies to 6 GHz and can accept inputs
that have rms values from less than −50 dBm to at least 0 dBm,
with large crest factors exceeding the requirements for accurate
measurement of WiMAX, CDMA, W-CDMA, TD-SCDMA,
multicarrier GSM, and LTE signals.
Used as a power measurement device, VOUT is connected to
VSET. The output is then proportional to the logarithm of the
rms value of the input. The reading is presented directly in
decibels and is conveniently scaled to 52 mV/dB, or approximately
1 V per decade; however, other slopes are easily arranged. In
controller mode, the voltage applied to VSET determines the
power level required at the input to null the deviation from the
setpoint. The output buffer can provide high load currents.
The AD8363 has 1.5 mW power consumption when powered
down by a logic high applied to the TCM2/PWDN pin. It powers
up within about 30 μs to its nominal operating current of 60 mA at
25°C. The AD8363 is available in a 4 mm × 4 mm 16-lead LFCSP
for operation over the −40°C to +125°C temperature range.
A fully populated RoHS-compliant evaluation board is also
available.
The AD8363 can determine the true power of a high frequency
signal having a complex low frequency modulation envelope, or
it can be used as a simple low frequency rms voltmeter. The highpass corner generated by its internal offset-nulling loop can be
lowered by a capacitor added on the CHPF pin.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
AD8363
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Interface ......................................................................... 19
Applications ....................................................................................... 1
VTGT Interface .......................................................................... 20
Functional Block Diagram .............................................................. 1
Operation to 125°C .................................................................... 20
General Description ......................................................................... 1
Basis for Error Calculations ...................................................... 20
Revision History ............................................................................... 2
Measurement Mode Basic Connections.................................. 21
Specifications..................................................................................... 3
Device Calibration and Error Calculation .............................. 22
Absolute Maximum Ratings............................................................ 7
ESD Caution .................................................................................. 7
Selecting and Increasing Calibration Points to Improve
Accuracy over a Reduced Range .............................................. 22
Pin Configuration and Function Descriptions ............................. 8
Altering the Slope ....................................................................... 23
Typical Performance Characteristics ............................................. 9
Offset Compensation/Minimum CLPF and Maximum CHPF
Capacitance Values..................................................................... 24
Theory of Operation ...................................................................... 16
Square Law Detector and Amplitude Target .............................. 16
RF Input Interface ...................................................................... 17
Choice of RF Input Pin .............................................................. 17
Small Signal Loop Response ..................................................... 17
Temperature Sensor Interface ................................................... 18
VREF Interface ........................................................................... 18
Temperature Compensation Interface ..................................... 18
Power-Down Interface ............................................................... 19
VSET Interface ............................................................................ 19
Choosing a Value for CLPF.......................................................... 25
RF Pulse Response ..................................................................... 27
Controller Mode Basic Connections ....................................... 27
Constant Output Power Operation.......................................... 28
Description of RF Characterization ......................................... 29
Evaluation and Characterization Circuit Board Layouts ...... 30
Assembly Drawings .................................................................... 32
Outline Dimensions ....................................................................... 33
Ordering Guide .......................................................................... 33
REVISION HISTORY
5/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD8363
SPECIFICATIONS
VPOS = 5 V, TA = 25°C, ZO = 50 Ω, single-ended input drive, VOUT connected to VSET, VTGT = 1.4 V, CLPF = 3.9 nF, CHPF = 2.7 nF, error
referred to best-fit line (linear regression) from −20 dBm to −40 dBm, unless otherwise noted. Negative current values imply that the
AD8363 is sourcing current out of the indicated pin.
Table 1.
Parameter
OVERALL FUNCTION
Maximum Input Frequency
RF INPUT INTERFACE
Input Resistance
Common-Mode DC Voltage
100 MHz
Output Voltage: High Power In
Output Voltage: Low Power In
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Deviation from CW Response
Input Impedance
900 MHz
Output Voltage: High Power In
Output Voltage: Low Power In
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Deviation from CW Response
Input Impedance
Conditions
Min
INHI (Pin 14), INLO (Pin 15), ac-coupled
Single-ended drive
TCM1 (Pin 16) = 0.47 V, TCM2 (Pin 1) = 1.0 V, INHI input
PIN = −10 dBm
PIN = −40 dBm
CW input, TA = 25°C
Deviation from output at 25°C
−40°C < TA < +85°C; PIN = −10 dBm
−40°C < TA < +85°C; PIN = −40 dBm
13 dB peak-to-rms ratio (W-CDMA), over 40 dB dynamic range
12 dB peak-to-rms ratio (WiMAX), over 40 dB dynamic range
14.0 dB peak-to-rms ratio (16C CDMA2K), over 40 dB dynamic
range
256 QAM, CF = 8 dB, over 40 dB dynamic range
Single-ended drive
TCM1 (Pin 16) = 0.5 V, TCM2 (Pin 1) = 1.2 V, INHI input
PIN = −15 dBm
PIN = −40 dBm
CW input, TA = 25°C
Deviation from output at 25°C
−40°C < TA < +85°C; PIN = −15 dBm
−40°C < TA < +85°C; PIN = −40 dBm
13 dB peak-to-rms ratio (W-CDMA), over 40 dB dynamic range
12 dB peak-to-rms ratio (WiMAX), over 40 dB dynamic range
14.0 dB peak-to-rms ratio (16C CDMA2K), over 40 dB dynamic
range
256 QAM, CF = 8 dB, over 40 dB dynamic range
Single-ended drive
Rev. 0 | Page 3 of 36
Typ
Max
Unit
6
GHz
50
2.6
Ω
V
2.47
0.92
65
9
−56
V
V
dB
dBm
dBm
−0.2/+0.3
−0.5/+0.6
51.7
−58
<±0.1
<±0.1
<±0.1
dB
dB
mV/dB
dBm
dB
dB
dB
<±0.1
49 − j0.09
dB
Ω
2.2
0.91
54
−2
−56
V
V
dB
dBm
dBm
+0.6/−0.4
+0.8/−0.6
51.8
−58
<±0.1
<±0.1
<±0.1
dB
dB
mV/dB
dBm
dB
dB
dB
<±0.1
60 − j3.3
dB
Ω
AD8363
Parameter
1.9 GHz
Output Voltage: High Power In
Output Voltage: Low Power In
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Deviation from CW Response
Input Impedance
2.14 GHz
Output Voltage: High Power In
Output Voltage: Low Power In
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Deviation from CW Response
Rise Time
Fall Time
Input Impedance
2.6 GHz
Output Voltage: High Power In
Output Voltage: Low Power In
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Conditions
TCM1 (Pin 16) = 0.52 V, TCM2 (Pin 1) = 0.51 V, INHI input
PIN = −15 dBm
PIN = −40 dBm
CW input, TA = 25°C
Deviation from output at 25°C
−40°C < TA < +85°C; PIN = −15 dBm
−40°C < TA < +85°C; PIN = −40 dBm
13 dB peak-to-rms ratio (W-CDMA), over 37 dB dynamic range
12 dB peak-to-rms ratio (WiMAX), over 37 dB dynamic range
14.0 dB peak-to-rms ratio (16C CDMA2K), over 37 dB dynamic
range
256 QAM, CF = 8 dB, over 37 dB dynamic range
Single-ended drive
TCM1 (Pin 16) = 0.52 V, TCM2 (Pin 1) = 0.6 V, INHI input
PIN = −15 dBm
PIN = −40 dBm
CW input, TA = 25°C
Deviation from output at 25°C
−40°C < TA < +85°C; PIN = −15 dBm
−40°C < TA < +85°C; PIN = −40 dBm
13 dB peak-to-rms ratio (W-CDMA), over 35 dB dynamic range
12 dB peak-to-rms ratio (WiMAX), over 35 dB dynamic range
14.0 dB peak-to-rms ratio (16C CDMA2K), over 35 dB dynamic
range
256 QAM, CF = 8 dB, over 35 dB dynamic range
Transition from no input to 1 dB settling at RFIN = −10 dBm,
CLPF = 390 pF, CHPF = open
Transition from −10 dBm to within 1 dB of final value
(that is, no input level), CLPF = 390 pF, CHPF = open
Single-ended drive
TCM1 (Pin 16) = 0.54 V, TCM2 (Pin 1) = 1.1 V, INHI input
PIN = −15 dBm
PIN = −40 dBm
CW input, TA = 25°C
Deviation from output at 25°C
−40°C < TA < +85°C; PIN = −15 dBm
−40°C < TA < +85°C; PIN = −40 dBm
Logarithmic Slope
Logarithmic Intercept
Rev. 0 | Page 4 of 36
Min
Typ
Max
Unit
2.10
0.8
48
−6
−54
V
V
dB
dBm
dBm
+0.3/−0.5
+0.4/−0.4
52
−55
±0.1
±0.1
±0.1
dB
dB
mV/dB
dBm
dB
dB
dB
±0.1
118 − j26
dB
Ω
2.0
0.71
44
−8
−52
V
V
dB
dBm
dBm
+0.1/−0.2
+0.3/−0.5
52.2
−54
±0.1
±0.1
±0.1
dB
dB
mV/dB
dBm
dB
dB
dB
±0.1
3
dB
μs
15
μs
130 − j49
Ω
1.84
0.50
41
−7
−48
V
V
dB
dBm
dBm
+0.5/−0.2
+0.6/−0.2
52.9
−49
dB
dB
mV/dB
dBm
AD8363
Parameter
Deviation from CW Response
Input Impedance
3.8 GHz
Output Voltage: High Power In
Output Voltage: Low Power In
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Deviation from CW Response
Input Impedance
5.8 GHz
Output Voltage: High Power In
Output Voltage: Low Power In
±1.0 dB Dynamic Range
Maximum Input Level, ±1.0 dB
Minimum Input Level, ±1.0 dB
Deviation vs. Temperature
Logarithmic Slope
Logarithmic Intercept
Deviation from CW Response
Input Impedance
OUTPUT INTERFACE
Output Swing, Controller Mode
Current Source/Sink Capability
Voltage Regulation
Rise Time
Fall Time
Noise Spectral Density
Conditions
13 dB peak-to-rms ratio (W-CDMA), over 32 dB dynamic range
12 dB peak-to-rms ratio (WiMAX), over 32 dB dynamic range
14.0 dB peak-to-rms ratio (16C CDMA2K), over 32 dB dynamic
range
256 QAM, CF = 8 dB, over 32 dB dynamic range
Single-ended drive
TCM1 (Pin 16) = 0.56 V, TCM2 (Pin 1) = 1.0 V, INLO input
PIN = −20 dBm
PIN = −40 dBm
CW input, TA = 25°C
Deviation from output at 25°C
−40°C < TA < +85°C; PIN = −20 dBm
−40°C < TA < +85°C; PIN = −40 dBm
13 dB peak-to-rms ratio (W-CDMA), over 32 dB dynamic range
12 dB peak-to-rms ratio (WiMAX), over 32 dB dynamic range
14.0 dB peak-to-rms ratio (16C CDMA2K), over 32 dB dynamic
range
256 QAM, CF = 8 dB, over 32 dB dynamic range
Single-ended drive
TCM1 (Pin 16) = 0.88 V, TCM2 (Pin 1) = 1.0 V, INLO input
PIN = −20 dBm
PIN = −40 dBm
CW input, TA = 25°C
Deviation from output at 25°C
−40°C < TA < +85°C; PIN = −20 dBm
−40°C < TA < +85°C; PIN = −40 dBm
13 dB peak-to-rms ratio (W-CDMA), over 32 dB dynamic range
12 dB peak-to-rms ratio (WiMAX), over 32 dB dynamic range
14.0 dB peak-to-rms ratio (16C CDMA2K), over 32 dB dynamic
range
256 QAM, CF = 8 dB, over 32 dB dynamic range
Single-ended drive
VOUT (Pin 6)
Swing range minimum, RL ≥ 500 Ω to ground
Swing range maximum, RL ≥ 500 Ω to ground
Output held at VPOS/2
ILOAD = 8 mA, source/sink
Transition from no input to 1 dB settling at RFIN = −10 dBm,
CLPF = 390 pF, CHPF = open
Transition from −10 dBm to within 1 dB of final value (that is,
no input level), CLPF = 390 pF, CHPF = open
Measured at 100 kHz
Rev. 0 | Page 5 of 36
Min
Typ
±0.1
±0.1
±0.1
Max
Unit
dB
dB
dB
±0.1
95 − j65
dB
Ω
1.54
0.54
43
−5
−48
V
V
dB
dBm
dBm
+0.1/−0.7
+0.4/−0.5
50.0
−51
±0.1
±0.1
±0.1
dB
dB
mV/dB
dBm
dB
dB
dB
±0.1
42 − j4.5
dB
Ω
1.38
0.36
45
−3
−48
V
V
dB
dBm
dBm
+0.1/−0.6
+0.3/−0.8
51.1
−47
±0.1
±0.1
±0.1
dB
dB
mV/dB
dBm
dB
dB
dB
±0.1
28 + j1.6
dB
Ω
0.03
4.8
−0.2/+0.1
3
V
V
mA
%
μs
15
μs
45
nV/√Hz
10/10
AD8363
Parameter
SETPOINT INPUT
Voltage Range
Input Resistance
Logarithmic Scale Factor
Logarithmic Intercept
TEMPERATURE COMPENSATION
Input Voltage Range
Input Bias Current, TCM1
Input Resistance, TCM1
Input Current, TCM2
Input Resistance, TCM2
VOLTAGE REFERENCE
Output Voltage
Temperature Sensitivity
Current Source/Sink Capability
Voltage Regulation
TEMPERATURE REFERENCE
Output Voltage
Temperature Coefficient
Current Source/Sink Capability
Voltage Regulation
RMS TARGET INTERFACE
Input Voltage Range
Input Bias Current
Input Resistance
POWER-DOWN INTERFACE
Logic Level to Enable
Logic Level to Disable
Input Current
Enable Time
Disable Time
POWER SUPPLY INTERFACE
Supply Voltage
Quiescent Current
Power-Down Current
Conditions
VSET (Pin 7)
Log conformance error ≤ 1 dB, minimum 2.14 GHz
Log conformance error ≤ 1 dB, maximum 2.14 GHz
Min
Typ
2.0
0.7
72
19.2
−54
f = 2.14 GHz, −40°C ≤ TA ≤ +85°C
f = 2.14 GHz, −40°C ≤ TA ≤ +85°C, referred to 50 Ω
TCM1 (Pin 16), TCM2 (Pin 1)
0
VTCM1 = 0 V
VTCM1 = 0.5 V
VTCM1 > 0.7 V
VTCM2 = 5 V
VTCM2 = 4.5 V
VTCM2 = 1 V
VTCM2 = 0 V
0.7 V ≤ VTCM2 ≤ 4.0 V
VREF (Pin 11)
RFIN = −55 dBm
25°C ≤ TA ≤ 70°C
70°C ≤ TA ≤ 125°C
−40°C ≤ TA ≤ +25°C
25°C ≤ TA ≤ 125°C
−40°C ≤ TA < +25°C
TA = 25°C, ILOAD = 3 mA
TEMP (Pin 8)
TA = 25°C, RL ≥ 10 kΩ
−40°C ≤ TA ≤ +125°C, RL ≥ 10 kΩ
25°C ≤ TA ≤ 125°C
−40°C ≤ TA < +25°C
TA = 25°C, ILOAD = 3 mA
VTGT (Pin 12)
2.5
2.3
0.04
−0.06
−0.18
4/0.05
3/0.05
−0.6
1.4
5
4/0.05
3/0.05
−0.1
1.4
TCM2 (Pin1)
VPWDN decreasing
VPWDN increasing
VTCM2 = 5 V
VTCM2 = 4.5 V
VTCM2 = 1 V
VTCM2 = 0 V
TCM2 low to VOUT at 1 dB of final value, CLPF = 470 pF,
CHPF = 220 pF, RFIN = 0 dBm
TCM2 high to VOUT at 1 dB of final value, CLPF = 470 pF,
CHPF = 220 pF, RFIN = 0 dBm
VPOS (Pin 3, Pin 10)
4.5
Rev. 0 | Page 6 of 36
Unit
V
V
kΩ
dB/V
dBm
−140
80
5
2
750
−2
−3
500
VTGT = 1.4 V
TA = 25°C, RFIN = −55 dBm
TA = 85°C
VTCM2 > VPOS − 0.3 V
Max
2.5
V
μA
μA
kΩ
μA
μA
μA
μA
kΩ
V
mV/°C
mV/°C
mV/°C
mA
mA
%
V
mV/°C
mA
mA
%
14
100
V
μA
kΩ
4.2
4.7
2
750
−2
−3
35
V
V
μA
μA
μA
μA
μs
25
μs
5
60
72
300
5.5
V
mA
mA
μA
AD8363
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage, VPOS
Input Average RF Power 1
Equivalent Voltage, Sine Wave Input
Internal Power Dissipation
θJC 2
θJB2
θJA2
ΨJT2
ΨJB2
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
5.5 V
21 dBm
2.51 V rms
450 mW
10.6°C/W
35.3°C/W
57.2°C/W
1.0°C/W
34°C/W
150°C
−40°C to +125°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1
This is for long durations. Excursions above this level, with durations much
less than 1 second, are possible without damage.
2
No airflow with the exposed pad soldered to a 4-layer JEDEC board.
Rev. 0 | Page 7 of 36
AD8363
12 VTGT
11 VREF
10 VPOS
14 INHI
NOTES
1. NC = NO CONNECT
07368-002
9 COMM
TEMP 8
VSET 7
TOP VIEW
(Not to Scale)
CLPF 5
COMM 4
AD8363
VOUT 6
VPOS 3
13 NC
PIN 1
INDICATOR
TCM2/PWDN 1
CHPF 2
15 INLO
16 TCM1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
TCM2/PWDN
2
CHPF
3, 10
VPOS
4, 9,
EPAD
COMM
5
CLPF
6
VOUT
7
VSET
8
11
12
TEMP
VREF
VTGT
13
14
NC
INHI
15
INLO
16
TCM1
Description
This is a dual function pin used for controlling the amount of nonlinear intercept temperature
compensation at voltages <2.5 V and/or for shutting down the device at voltages >4 V. If the
shutdown function is not used, this pin can be connected to the VREF pin through a voltage divider.
Connect this pin to VPOS via a capacitor to determine the −3 dB point of the input signal high-pass filter.
Only add a capacitor when operating at frequencies below 10 MHz.
Supply for the Device. Connect these pins to a 5 V power supply. Pin 3 and Pin 10 are not
internally connected; therefore, both must connect to the source.
System Common Connection. Connect these pins via low impedance to system common. The
exposed paddle is also COMM and should have both a good thermal and good electrical
connection to ground.
Connection for Loop Filter Integration (Averaging) Capacitor. Connect a ground-referenced
capacitor to this pin. A resistor can be connected in series with this capacitor to improve loop
stability and response time. Minimum CLPF value is 390 pF.
Output Pin in Measurement Mode (Error Amplifier Output). In measurement mode, this pin
is connected to VSET. This pin can be used to drive a gain control when the device is used in
controller mode.
The voltage applied to this pin sets the decibel value of the required RF input voltage that results
in zero current flow in the loop integrating capacitor pin, CLPF. This pin controls the variable gain
amplifier (VGA) gain such that a 50 mV change in VSET reduces the gain by approximately 1 dB.
Temperature Sensor Output.
General-Purpose Reference Voltage Output of 2.3 V.
The voltage applied to this pin determines the target power at the input of the RF squaring circuit.
The intercept voltage is proportional to the voltage applied to this pin. The use of a lower target
voltage increases the crest factor capacity; however, this may affect the system loop response.
No Connect.
This is the RF input pin for frequencies up to and including 2.6 GHz. The RF input signal is
normally ac-coupled to this pin through a coupling capacitor.
This is the RF input pin for frequencies above 2.6 GHz. The RF input signal is normally ac-coupled
to this pin through a coupling capacitor.
This pin is used to adjust the intercept temperature compensation. Connect this pin to VREF
through a voltage divider or to an external dc source.
Rev. 0 | Page 8 of 36
Equivalent
Circuit
See Figure 49
See Figure 60
N/A
N/A
See Figure 51
See Figure 51
See Figure 50
See Figure 45
See Figure 46
See Figure 52
N/A
See Figure 44
See Figure 44
See Figure 48
AD8363
TYPICAL PERFORMANCE CHARACTERISTICS
VPOS = 5 V, ZO = 50 Ω, single-ended input drive, VOUT connected to VSET, VTGT = 1.4 V, CLPF = 3.9 nF, CHPF = 2.7 nF, TA = +25°C (black),
−40°C (blue), +85°C (red), where appropriate. Error referred to best-fit line (linear regression) from −20 dBm to −40 dBm, unless
otherwise indicated. Input RF signal is a sine wave (CW), unless otherwise indicated.
2
4
2
6
INHI INPUT
VTCM1 = 0.5V, VTCM2 = 1.2V
INHI INPUT
VTCM1 = 0.47V, VTCM2 = 1V
1
–1
4
3
0
ERROR (dB)
0
OUTPUT VOLTAGE (V)
2
1
ERROR (dB)
OUTPUT VOLTAGE (V)
5
1
3
2
–1
1
–30
–20
PIN (dBm)
–10
–2
10
0
0
–60
Figure 3. VOUT and Log Conformance Error with Respect to 25°C Ideal Line
over Temperature vs. Input Amplitude at 100 MHz, CW, Typical Device
–30
–20
PIN (dBm)
–10
–2
10
0
2
6
INHI INPUT
VTCM1 = 0.47V, VTCM2 = 1V
REPRESENTS 35 DEVICES FROM 3 LOTS
INHI INPUT
VTCM1 = 0.5V, VTCM2 = 1.2V
REPRESENTS 35 DEVICES FROM 3 LOTS
5
1
2
0
1
–1
1
OUTPUT VOLTAGE (V)
3
ERROR (dB)
OUTPUT VOLTAGE (V)
–40
Figure 6. VOUT and Log Conformance Error with Respect to 25°C Ideal Line
over Temperature vs. Input Amplitude at 900 MHz, CW, Typical Device
2
4
–50
07368-006
–40
4
3
0
ERROR (dB)
–50
07368-003
0
–60
2
–1
1
–40
–30
–20
PIN (dBm)
–10
–2
10
0
0
–60
Figure 4. Distribution of VOUT and Error with Respect to 25°C Ideal Line over
Temperature vs. Input Amplitude at 100 MHz, CW
–30
–20
PIN (dBm)
–10
–2
10
0
2
INHI INPUT
VTCM1 = 0.47V, VTCM2 = 1V
REPRESENTS 35 DEVICES FROM 3 LOTS
INHI INPUT
VTCM1 = 0.5V, VTCM2 = 1.2V
REPRESENTS 35 DEVICES FROM 3 LOTS
1
ERROR (dB)
1
0
–1
0
–1
–40
–30
–20
PIN (dBm)
–10
0
10
–2
–60
07368-005
–50
Figure 5. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude at 100 MHz, CW
–50
–40
–30
–20
PIN (dBm)
–10
0
10
07368-008
ERROR (dB)
–40
Figure 7. Distribution of VOUT and Error with Respect to 25°C Ideal Line over
Temperature vs. Input Amplitude at 900 MHz, CW
2
–2
–60
–50
07368-007
–50
07368-004
0
–60
Figure 8. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude at 900 MHz, CW
Rev. 0 | Page 9 of 36
AD8363
3
6
3
6
0
2
–1
1
–2
–50
–40
–30
–20
PIN (dBm)
–10
–3
10
0
Figure 9. VOUT and Log Conformance Error with Respect to 25°C Ideal Line
over Temperature vs. Input Amplitude at 1.90 GHz, CW, Typical Device
INHI INPUT
VTCM1 = 0.52V, VTCM2 = 0.51V
REPRESENTS 35 DEVICES
FROM 3 LOTS
0
2
–1
1
–2
0
–60
–50
–40
–30
–20
PIN (dBm)
–10
–3
10
0
OUTPUT VOLTAGE (V)
3
Figure 10. Distribution of VOUT and Error with Respect to 25°C Ideal Line over
Temperature vs. Input Amplitude at 1.90 GHz, CW
–40
–30
–20
PIN (dBm)
–10
–3
10
0
3
INHI INPUT
VTCM1 = 0.52V, VTCM2 = 0.6V
REPRESENTS 35 DEVICES
FROM 3 LOTS
2
4
1
3
0
2
–1
1
–2
–50
–40
–30
–20
PIN (dBm)
–10
–3
10
0
3
INHI INPUT
VTCM1 = 0.52V, VTCM2 = 0.51V
REPRESENTS 35 DEVICES FROM 3 LOTS
INHI INPUT
VTCM1 = 0.52V, VTCM2 = 0.6V
REPRESENTS 35 DEVICES
FROM 3 LOTS
2
ERROR (dB)
1
0
0
–1
–1
–2
–2
–50
–40
–30
–20
PIN (dBm)
–10
0
10
–3
–60
07368-011
–3
–60
–50
Figure 13. Distribution of VOUT and Error with Respect to 25°C Ideal Line over
Temperature vs. Input Amplitude at 2.14 GHz, CW
1
ERROR (dB)
–2
0
–60
3
2
1
5
ERROR (dB)
1
–1
6
2
4
2
Figure 12. VOUT and Log Conformance Error with Respect to 25°C Ideal Line
over Temperature vs. Input Amplitude at 2.14 GHz, CW, Typical Device
07368-010
OUTPUT VOLTAGE (V)
5
0
0
–60
3
6
3
Figure 11. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude at 1.90 GHz, CW
–50
–40
–30
–20
PIN (dBm)
–10
0
10
07368-014
0
–60
1
ERROR (dB)
3
4
07368-012
1
2
ERROR (dB)
4
5
07368-013
2
OUTPUT VOLTAGE (V)
5
ERROR (dB)
INHI INPUT
VTCM1 = 0.52V, VTCM2 = 0.6V
07368-009
OUTPUT VOLTAGE (V)
INHI INPUT
VTCM1 = 0.52V, VTCM2 = 0.51V
Figure 14. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude at 2.14 GHz, CW
Rev. 0 | Page 10 of 36
AD8363
3
6
3
3.0
0
2
–1
1
–2
–50
–40
–30
–20
PIN (dBm)
–10
–3
10
0
Figure 15. VOUT and Log Conformance Error with Respect to 25°C Ideal Line
over Temperature vs. Input Amplitude at 2.6 GHz, CW, Typical Device
INHI INPUT
VTCM1 = 0.54V, VTCM2 = 1.1V
REPRESENTS 35 DEVICES
FROM 3 LOTS
0
2
–1
1
–2
0
–60
–50
–40
–30
–20
PIN (dBm)
–10
–3
10
0
–2
Figure 16. Distribution of VOUT and Error with Respect to 25°C Ideal Line over
Temperature vs. Input Amplitude at 2.6 GHz, CW
–30
–20
PIN (dBm)
–10
–3
10
0
3
INLO INPUT
VTCM1 = 0.56V, VTCM2 = 1.0V
REPRESENTS 35 DEVICES
FROM 3 LOTS
2
1
1.5
0
1.0
–1
0.5
–2
0
–60
–50
–40
–30
–20
PIN (dBm)
–10
–3
10
0
Figure 19. Distribution of VOUT and Error with Respect to 25°C Ideal Line over
Temperature vs. Input Amplitude at 3.8 GHz, CW
3
INHI INPUT
VTCM1 = 0.54V, VTCM2 = 1.1V
REPRESENTS 35 DEVICES
FROM 3 LOTS
2
INLO INPUT
VTCM1 = 0.56V, VTCM2 = 1.0V
REPRESENTS 35 DEVICES
FROM 3 LOTS
2
1
ERROR (dB)
1
0
0
–1
–1
–2
–2
–50
–40
–30
–20
PIN (dBm)
–10
0
10
–3
–60
07368-017
ERROR (dB)
–40
2.0
3
–3
–60
–50
2.5
OUTPUT VOLTAGE (V)
3
0.5
3.0
ERROR (dB)
1
–1
Figure 18. VOUT and Log Conformance Error with Respect to 25°C Ideal Line
over Temperature vs. Input Amplitude at 3.8 GHz, CW, Typical Device
2
4
1.0
07368-016
OUTPUT VOLTAGE (V)
5
0
0
–60
3
6
1.5
Figure 17. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude at 2.6 GHz, CW
–50
–40
–30
–20
PIN (dBm)
–10
0
10
07368-020
0
–60
1
ERROR (dB)
3
2.0
07368-018
1
2
ERROR (dB)
4
2.5
07368-019
2
OUTPUT VOLTAGE (V)
5
ERROR (dB)
INLO INPUT
VTCM1 = 0.56V, VTCM2 = 1.0V
07368-015
OUTPUT VOLTAGE (V)
INHI INPUT
VTCM1 = 0.54V, VTCM2 = 1.1V
Figure 20. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude at 3.8 GHz, CW
Rev. 0 | Page 11 of 36
AD8363
3
3.0
2.5
2
2.0
1
1.5
0
1.0
–1
ERROR (dB)
OUTPUT VOLTAGE (V)
INLO INPUT
VTCM1 = 0.88V, VTCM2 = 1.0V
100MHz
900MHz
1.9GHz
2.14GHz
5.8GHz
3.8GHz
–2
0.5
2.6GHz
–40
–30
–20
PIN (dBm)
–10
–3
10
0
07368-030
–50
07368-021
0
–60
Figure 21. VOUT and Log Conformance Error with Respect to 25°C Ideal Line
over Temperature vs. Input Amplitude at 5.8 GHz, Typical Device
3
3.0
INLO INPUT
VTCM1 = 0.88V, VTCM2 = 1.0V
REPRESENTS 35 DEVICES
FROM 3 LOTS
1
1.5
0
1.0
–1
0.5
–2
QUANTITY
2.0
REPRESENTS
APPROXIMATELY
3000 PARTS FROM
SIX LOTS
800
2
ERROR (dB)
2.5
OUTPUT VOLTAGE (V)
Figure 24. Single-Ended Input Impedance (S11) vs.
Frequency; ZO = 50 Ω, INHI or INLO
600
400
–50
–40
–30
–20
PIN (dBm)
–10
–3
10
0
0
1.34
07368-022
0
–60
1.38
1.40
VTEMP (V)
1.42
1.44
1.46
Figure 25. Distribution of VTEMP Voltage at 25oC, No RF Input
Figure 22. Distribution of VOUT and Error with Respect to 25°C Ideal Line over
Temperature vs. Input Amplitude at 5.8 GHz, CW
3
2
1.36
07368-077
200
INLO INPUT
VTCM1 = 0.88V, VTCM2 = 1.0V
REPRESENTS 35 DEVICES FROM 3 LOTS
2.00
4
1.75
3
1.50
2
1.25
1
1.00
0
0.75
–1
0.50
–2
0.25
–3
0
ERROR (°C)
VTEMP (V)
ERROR (dB)
1
–1
–50
–40
–30
–20
PIN (dBm)
–10
0
10
–4
0
–50–40–30–20–10 0 10 20 30 40 50 60 70 80 90 100 110 120130
TEMPERATURE (°C)
07368-023
–3
–60
Figure 23. Distribution of Error with Respect to 25°C over Temperature vs.
Input Amplitude at 5.8 GHz, CW
07368-027
–2
Figure 26. VTEMP and Error with Respect to Straight Line vs. Temperature for
Eleven Devices
Rev. 0 | Page 12 of 36
AD8363
3
3
ERROR CW
ERROR CDMA2K PILOT CH SR1
ERROR CDMA2K 9CH SR1
ERROR CDMA2K 3 CAR 9CH SR1
ERROR CDMA2K 4 CAR 9CH SR1
2
2
1
–1
–1
–2
–2
–50
–40
–30
–20
PIN (dBm)
–10
0
10
–3
–60
Figure 27. Error from CW Linear Reference vs. Input Amplitude with
Modulation, Frequency at 900 MHz, CLPF = 0.1 μF, INHI Input
–30
–20
PIN (dBm)
–10
10
0
–1
–1
–2
–2
–40
–30
–20
PIN (dBm)
–10
0
10
–3
–60
07368-025
–50
CW
W-CDMA 1 CAR TM1 32 DPCH
QPSK
256QAM
WIMAX 256 SUBCR, 64 QAM, 10MHz BW
CDMA2K 9 CH SR1 4 CAR
–50
–40
–30
–20
PIN (dBm)
–10
0
10
07368-028
ERROR (dB)
1
0
Figure 31. Error from CW Linear Reference vs. Input Amplitude with
Modulation, Frequency at 2.6 GHz, CLPF = 0.1 μF, INHI Input
Figure 28. Error from CW Linear Reference vs. Input Amplitude with
Modulation, Frequency at 1.9 GHz, CLPF = 0.1 μF, INHI Input
1.0
160
INHI INPUT
VTCM1 = 0.52V
VTCM2 = 0.6V
140
0.5
ERROR (dB)
100
80
60
0
4.50V
4.75V
5.00V
5.25V
5.50V
–0.5
40
20
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 29. Typical Noise Spectral Density of VOUT; All CLPF Values
–1.0
–60
07368-031
1k
–50
–40
–30
PIN (dBm)
–20
–10
0
07368-032
120
0
100
0
2
1
ERROR (dB)
–40
3
ERROR CW
ERROR CDMA2K 3 CAR 9CH SR1
ERROR CDMA2K 4 CAR 9CH SR1
2
–3
–60
–50
Figure 30. Error from CW Linear Reference vs. Input Amplitude with
Modulation, Frequency at 2.14 GHz, CLPF = 0.1 μF, INHI Input
3
NOISE SPECTRAL DENSITY (nV/ Hz)
0
07368-026
ERROR (dB)
0
07368-024
ERROR (dB)
1
–3
–60
ERROR CW
ERROR W-CDMA 1 CAR TM1 64 DPCH
ERROR W-CDMA 2 CAR TM1 64 DPCH
ERROR W-CDMA 3 CAR TM1 64 DPCH
ERROR W-CDMA 4 CAR TM1 64 DPCH
Figure 32. Output Stability at 2.14 GHz with VPOS Variation, Error Normalized
to Response at 5 V, VTGT = 1.4 V (Fixed)
Rev. 0 | Page 13 of 36
AD8363
5.0
5.0
–20dBm
–30dBm
–40dBm
0dBm
4.5
4.0
4.0
3.5
VOUT (V)
2.0
1.5
0.5
0
0
–0.5
–0.5
5
6 7 8 9 10 11 12 13 14 15 16
TIME (µs)
–1.0
–2
07368-033
4
Figure 33. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz,
CLPF = 390 pF, CHPF = Open, Rising Edge
5.0
5.0
4.5
4.5
4
6
8
10 12 14 16 18 20 22 24 26 28 30
TIME (µs)
0dBm
–10dBm
–20dBm
–30dBm
–40dBm
RF
ENVELOPE
3.5
3.0
3.0
2.5
2.5
VOUT (V)
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.5
0
0
0dBm
–10dBm
–20dBm
–30dBm
–40dBm
0
1
2
TIME (ms)
3
–0.5
5
4
–1.0
–1
07368-034
–0.5
3
TCM2 LOW
TCM2 HIGH
4
4
3
Figure 37. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz,
CLPF = 0.1 μF, CHPF = Open, Falling Edge
100
SUPPLY CURRENT (mA)
5
2
VTCM2 INCREASING
VTCM2 (V)
6
1
TIME (ms)
Figure 34. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz,
CLPF = 0.1 μF, CHPF = Open, Rising Edge
6
0
07368-036
VOUT (V)
2
4.0
RF
ENVELOPE
3.5
–1.0
–1
0
Figure 36. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz,
CLPF = 390 pF, CHPF = Open, Falling Edge
4.0
OUTPUT VOLTAGE, VOUT (V)
1.5
1.0
3
–40dBm
2.0
0.5
2
–30dBm
2.5
1.0
1
–20dBm
3.0
2.5
–1.0
–2 –1 0
–10dBm
RF
ENVELOPE
3.5
RF
ENVELOPE
3.0
VOUT (V)
–10dBm
07368-035
0dBm
4.5
0
0dBm
3
2
VTCM2 DECREASING
10
1
1
07368-037
–50
–25
0
25
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
550
575
600
TIME (µs)
0.1
4.0
Figure 35. Output Response Using Power-Down Mode for Various RF Input
Levels Carrier Frequency at 2.14 GHz, CLPF = 470 pF, CHPF = 220 pF
Rev. 0 | Page 14 of 36
4.1
4.2
4.3
4.4
4.5
4.6
VTCM2 (V)
4.7
Figure 38. Supply Current vs. VTCM2
4.8
4.9
5.0
07368-051
–50dBm
0
AD8363
2.325
REPRESENTS
APPROXIMATELY
3000 PARTS FROM
SIX LOTS
600
500
2.320
VREF (V)
300
200
2.310
2.305
2.300
100
0
2.24
2.26
2.28
2.30
VREF (V)
2.32
2.34
2.36
07368-029
2.295
2.290
–40
Figure 39. Distribution of VREF, 25°C, No RF Input
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
07368-048
QUANTITY
2.315
400
Figure 41. Change in VREF with Temperature for Eleven Devices
2.320
2.34
2.318
2.33
2.316
2.32
2.31
VREF (V)
2.312
2.310
2.308
2.30
2.29
2.306
2.28
2.304
2.300
4.5
4.6
4.7
4.8
4.9
5.0
5.1
VPOS (V)
5.2
5.3
5.4
5.5
Figure 40. Change in VREF with VPOS for Nine Devices
2.26
–30
–25
–20
–15
–10
–5
PIN (dBm)
0
5
10
Figure 42. Change in VREF with Input Amplitude for Eleven Devices
Rev. 0 | Page 15 of 36
07368-049
2.27
2.302
07368-038
VREF (V)
2.314
AD8363
THEORY OF OPERATION
The AD8363 is a 6 GHz, true rms responding detector with a
40 dB measurement range at 6 GHz and a greater than 50 dB
measurement range at frequencies less than 1 GHz. It incorporates
a modified AD8362 architecture that increases the frequency range
and improves measurement accuracy at high frequencies. Log
conformance peak-to-peak ripple has been reduced to <±0.1 dB
over the entire dynamic range. Temperature stability of the rms
output measurements provides <±0.5 dB error typically over the
specified temperature range of −40°C to 85°C through proprietary
techniques.
The AD8363 is an rms-to-dc converter capable of operating
on signals of approximately 50 Hz to 6 GHz or more. Unlike
logarithmic amplifiers, the AD8363 response is waveform
independent. The device accurately measures waveforms
that have a high peak-to-rms ratio (crest factor).
The nomenclature used in this data sheet to distinguish
between a pin name and the signal on that pin is as follows:
(1)
where:
GO is the basic fixed gain.
VGNS is a scaling voltage that defines the gain slope (the decibel
change per voltage). The gain decreases with increasing VSET.
The VGA output is
VSIG = GSET × RFIN = GO × RFIN exp(VSET/VGNS)
The pin name is all upper cased, for example, VPOS,
COMM, and VOUT.
The signal name or a value associated with that pin is the
pin mnemonic with a partial subscript, for example, CLPF,
CHPF, and VOUT.
Mean(ISQR) = ITGT
(3)
This equilibrium occurs only when
Mean(VSIG2) = VTGT2
(4)
where VTGT is the voltage presented at the VTGT pin. This pin
can conveniently be connected to the VREF pin through a voltage
divider to establish a target rms voltage VATG of ~70 mV rms, when
VTGT = 1.4 V.
Because the square law detectors are electrically identical and
well matched, process and temperature dependant variations
are effectively cancelled.
INHI
VSIG
VGA
X2
SUMMING
NODE
ISQR
ITGT
VATG =
VTGT
20
X2
VTGT
INLO
GSET
CLPF
VSET
CLPF
(EXTERNAL)
VPOS
CF
(INTERNAL)
VOUT
COMM
CH
(INTERNAL)
CHPF
CHPF
(EXTERNAL)
(2)
The output of the VGA, VSIG, is applied to a wideband square
law detector. The detector provides the true rms response of the
RF input signal, independent of waveform. The detector output,
ISQR, is a fluctuating current with positive mean value. The
difference between ISQR and an internally generated current,
ITGT, is integrated by CF and the external capacitor attached to
the CLPF pin at the summing node. CF is an on-chip 25 pF filter
capacitor, and CLPF, the external capacitance connected to the
CLPF pin, can be used to arbitrarily increase the averaging time
while trading off with the response time. When the AGC loop is
at equilibrium
TEMPERATURE COMPENSATION
AND BIAS
TCM1
TCM2/PWDN
TEMPERATURE
SENSOR
TEMP (1.4V)
BAND GAP
REFERENCE
VREF (2.3V)
Figure 43. Simplified Architecture Details
Rev. 0 | Page 16 of 36
07368-076
•
The VGA gain has the form
GSET = GO exp(−VSET/VGNS)
where
RFIN is the ac voltage applied to the input terminals of the AD8363.
The AD8363 consists of a high performance AGC loop. As
shown in Figure 43, the AGC loop comprises a wide bandwidth
variable gain amplifier (VGA), square law detectors, an amplitude
target circuit, and an output driver. For a more detailed description
of the functional blocks, see the AD8362 data sheet.
•
SQUARE LAW DETECTOR AND AMPLITUDE TARGET
AD8363
By forcing the previous identity through varying the VGA setpoint,
it is apparent that
ESD
(5)
2.5kΩ
INHI
50Ω
Substituting the value of VSIG from Equation 2 results in
ESD
RMS(G0 × RFIN exp(−VSET/VGNS)) = VATG
INLO
ESD ESD ESD ESD ESD ESD
ESD ESD ESD ESD ESD ESD
ESD
(7)
where:
VSLOPE is 1 V/decade (or 50 mV/dB).
VZ is the intercept voltage.
ESD
Figure 44. RF Inputs Simplified Schematic
Extensive ESD protection is employed on the RF inputs, which
limits the maximum possible input amplitude to the AD8363.
When RMS(RFIN) = VZ, because log10(1) = 0, this implies that
VOUT = 0 V, making the intercept the input that forces VOUT = 0 V.
VZ has been fixed to approximately 280 μV (approximately
−58 dBm, referred to 50 Ω) with a CW signal at 100 MHz.
In reality, the AD8363 does not respond to signals less than
~−56 dBm. This means that the intercept is an extrapolated
value outside the operating range of the device.
If desired, the effective value of VSLOPE can be altered by using a
resistor divider between VOUT and VSET. (Refer to the
Altering the Slope section for more information.)
In most applications, the AGC loop is closed through the
setpoint interface and the VSET pin. In measurement mode,
VOUT is directly connected to VSET. (See the Measurement
Mode Basic Connections section for more information.) In
controller mode, a control voltage is applied to VSET and the
VOUT pin typically drives the control input of an amplification
or attenuation system. In this case, the voltage at the VSET pin
forces a signal amplitude at the RF inputs of the AD8363 that
balances the system through feedback. (See the Controller
Mode Basic Connections section for more information.)
RF INPUT INTERFACE
Figure 44 shows the connections of the RF inputs within the
AD8363. The input impedance is set primarily by an internal 50 Ω
resistor connected between INHI and INLO. A dc level of
approximately half the supply voltage on each pin is established
internally. Either the INHI pin or the INLO pin can be used as
the single-ended RF input pin. (See the Choice of RF Input Pin
section.) If the dc levels at these pins are disturbed,
performance is compromised; therefore, signal coupling
capacitors must be connected from the input signal to INHI
and INLO. The input signal high-pass corner formed by the
coupling capacitors and the internal resistances is
fHIGH-PASS = 1/(2 × π × 50 × C)
ESD
(6)
When connected as a measurement device, VSET = VOUT. Solving
for VOUT as a function of RFIN
VOUT = VSLOPE × log10(RMS(RFIN)/VZ)
2.5kΩ
07368-039
RMS(VSIG) = √(Mean(VSIG2)) = √(VATG2) = VATG
VBIAS
VPOS
(8)
where C is in farads and fHIGH-PASS is in hertz. The input coupling
capacitors must be large enough in value to pass the input signal
frequency of interest. The other input pin should be RF accoupled to common (ground).
CHOICE OF RF INPUT PIN
The dynamic range of the AD8363 can be optimized by choosing
the correct RF input pin for the intended frequency of operation.
Using INHI (Pin 14), users can obtain the best dynamic range at
frequencies up to 2.6 GHz. Above 2.6 GHz, it is recommended
that INLO (Pin 15) be used. At 2.6 GHz, the performance obtained
at the two inputs is approximately equal. The AD8363 was designed
with a single-ended RF drive in mind. A balun can be used to
drive INHI and INLO differentially, but it is not necessary, and
it does not result in improved dynamic range.
SMALL SIGNAL LOOP RESPONSE
The AD8363 uses a VGA in a loop to force a squared RF signal
to be equal to a squared dc voltage. This nonlinear loop can be
simplified and solved for a small signal loop response. The lowpass corner pole is given by
FreqLP ≈ 1.83 × ITGT/(CLPF)
(9)
where:
ITGT is in amperes.
CLPF is in farads.
FreqLP is in hertz.
ITGT is derived from VTGT; however, ITGT is a squared value of
VTGT multiplied by a transresistance, namely
ITGT = gm × VTGT2
(10)
gm is approximately 18.9 μs, so with VTGT equal to the typically
recommended 1.4 V, ITGT is approximately 37 μA. The value of
this current varies with temperature; therefore, the small signal
pole varies with temperature. However, because the RF squaring
circuit and dc squaring circuit track with temperature, there is no
temperature variation contribution to the absolute value of VOUT.
For CW signals,
FreqLP ≈ 67.7 × 10−6/(CLPF)
(11)
However, signals with large crest factors include low
pseudorandom frequency content that either needs to be
filtered out or sampled and averaged out. See the Choosing a
Value for CLPF section for more information.
Rev. 0 | Page 17 of 36
AD8363
TEMPERATURE SENSOR INTERFACE
The AD8363 provides a temperature sensor output with an
output voltage scaling factor of approximately 5 mV/°C. The
output is capable of sourcing 4 mA and sinking 50 μA maximum at
temperatures at or above 25°C. If additional current sink capability
is desired, an external resistor can be connected between the
TEMP and COMM pins. The typical output voltage at 25°C is
approximately 1.4 V.
VPOS
Compensating the device for the temperature drift using TCM1
and TCM2/PWDN allows for great flexibility and the user may
wish to modify these values to optimize for another amplitude
point in the dynamic range, for a different temperature range,
or for an operating frequency other than those shown in Table 4.
To find a new compensation point, VTCM1 and VTCM2 can be
swept while monitoring VOUT over the temperature at the
frequency and amplitude of interest. The optimal voltages for
VTCM1 and VTCM2 to achieve minimum temperature drift at a given
power and frequency are the values of VTCM1 and VTCM2 where
VOUT has minimum movement. See the AD8364 and ADL5513
data sheets for more information.
INTERNAL
VPAT
TEMP
12kΩ
07368-041
4kΩ
COMM
The values in Table 4 were chosen to give the best drift
performance at the high end of the usable dynamic range
over the −40°C to +85°C temperature range.
Figure 45. TEMP Interface Simplified Schematic
VREF INTERFACE
The VREF pin provides an internally generated voltage reference.
The VREF voltage is a temperature stable 2.3 V reference that is
capable of sourcing 4 mA and sinking 50 μA maximum at
temperatures at or above 25°C. An external resistor can be
connected between the VREF and COMM pins to provide
additional current sink capability. The voltage on this pin can be
used to drive the TCM1, TCM2/PWDN, and VTGT pins, if desired.
Varying VTCM1 and VTCM2 has only a very slight effect on VOUT at
device temperatures near 25°C; however, the compensation circuit
has more and more effect, and is more and more necessary for
best temperature drift performance, as the temperature departs
farther from 25°C.
Figure 47 shows the effect on temperature drift performance at
25°C and 85°C as VTCM1 is varied but VTCM2 is held constant at 0.6 V.
3
2
VTCM1 = 0.62V
VPOS
1
ERROR (dB)
INTERNAL
VOLTAGE
VREF
16kΩ
–1
07368-042
COMM
0
VTCM1 = 0.42V
25°C
85°C
–2
–3
–60
TEMPERATURE COMPENSATION INTERFACE
While the AD8363 has a highly stable measurement output with
respect to temperature, it uses proprietary techniques to make it
even more stable. For optimal performance, the output temperature
drift must be compensated for using the TCM1 and TCM2/
PWDN pins. The absolute value of compensation varies with
frequency and VTGT. Table 4 shows the recommended voltages for
the TCM1 and TCM2/PWDN pins to maintain the best
temperature drift error over the rated temperature range (−40°C <
TA < 85°C) when driven single-ended and using a VTGT = 1.4 V.
Table 4. Recommended Voltages for TCM1 and TCM2/PWDN
Frequency
100 MHz
900 MHz
1.9 GHz
2.14 GHz
2.6 GHz
3.8 GHz
5.8 GHz
TCM1 (V)
0.47
0.5
0.52
0.52
0.54
0.56
0.88
TCM2/PWDN (V)
1.0
1.2
0.51
0.6
1.1
1.0
1.0
–50
–40
–30
–20
RFIN (dBm)
–10
0
10
07368-050
Figure 46. VREF Interface Simplified Schematic
Figure 47. Error vs. Input Amplitude over Stepped VTCM1 Values,
25oC and 85oC, 2.14 GHz, VTCM2 = 0.6 V
TCM1 primarily adjusts the intercept of the AD8363 at
temperature. In this way, TCM1 can be thought of as a coarse
adjustment to the compensation. Conversely, TCM2 performs a
fine adjustment. For this reason, it is advised that when searching
for compensation with VTCM1 and VTCM2, that VTCM1 be adjusted
first, and when best performance is found, VTCM2 can then be
adjusted for optimization.
It is evident from Figure 47 that the temperature compensation
circuit can be used to adjust for the lowest drift at any input
amplitude of choice. Though not shown in Figure 47, a similar
analysis can simultaneously be performed at −40°C, or any
other temperature within the operating range of the AD8363.
Rev. 0 | Page 18 of 36
AD8363
The TCM1 and TCM2 pins have high input impedances,
approximately 5 kΩ and 500 kΩ, respectively, and can be
conveniently driven from an external source or from a fraction
of VREF by using a resistor divider. VREF does change slightly with
temperature and RF input amplitude (see Figure 41 and Figure 42);
however, the amount of change is unlikely to result in a significant
effect on the final temperature stability of the RF measurement system.
VSET INTERFACE
The VSET interface has a high input impedance of 72 kΩ.
The voltage at VSET is converted to an internal current used
to set the internal VGA gain. The VGA attenuation control is
approximately 19 dB/V.
GAIN ADJUST
VSET
54kΩ
18kΩ
2.5kΩ
Figure 48 shows a simplified schematic representation of TCM1.
See the Power-Down Interface section for the TCM2 interface.
COMM
Figure 50. VSET Interface Simplified Schematic
VPOS
OUTPUT INTERFACE
ESD
ESD
The output driver used in the AD8363 is different from the
output stage on the AD8362. The AD8363 incorporates rail-torail output drivers with pull-up and pull-down capabilities. The
closed-loop −3 dB bandwidth of the VOUT buffer with no load
is approximately 58 MHz with a single-pole roll-off of −20 dB/dec.
The output noise is approximately 45 nV/√Hz at 100 kHz, which
is independent of CLPF due to the architecture of the AD8363.
VOUT can source and sink up to 10 mA. There is an internal
load between VOUT and COMM of 2.5 kΩ.
TCM1
3kΩ
07368-043
ESD
COMM
Figure 48. TCM1 Interface Simplified Schematic
POWER-DOWN INTERFACE
The quiescent and disabled currents for the AD8363 at 25°C are
approximately 60 mA and 300 μA, respectively. The dual function
pin, TCM2/PWDN, is connected to a temperature compensation
circuit as well as a power-down circuit. Typically, when PWDN
is greater than VPOS − 0.1 V, the device is fully powered down.
Figure 38 shows this characteristic as a function of VPWDN. Note
that because of the design of this section of the AD8363, as
VTCM2 passes through a narrow range at ~4.5 V (or ~VPOS − 0.5 V),
the TCM2/PWDN pin sinks approximately 750 μA. The source
used to disable the AD8363 must have a sufficiently high current
capability for this reason. Figure 35 shows the typical response
times for various RF input levels. The output reaches within 0.1
dB of its steady-state value in approximately 35 μs; however, the
reference voltage is available to full accuracy in a much shorter
time. This wake-up response varies depending on the input
coupling and the capacitances, CHPF and CLPF.
VPOS
ESD
200Ω
200Ω
200Ω
ESD
7kΩ
VREF
INTERCEPT
TEMPERATURE
COMPENSATION
COMM
07368-044
TCM2/
PWDN
ESD
7kΩ
Figure 49. PWDN Interface Simplified Schematic
Rev. 0 | Page 19 of 36
VPOS
ESD
2pF
CLPF
VOUT
ESD
2kΩ
ESD
500Ω
COMM
Figure 51. VOUT Interface Simplified Schematic
07368-046
3kΩ
SHUTDOWN POWER-UP
CIRCUIT CIRCUIT
07368-045
Performance varies slightly from device to device; therefore,
optimal VTCM1 and VTCM2 values must be arrived at statistically
over a population of devices to be useful in mass production
applications.
AD8363
VTGT INTERFACE
BASIS FOR ERROR CALCULATIONS
The target voltage can be set with an external source or by
connecting the VREF pin (nominally 2.3 V) to the VTGT pin
through a resistive voltage divider. With 1.4 V on the VTGT pin,
the rms voltage that must be provided by the VGA to balance the
AGC feedback loop is 1.4 V × 0.05 = 70 mV rms. Most of the
characterization information in this data sheet was collected at
VTGT = 1.4 V. Voltages higher and lower than this can be used;
however, doing so increases or decreases the gain at the internal
squaring cell, which results in a corresponding increase or
decrease in intercept. This in turn affects the sensitivity and the
usable measurement range. Because the gain of the squaring
cell varies with temperature, oscillations or a loss in measurement
range can result. For these reasons, do not reduce VTGT below 1.3 V.
The slope and intercept used in the error plots are calculated
using the coefficients of a linear regression performed on data
collected in its central operating range. The error plots in the
Typical Performance Characteristics section are shown in two
formats: error from the ideal line and error with respect to 25°C.
The error from the ideal line is the decibel difference in VOUT
from the ideal straight-line fit of VOUT calculated by the linearregression fit over the linear range of the detector, typically at
25°C. The error in decibels is calculated by
VPOS
ESD
g × X2
VTGT
ITGT
50kΩ
ESD
50kΩ
ESD
07368-047
10kΩ
COMM
Figure 52. VTGT Interface Simplified Schematic
OPERATION TO 125°C
Most of the information in this data sheet describes operation up
to, but not exceeding, 85°C. Operation up to 125°C is possible;
however, the performance of the AD8363 above 85°C can be
degraded. Figure 53 shows the typical operation at 125°C as
compared to other temperatures using the TCM1 and TCM2
values in Table 4. Temperature compensation can be optimized
for operation above 85°C by modifying the voltages on the TCM1
and TCM2 pins from those shown in Table 4.
3
6
–40°C
+25°C
+85°C
+125°C
4
1
3
0
2
–1
INHI INPUT
VTCM1 = 0.52V, VTCM2 = 0.6V
1
0
–60
–50
–40
–30
–20
PIN (dBm)
–10
0
Figure 53. VOUT and Log Conformance Error vs.
Input Amplitude at 2.14 GHz, −40°C to +125°C
ERROR (dB)
2
–2
–3
10
07368-053
OUTPUT VOLTAGE (V)
5
Error (dB) = (VOUT − Slope × (PIN − PZ))/Slope
(12)
where PZ is the x-axis intercept expressed in dBm (the input
amplitude that produces a 0 V output, if such an output is possible).
The linear range of the detector was assumed to be −20 dBm to
−40 dBm. The error from the ideal line is not a measure of absolute
accuracy because it is calculated using the slope and intercept of
each device. However, it verifies the linearity and the effect of
temperature and modulation on the response of the device.
Examples of this type of plot are Figure 3 and Figure 4. The slope
and intercept that form the ideal line are those at 25°C with CW
modulation. Figure 27, Figure 28, Figure 30, and Figure 31 show
the error with various popular forms of modulation with respect to
the ideal CW line. This method for calculating error is accurate
assuming each device is calibrated at room temperature and/or
CW modulation, as appropriate.
In the second plot format, the VOUT voltage at a given input
amplitude and temperature is subtracted from the corresponding
VOUT at 25°C and then divided by the 25°C slope to obtain an error
in decibels. This type of plot does not provide any information on
the linear-in-dB performance of the device; it merely shows the
decibel equivalent of the deviation of VOUT over temperature,
given a calibration at 25°C. When calculating error from any
one particular calibration point, this error format is accurate. It is
accurate over the full range shown on the plot assuming enough
calibration points are used. Figure 5 shows this plot type.
The error calculation for Figure 32 is in the same method as the
first type previously mentioned, except that instead of varying
the operating temperature of the device, the operating voltage
was varied and the error is expressed with the nominal (5 V)
response as the base response.
The error calculations for Figure 26 are similar to that for the
VOUT plots. The slope and intercept of the VTEMP function vs.
temperature were determined and applied as follows:
Error (°C) = (VTEMP − Slope × (Temp − TZ))/Slope
(13)
where:
TZ is the x-axis intercept expressed in degrees Celsius (the
temperature that would result in a VTEMP of 0 V (an
extrapolation because this is not possible).
Temp is the temperature of the AD8363 in degrees Celsius.
Slope is expressed in V/°C.
VTEMP is the voltage at the TEMP pin at that temperature.
Rev. 0 | Page 20 of 36
AD8363
MEASUREMENT MODE BASIC CONNECTIONS
The AD8363 is placed in measurement mode by connecting
VOUT to VSET. This closes the AGC loop within the device
with VOUT representing the VGA control voltage, which is
required to present the correct rms voltage at the input of the
internal square law detector.
The AD8363 requires a single supply of nominally 5 V. The
supply is connected to the two supply pins, VPOS. Decouple
the pins using two capacitors with values equal or similar to
those shown in Figure 54. These capacitors must provide a low
impedance over the full frequency range of the input, and they
should be placed as close as possible to the VPOS pins. Use two
different capacitor values in parallel to provide a broadband ac
short to ground.
As the input signal is swept over its nominal input dynamic range
of −50 dBm to 0 dBm, the output swings from approximately 0 V
to a high value of approximately 3 V.
Input signals can be applied differentially or single-ended; however,
in both cases, the input impedance is 50 Ω. Most performance
information in this data sheet was derived with a single-ended
drive. The optimal measurement range is achieved using a singleended drive on the INHI pin at frequencies below 2.6 GHz (as
shown in Figure 54), and likewise, optimal performance is achieved
using the INLO pin above 2.6 GHz (similar to Figure 54; except
INLO is ac-coupled to the input and INHI is ac-coupled to ground).
VPOS2
C7
0.1µF
VREF
C5
100pF
R10
845Ω
16
VREF
INHI
AD8363
VSET
INLO
DUT1
VOUT
TCM1
1
CLPF
2
3
7
6
VOUT
5
C9
0.1µF
4
C3
OPEN
C4
100pF
PADDLE
AGND
C13
0.1µF
TCM2/PWDN
VPOS1
Figure 54. Measurement Mode Basic Connections
Rev. 0 | Page 21 of 36
8
07368-062
C12
0.1µF TCM1
TEMP
NC
COMM
15
TEMP
9
VPOS
14
CHPF
LOW FREQUENCY INPUT
13
TCM2/PWDN
C10
0.1µF
10
COMM
11
VTGT
12
VPOS
R11
1.4kΩ
AD8363
DEVICE CALIBRATION AND ERROR CALCULATION
The measured transfer function of the AD8363 at 2.14 GHz is
shown in Figure 55. It shows plots of both output voltage vs.
input amplitude (power) and calculated error vs. input amplitude
(power). As the input power varies from −50 dBm to 0 dBm,
the output voltage varies from 0.25 V to about 2.8 V.
5.0
2.5
+25°C
–40°C
+85°C
4.0
1.5
3.5
3.0
0.5
2.5
2.0
–0.5
ERROR (dB)
OUTPUT VOLTAGE, VOUT (V)
4.5
1.5
1.0
–1.5
0
–60
–50
–40
–30
–20
PIN, INHI (dBm)
–10
0
–2.5
10
07368-064
0.5
The log conformance error is the deviation of the detector from
the ideal calculated power and is given by
Error (dB) = (VOUT(MEASURED) − VOUT(IDEAL))/Slope
(18)
Figure 56 includes a plot of the error at 25°C, the temperature at
which the log amp is calibrated. Note that the error is not zero
because the detector does not perfectly follow the ideal straight
line. The error at the calibration points (in this case, −40 dBm
and −21 dBm) are, however, equal to zero by definition. Note that
Figure 55 is slightly different from those found in the Typical
Performance Characteristics section; its slope and intercept are
calculated using a two-point calculation and not based on multiple
points, as was used for the Typical Performance Characteristics.
Figure 55 also includes error plots for the output voltage at −40°C
and +85°C. These error plots are calculated using the slope and
intercept at 25°C. Another way of saying this is that the hot and
cold temperatures are calculated with respect to the output voltage
at ambient, and by definition, the error at ambient becomes
equal to 0. This is consistent with calibration in a mass production
environment, where calibration at temperature is not practical.
5.0
2.5
Figure 55. 2.14 GHz Transfer Function Using Two-Point Calibration
+25°C
–40°C
+85°C
where:
Slope is the change in output voltage divided by the change in
power (dB).
Intercept is the calculated input power level at which the output
voltage would be 0 V. (Note that Intercept is a theoretical value;
the output voltage can never achieve 0 V).
In general, calibration is performed by applying two (or more)
known signal levels into the input of the AD8363 and by measuring
the corresponding output voltages. The calibration points are
generally within the linear-in-dB operating range of the device
(see the Specifications section for more details).
The slope and intercept are calculated as follows:
Slope = (VOUT1 − VOUT2)/(PIN1 − PIN2)
(15)
Intercept = PIN1 − (VOUT1/Slope)
(16)
The previous formula for intercept is a shorthand formula based
upon Equation 14 and the assumption that the AD8363 is
operating within the linear-in-dB operating range. When the
slope and intercept are calculated, an equation can be written
that allows the calculation of the ideal input power based on the
output voltage of the detector.
PIN (unknown) = (VOUT1(MEASURED)/Slope) + Intercept
1.5
3.5
3.0
0.5
2.5
2.0
–0.5
ERROR (dB)
(14)
4.0
1.5
1.0
–1.5
0.5
0
–60
–50
–40
–30
–20
PIN, INHI (dBm)
–10
0
–2.5
10
07368-065
VOUT = Slope × (PIN − Intercept)
OUTPUT VOLTAGE, VOUT (V)
4.5
Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve high accuracy.
The equation for output voltage can be written as
Figure 56. 2.14 GHz Transfer Function Using a Three-Point Calibration
SELECTING AND INCREASING CALIBRATION
POINTS TO IMPROVE ACCURACY OVER A
REDUCED RANGE
Choose the amount and location of the calibration points carefully
because they can optimize the performance of the detector. In
some applications, increasing the dynamic range of the AD8363
may be desirable; however, in others, very high accuracy is required
at one power level or over a reduced input range. For example,
in a wireless transmitter, the accuracy of the high power amplifier
(HPA) is most critical at or close to full power. These objectives
can be achieved by the proper selection of the amount and
location of the calibration points.
(17)
Rev. 0 | Page 22 of 36
AD8363
Even though a large amount of calibration points is less practical,
Figure 14 is helpful because it shows the true temperature
performance no matter the location of the calibration point. As
can be seen from both Figure 14 and Figure 56, the temperature
performance tends to change at power levels above −15 dBm.
As shown in Figure 14, because the distribution of temperature
performance is tight for the higher power levels, VTCM1 and
VTCM2 can be optimized for the higher power levels, or a separate
offset can be placed in the calibration routine that adds offsets for
changes in temperature.
Figure 57 shows a two-point calibration like Figure 55 but the
calibration points were changed from −40 dBm and −21 dBm
to −39 dBm and −11 dBm. This demonstrates how calibration
points can be adjusted to increase dynamic range at the expense
of linearity. The higher power calibration point was moved to a
point where the AD8363 is not as linear. At 25°C, there is an error
of 0 dB at the calibration points. Note that the range over which
the AD8363 maintains an error of <±0.5 dB is extended to +53 dB
at 25°C. The disadvantage of this approach is that linearity suffers
and the linearity at −25 dBm degrades by about 0.2 dB and the
error at +3 dBm increases by about 0.7 dB.
5.0
+25°C
–40°C
+85°C
1.5
0.5
2.5
2.0
–0.5
ERROR (dB)
3.0
1.5
1.0
–1.5
0.5
0
–60
8
7
TEMP
VSET
R1
6
VOUT
R2
5
CLPF
Figure 58. Altering the Slope
Use moderately low resistance values to minimize the scaling
errors from the approximately 72 kΩ input resistance at the
VSET pin. Note that this resistor string also loads the output,
and eventually, it reduces the load driving capabilities, if very
low values are used. Equation 19 can be used to calculate the
resistor values.
R1 = R2' (SD/52 − 1)
(19)
The typical slope of the AD8363 is 52; adjust this as needed.
3.5
–50
–40
–30
–20
PIN, INHI (dBm)
–10
0
–2.5
10
Figure 57. 2.14 GHz Transfer Function with Change in
Two-Point Calibration Points
07368-066
OUTPUT VOLTAGE, VOUT (V)
4.0
None of the changes to operating conditions discussed so far
effect the AD8363 logarithmic slope. The slope of the AD8363
can be easily increased or decreased. To reduce the slope, add a
voltage divider on the output, VOUT. To increase the slope, control
the fraction of VOUT that is fed back to the setpoint interface at
the VSET pin. When the full signal from VOUT is applied to
VSET, the slope assumes its nominal value of 52 mV/dB. It can
be increased by including a voltage divider between these pins,
as shown in Figure 58.
where:
SD is the desired slope, expressed in mV/dB.
R2' is the value of R2 in parallel with 72 kΩ.
2.5
4.5
ALTERING THE SLOPE
07368-067
Increasing the amount of calibration points can increase the
accuracy of the room temperature performance over a select
power level. Figure 56 shows the same measured data as Figure 55;
except that one calibration point was added at −7 dBm giving
an increase in room temperature linearity between −20 dBm to
+4 dBm. Figure 56 is similar to Figure 14, except Figure 14 includes
more parts and assumes many more calibration points, specifically
1 dB steps from −20 dBm to −40 dBm.
Figure 59 shows a comparison between the regular slope of a
part and when the slope is doubled. For this example, R1 =
1.65 kΩ and R2 = 1.69 kΩ (R2' = 1.65 kΩ). The initial slope
was 52 mV/dB, and it increased to 104 mV/dB. The choice of
100 mV/dB scaling is useful when the output is applied to a
digital voltmeter because the displayed number directly reads
as a decibel quantity with only a decimal point shift.
When measuring a particular section of the input range,
operating at a high slope is useful. With a slope of 104 mV/dB,
a measurement range of 50 dB corresponds to a 5.2 V change in
VOUT, exceeding the capacity of the output stage of the AD8363,
when operating on a 5 V supply. Figure 59 clearly shows this effect.
Rev. 0 | Page 23 of 36
AD8363
When interfacing with an ADC, use as much of the input
dynamic range as possible to maximize the resolution. It is also
important that the VOUT voltage of the AD8363 does not exceed
the range accepted by the input of the ADC for the power levels
of interest. This must take into account the part-to-part variation of
the AD8363 and its variation over temperature. This is especially
important when the slope is increased. The VOUT distribution
is well characterized at major frequencies bands in the Typical
Performance Characteristics section. Most of the VOUT variation
from part to part and over temperature is due to an intercept
shift; therefore, increasing the slope should not increase the
distribution greatly. When increasing the slope, the intercept
does not change greatly. In Figure 59, the intercept changed
by 0.2 dB after the slope change. Therefore, it is possible to
calculate the maximum voltage for a particular power level
by using the following equation:
NewVMAX = OldVMAX (New Slope/Old Slope)
(20)
For example, Figure 10 shows that the maximum voltage for a
−20 dBm input at 1.9 GHz is 2 V. If the slope is doubled from
52 mV/dB to 104 mV/dB, the maximum voltage at the new
slope is 4 V. The REFIN voltage of the ADC (the voltage that
sets the maximum readable voltage in the ADC) is set to 4.16 V,
assuming a 3 dB margin on its input.
5
5.0
3
3.5
2
3.0
1
2.5
0
2.0
–1
1.5
–2
1.0
–3
0.5
–4
0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
PIN (dBm)
0
5
–5
10
CLPF > 20 × 10−3/FREQRFIN
(21)
where:
ERROR (dB)
VOUT (V)
4.0
In measurement mode, take care in choosing CHPF and CLPF
because there is a potential to create oscillations. In general, make
the capacitance on the CLPF pin as large as possible; there is no
maximum on the amount of capacitance that can be added to
this pin. Generally, there is no need for an external capacitor on the
CHPF pin; therefore, the pin can be left open. However, when
trying to get a fast response time and/or when working at low
frequencies, extra care in choosing the proper capacitance values
for CHPF and CLPF is prudent. With the gain control pin (VSET)
connected to VOUT, VSET can slew at a rate determined by the
on-chip squaring cell and CLPF. When VSET is changing with time,
the dc offsets in the VGA also vary with time. The speed at
which VSET slews can create a time varying offset that falls within
the high-pass corner set by CHPF. Therefore, in measurement mode,
take care to set CLPF appropriately to reduce the slew. It is also worth
noting that most of the typical performance data was derived with
CLPF = 3.9 nF and CHPF = 2.7 nF and with a CW waveform.
The minimum appropriate CLPF based on slew rate limitations is
as follows
4
CLPF is in farads.
FREQRFIN is in hertz.
07368-068
4.5
100mV SLOPE
50mV SLOPE
ERROR 50mV SLOPE
ERROR 100mV SLOPE
The input offset voltage varies depending on the actual gain at
which the VGA is operating and, therefore, on the input signal
amplitude. When a large CHPF value is used, the offset correction
process can lag the more rapid changes in the gain of the VGA,
which can increase the time required for the loop to fully settle
for a given steady input amplitude. This can manifest itself in a
jumpy, seemingly oscillatory response of the AD8363.
Figure 59. Slope Change from 52 mV/dB to 104 mV/dB, Frequency = 2.14 GHz
This takes into account the on-chip 25 pF capacitor, CF, in
parallel with CLPF. However, because there are other internal
device time delays that affect loop stability, use a minimum CLPF
of 390 pF.
The minimum appropriate CHPF for a given high-pass pole
frequency is
CHPF = 29.2 × 10−6/FHPPOLE − 25 pF
OFFSET COMPENSATION/MINIMUM CLPF AND
MAXIMUM CHPF CAPACITANCE VALUES
(22)
where FHPPOLE is in hertz.
An offset-nulling loop is used to address small dc offsets within
the internal VGA as shown in Figure 60. The high-pass corner
frequency of this loop is set to about 1 MHz using an on-chip
25 pF capacitor, which is sufficiently low for most RF applications.
The high-pass corner can be lowered further by connecting a
capacitor between CHPF and VPOS.
The subtraction of 25 pF is a result of the on-chip 25 pF
capacitor in parallel with the external CHPF. Typically, choose
CHPF to give a pole (3 dB corner) at least 1 decade below the
desired signal frequency. Note that the high pass corner of the
offset compensation system is approximately 1 MHz without an
external CHPF; therefore, adding an external capacitor lowers the
corner frequency.
Rev. 0 | Page 24 of 36
AD8363
3.
It can also be noted that per Equation 9
Figure 61 shows how residual ripple, rise time, and fall time
vary with filter capacitance when the AD8363 is driven by a
single carrier CDMA2000 9CH SR1 signal at 2.14 GHz. The rise
time and fall time is based on a signal that is pulsed between no
signal and 10 dBm but is faster if the input power change is less.
110Ω
1pF
110Ω
1pF
CHPF
gm2
VX
40dB
g × X2
IRF
07368-040
A=1
2100
250
1750
200
1400
150
1050
100
700
50
350
10
20
30
40
50
60
70
CLPF CAPACITANCE (nF)
80
90
0
100
Figure 61. Residual Ripple, Rise Time, and Fall Time vs. CLPF Capacitance,
Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz with 10 dBm Pulse
gm1
gm
300
0
VGA
RFIN
RESIDUAL RIPPLE (mV)
RISE TIME (µs)
FALL TIME (µs)
0
VPOS
25pF
(INTERNAL)
2450
350
FreqLP ≈ 1.83 × ITGT/(CLPF)
A CLPF of 470 pF results in a small signal low-pass corner
frequency of approximately 144 kHz. This reflects the bandwidth
of the measurement system, and how fast the user can expect
changes on the output. It does not imply any limitations on the
input RF carrier frequency.
2800
400
FALL TIME (µs)
2.
Choose the input coupling capacitors that have a 3 dB
corner at least one decade below the input signal frequency.
From Equation 8, C > 10/(2 × π × RFIN × 50) = 32 pF
minimum. According to this calculation, 32 pF is sufficient;
however, the input coupling capacitors should be a much
larger value, typically 0.1 μF. The offset compensation
circuit, which is connected to CHPF, should be the true
determinant of the system high-pass corner frequency and
not the input coupling capactitors. With 0.1 μF coupling
capacitors, signals as low as 32 kHz can couple to the input,
which will be well below the system high-pass frequency.
Choose CLPF to reduce instabilities due to VSET slew rate.
See Equation 21, where FRQRFIN = 1 GHz, and this results in
CLPF > 20 pF. However, as previously mentioned, values below
390 pF are not recommended. For this reason, a 470 pF
capacitor was chosen. In addition, if fast response times are
not required, an even larger CLPF value than given here
should be chosen.
Choose CHPF to set a 3 dB corner to the offset compensation
system. See Equation 22, where FHPPOLE is in this case
100 MHz, one decade below the desired signal. This results
in a negative number and, obviously, a negative value is not
practical. Because the high-pass corner frequency is already
1 MHz, this result simply illustrates that the appropriate
solution is to use no external CHPF capacitor.
The Small Signal Loop Response section and the Offset
Compensation/Minimum CLPF and Maximum CHPF
Capacitance Values section discussed how to choose the
minimum value capacitance for CLPF based on a minimum
capacitance of 390 pF, slew rate limitation, and frequency of
operation. Using the minimum value for CLPF allows the quickest
response time for pulsed type waveforms (such as WiMAX) but
also allows the most residual ripple on the output caused by the
pseudorandom modulation waveform. There is not a maximum
for the capacitance that can be applied to the CLPF pin, and in
most situations, a large enough capacitor can be added to remove
the residual ripple caused by the modulation and yet allow a fast
enough response to changes in input power.
07368-069
1.
CHOOSING A VALUE FOR CLPF
RESIDUAL RIPPLE (mV p-p)
RISE TIME (µs)
The following example illustrates the proper selection of the input
coupling capacitors, minimum CLPF, and maximum CHPF when
using the AD8363 in measurement mode for a 1 GHz input signal.
Figure 60. Offset Compensation Circuit
Rev. 0 | Page 25 of 36
AD8363
Table 5 shows the recommended values of CLPF for popular
modulation schemes. For nonpulsed waveforms, increase CLPF
until the residual output noise falls below 50 mV (±0.5 dB). In
each case, the capacitor can be increased to further reduce the
noise. A 10% to 90% step response to an input step
is also listed. Where the increased response time is unacceptably
high, reduce CLPF, which increases the noise on the output. Due
to the random nature of the output ripple, if it is sampled by
an ADC, averaging in the digital domain further reduces the
residual noise.
System specifications determine the necessary rise time and fall
time. For example, the suggested CLPF value for WiMAX assumes
that it is not necessary to measure the power in the preamble.
Figure 62 shows how the rise time cuts off the preamble. Note
that the power in the preamble can be easily measured; however,
the CLPF value would have to be reduced slightly, and the noise in
the main signal would increase.
CH1 RISE
81.78µs
CH1 FALL
1.337ms
1
CH1 500mV
M 1.00ms
T 10.00%
A CH1
600mV
07368-054
Table 5 gives CLPF values to minimize noise while trying to keep
a reasonable response time. For nonpulsed type waveforms,
averaging is not required on the output. For pulsed waveforms,
the smaller the noise, the less averaging is needed on the output.
T
Figure 62. AD8363 Output to a WiMAX 802.16, 64 QAM, 256 Subcarriers,
10 MHz Bandwidth Signal with CLPF = 0.027 μF
As shown in Figure 61, the fall time for the AD8363 increases
faster than the rise time with an increase in CLPF capacitance.
Some pulse-type modulation standards require a fast fall time as
well as a fast rise time, and in all cases, less output ripple is desired.
Placing an RC filter on the output reduces the ripple, according
to the frequency content of the ripple and the filter’s poles and
zeros. Using an RC output filter also changes the rise and fall
time vs. the output ripple response as compared to increasing
the CLPF capacitance.
Table 5. Recommended CLPF Values for Various Modulation Schemes
Modulation/Standard
W-CDMA, 1Carrier, TM1-64
W-CDMA, 1Carrier, TM1-64 (EVDO)
W-CDMA 4Carrier, TM1-64
CDMA2000, 1Carrier, 9CH
CDMA2000, 3Carrier, 9CH
WiMAX 802.16 , 64 QAM, 256 Subcarriers, 10 MHz Bandwidth
6C TD-SCDMA
1C TD-SCDMA
Crest Factor (dB)
12
12
11
9.1
11
14
14
11.4
Rev. 0 | Page 26 of 36
CLPF
0.1 μF
3900 pF
0.1 μF
0.1 μF
0.1 μF
0.027 μF
0.01 μF
0.01 μF
Residual Ripple
(mV p-p)
15
150
8
10
13
10
69
75
Response Time (Rise/Fall)
10% to 90%
236 μs/2.9 ms
8.5 μs/100 μs
240 μs/2.99 ms
210 μs/3.1 ms
215 μs/3.14 ms
83 μs/1.35 ms
24 μs/207 μs
24 μs /198 μs
AD8363
Figure 63 shows the response for a 2.14 GHz pulsed signal,
with CLPF = 3900 pF. The residual ripple from a single carrier
CDMA2000 9CH SR1 signal is 150 mV p-p. (The ripple is not
shown in Figure 63. The ripple was measured separately.) Figure 64
shows the response for a 2.14 GHz pulse signal with a CLPF of
390 pF and an output filter that consists of a series 75 Ω resistor
(closest to the output) followed by a 0.15 μF capacitor to ground.
The residual ripple for this configuration is also 150 mV p-p.
Note that the rise time is faster and the fall time is slower when
the larger CLPF is used to obtain a 150 mV p-p ripple.
T
CH1 RISE
8.480µs
CH1 FALL
101.4µs
CH1 AMPL
2.37V
M 100µs
T 10.40%
A CH1
720mV
Figure 63. Pulse Response with CLPF = 3900 pF Resulting in a 150 mV p-p
Ripple for a Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz
T
8
7
6
5
TEMP
VSET
VOUT
75Ω
CLPF
OSCILLOSCOPE
PROBE
CH1 RISE
13.66µs
0.15µF
390pF
CH1 FALL
35.32µs
In addition to being a measurement device, the AD8363 can
also be configured to control rms signal levels, as shown in
Figure 65.
The RF input to the device is configured as it was in measurement
mode and either input can be used. A directional coupler taps
off some of the power being generated by the VGA. If loss in the
main signal path is not a concern, and there are no issues with
reflected energy from the next stage in the signal chain, a power
splitter can be used instead of a directional coupler. Some
additional attenuation may be required to set the maximum
input signal at the AD8363 to be equal to the recommended
maximum input level for optimum linearity and temperature
stability at the frequency of operation.
The VSET and VOUT pins are no longer shorted together. VOUT
now provides a bias or gain control voltage to the VGA. The gain
control sense of the VGA must be negative and monotonic, that is,
increasing voltage tends to decrease gain. However, the gain
control transfer function of the device does not need to be well
controlled or particularly linear. If the gain control sense of the
VGA is positive, an inverting op amp circuit with a dc offset
shift can be used between the AD8363 and the VGA to keep the
gain control voltage in the 0.03 V to 4.8 V range.
VSET becomes the set-point input to the system. This can be
driven by a DAC, as shown in Figure 65, if the output power is
expected to vary, or it can simply be driven by a stable reference
voltage, if constant output power is required. This DAC should
have an output swing that covers the 0.15 V to 3.5 V range. The
AD7391 and AD7393 serial input and parallel input 10-bit DACs
provide adequate resolution (4 mV/bit) and an adjustable
output swing over 4.5 V.
CH1 AMPL
2.36V
VGA OR VVA
(OUTPUT POWER
DECREASES AS
VAPC INCREASES)
1
PIN
M 100µs
T 10.60%
A CH1
750mV
VAPC
07368-071
CH1 500mV
POUT
ATTENUATOR
(0.03V TO 4.8V AVAILABLE SWING)
Figure 64. Pulse Response with CLPF = 390 pF and Series 75 Ω Resistor
Followed by a 0.15 μF Capacitor to Ground, Resulting in a 150 mV p-p
Ripple for a Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz
VOUT
C10
INHI
RF PULSE RESPONSE
AD8363
The response of the AD8363 to pulsed RF waveforms is affected
by VTGT. Referring to Figure 33 and Figure 34, there is a period
of inactivity between the start of the RF waveform and the time
at which VOUT begins to show a reaction. This happens as a result of
the implementation of the balancing of the squarer currents within
the AD8363. This delay can be reduced by decreasing VTGT;
however, as previously noted in the VTGT Interface section,
this has implications on the sensitivity, intercept, and dynamic
range. While the delay is reduced, reducing VTGT increases the
rise and fall time of VOUT.
INLO
C12
VSET
CLPF
C9
SEE TEXT
DAC
Rev. 0 | Page 27 of 36
(0.15V TO 3.5V)
Figure 65. Controller Mode Operation for Automatic Power Control
07368-063
CH1 500mV
07368-070
1
CONTROLLER MODE BASIC CONNECTIONS
AD8363
For more information on controller mode, see the Controller
Mode Basic Connections section.
PIN
C5
100pF
T1
INHI
OPHI
INLO
OPLO
C6
100pF
The relationship between VSET and the RF input follows the
measurement mode behavior of the device. For example, Figure 6
shows the measurement mode transfer function at 900 MHz
and that an input power of −10 dBm yields an output voltage
of approximately 2.5 V. Therefore, in controller mode, if VSET is
2.5 V, the AD8363 output would go to whatever voltage is
necessary to set the AD8363 input power to −10 dBm.
C11
100pF
ADL5330
POUT
T2
C12
100pF
GAIN
AD8062
10kΩ
10kΩ
10kΩ
10kΩ
5V
CONSTANT OUTPUT POWER OPERATION
C10
0.1µF
VOUT
0.52V
TCM1
INHI
AD8363
0.6V
TCM2
VSET
INLO
CLPF
C12
0.1µF
C9
0.1µF
0.95V
Figure 66. Constant Power Circuit
–25.0
–25.5
–26.0
POUT (dBm)
In controller mode, the AD8363 can be used to hold the output
power of a VGA stable over a broad temperature/input power
range. This is useful in topologies where a transmit card is driving
an HPA, or when connecting any two power sensitive modules
together. Figure 66 shows a schematic of a circuit setup that holds
the output power to approximately −26 dBm at 2.14 GHz, when
the input power is varied over a 40 dB dynamic range. Figure 67
shows the results. A portion of the output power is coupled off
using a 10 dB coupler, and it is then fed into the AD8363. VSET is
fixed at 0.95 V, which forces to AD8363 output voltage to control
the ADL5330 so that the input to the AD8363 is approximately
−36 dBm. If the AD8363 was in measurement mode and a
−36 dBm input power is applied, the output voltage would be
0.95 V. A general-purpose, rail-to-rail op amp (AD8062) is used
to invert the slope of the AD8363 so that the gain of the ADL5330
decreases as the AD8363 control voltage increases. The output
power is controlled to a 10 dB higher power level than that seen
by the AD8363 due to the coupler. The high end power is
limited by the linearity of the VGA (ADL5330) with high
attenuation and can be increased by using a higher linearity VGA.
10dB
COUPLER
07368-072
In general, CLPF should be chosen to provide stable loop operation
for the complete output power control range. If the slope (in
dB/V) of the gain control transfer function of the VGA is not
constant, CLPF must be chosen to guarantee a stable loop when
the gain control slope is at its maximum. In addition, CLPF must
provide adequate averaging to the internal low range squaring
detector so that the rms computation is valid. Larger values of CLPF
tend to make the loop less responsive.
The low end power is limited by the maximum gain of the VGA
(ADL5330) and can be increased by using a VGA with more
gain. The temperature performance is directly related to the
temperature performance of the AD8363 at 2.14 GHz and
−26 dBm, using TCM1 = 0.52 V and TCM2 = 0.6 V. All other
temperature variations are removed by the AD8363.
–26.5
–27.0
–20°C
–40°C
+85°C
+25°C
0°C
–27.5
–28.0
–40
–35
–30
–25
–20
–15
PIN (dBm)
–10
–5
Figure 67. Performance of the Circuit Shown in Figure 66
Rev. 0 | Page 28 of 36
0
07368-055
When VSET is set to a particular value, the AD8363 compares
this value to the equivalent input power present at the RF input.
If these two values do not match, VOUT increases or decreases in
an effort to balance the system. The dominant pole of the error
amplifier/integrator circuit that drives VOUT is set by the capacitance
on the CLPF pin; some experimentation may be necessary to
choose the right value for this capacitor.
AD8363
A voltmeter measured the subsequent response to the stimulus,
and the results were stored in a database for later analysis. In this
way, multiple AD8363 devices were characterized over amplitude,
frequency, and temperature in a minimum amount of time.
DESCRIPTION OF RF CHARACTERIZATION
The general hardware configuration used for most of the AD8363
characterization is shown in Figure 68. The AD8363 was driven
in a single-ended configuration for all characterization.
The RF stimulus amplitude was calibrated up to the connector
of the circuit board that carries the AD8363. However, the
calibration does not account for the slight losses due to the
connector and the traces from the connector to the device
under test. For this reason, there is a small absolute amplitude
error (<0.5 dB) not accounted for in the characterization data.
Characterization of the AD8363 employed a multisite test
strategy. Several AD8363 devices mounted on circuit boards
constructed with Rogers 3006 material was simultaneously
inserted into a remotely-controlled thermal test chamber.
A Keithley S46 RF switching network connected an Agilent
E8251A signal source to the appropriate device under test. An
Agilent 34980A switch matrix provided switching of dc power
and metering for the test sites. A PC running Agilent VEE Pro
controlled the signal source, switching, and chamber temperature.
This implies a slight error in the reported intercept; however,
this is generally not important because the slope and the relative
accuracy of the AD8363 are not affected.
The typical performance data was derived with CLPF = 3.9 nF
and CHPF = 2.7 nF with a CW waveform.
AGILENT E3631A
DC POWER
SUPPLIES
AGILENT 34980A
SWITCH MATRIX/
DC METER
AGILENT E8251A
MICROWAVE
SIGNAL
GENERATOR
KEITHLEY S46
MICROWAVE
SWITCH
AD8363
CHARACTERIZATION
BOARD – TEST SITE 1
AD8363
CHARACTERIZATION
BOARD – TEST SITE 2
AD8363
PERSONAL
COMPUTER
DC
DATA AND CONTROL
Figure 68. General RF Characterization Configuration
Rev. 0 | Page 29 of 36
07368-075
RF
CHARACTERIZATION
BOARD – TEST SITE 3
AD8363
EVALUATION AND CHARACTERIZATION CIRCUIT
BOARD LAYOUTS
Figure 69 to Figure 73 show the evaluation board for the AD8363.
VTGT
VREF
VPOS
C7
0.1µF
VPOS
R10
845Ω
11
15
C6
OPEN
C12
0.1µF
16
TCM1
R17
OPEN
NC
INHI
AD8363
VSET
INLO
DUT1
VOUT
R18
OPEN
1
VREFC
CLPF
2
3
8
7
R13
OPEN
R6
0Ω
VOUT
R15
0Ω
R1
0Ω
6
VOUT
5
C9
0.1µF
C8
OPEN
R5
0Ω
4
PADDLE
AGND
TCM2/PWDN
R12
OPEN
R2
OPEN
TEMP
TCM1
VSET
TEMP
COMM
14
IN
C5
100pF
9
VPOS
C11
OPEN
CHPF
13
TCM2/PWDN
C10
0.1µF
10
VREF
VTGT
12
R14
0Ω
VPOS
R11
1.4kΩ
R8
0Ω
COMM
R7
0Ω
C3
OPEN
R9
OPEN
R16
0Ω
C4
100pF
GND
GNDI
C13
0.1µF
VREFC
VPOS1
07368-074
VPOSC
Figure 69. Evaluation Board Schematic
Table 6. Bill of Materials
Component
C6, C10,
C11, C12
R7, R8,
R10, R11
C4, C5, C7,
C13, R14, R16
Function/Notes
Input. The AD8363 is single ended driven. At frequencies ≤2.6 GHz, the best dynamic range is achieved by
driving Pin 14 (INHI). When driving INHI, populate C10 and C12 with an appropriate capacitor value for
the frequency of operation and leave C6 and C11 open. For frequencies >2.6 GHz, additional dynamic
range can be achieved by driving Pin 15 (INLO). When driving INLO, populate C6 and C11 with an appropriate
capacitor value for the frequency of operation and leave C10 and C12 open.
VTGT. R10 and R11 are set up to provide 1.4 V to VTGT from VREF. If R10 and R11 are removed, an external
voltage can be used. Alternatively, R7 and R11 can be used to form a voltage divider for an external reference.
Power Supply Decoupling. The nominal supply decoupling consists of a 100 pF filter capacitor placed
physically close to the AD8363, a 0 Ω series resistor, and a 0.1 μF capacitor placed close to the power
supply input pin. The 0 Ω resistor can be replaced with a larger resistor to add more filtering; however,
it is at the expense of a voltage drop.
Rev. 0 | Page 30 of 36
Default Value
C6 = open,
C10 = 0.1 μF,
C11 = open
C12 = 0.1 μF
R7 = 0 Ω,
R8 = 0 Ω,
R10 = 845 Ω,
R11 = 1.4 kΩ
C4 = 100 pF,
C5 = 100 pF,
C7 = 0.1μF,
C13 = 0.1μF,
R14 = 0 Ω,
R16 = 0 Ω
AD8363
Component
R1, R2, R6,
R13, R15
C8, C9, R5
C3
R9, R12
R17, R18
Paddle
Function/Notes
Output Interface (Default Configuration) in Measurement Mode. In this mode, a portion of the output
voltage is fed back to the VSET pin via R6. Using the voltage divider created by R2 and R6, the magnitude
of the slope at VOUT is increased by reducing the portion of VOUT that is fed back to VSET. If a fast
responding output is expected, the 0 Ω resistor (R15) can be removed to reduce parasitics on
the output.
Output Interface in Controller Mode. In this mode, R6 must be open and R13 must have a 0 Ω resistor.
In controller mode, the AD8363 can control the gain of an external component. A setpoint voltage is
applied to the VSET pin, the value of which corresponds to the desired RF input signal level applied to
the AD8363. If a fast responding output is expected, the 0 Ω resistor (R15) can be removed to reduce
parasitics on the output.
Low-Pass Filter Capacitors, CLPF. The low-pass filter capacitors reduce the noise on the output and affect the
pulse response time of the AD8363. This capacitor should be as large as possible. The smallest CLPF
capacitance should be 390 pF. R5, when set to a value other than 0 Ω, is used in conjunction with C8 and
C9 to modify the loop transfer function and change the loop dynamics in controller mode.
CHPF Capacitor. The CHPF capacitor introduces a high-pass filter affect into the AD8363 transfer function
and can also affect the response time. The CHPF capacitor should be as small as possible and connect to
VPOS when used. No capacitor is needed for input frequencies greater than 10 MHz.
TCM2/PWDN. The TCM2/PWDN pin controls the amount of nonlinear intercept temperature compensation
and/or shuts down the device. The evaluation board is configured to control this from a test loop, but VREF
can also be used by the voltage divider created by R9 and R12.
TCM1. TCM1 controls the temperature compensation (5 kΩ impedance). The evaluation board is configured to
control this from a test loop, but VREF can also be used by the voltage divider created by R17 and R18.
Due to the relatively low impedance of the TCM1 pin and the limited current of the VREF pin, care should
be taken when choosing the R17 and R18 values.
Connect the paddle to both a thermal and electrical ground.
Rev. 0 | Page 31 of 36
Default Value
R1 = 0 Ω,
R2 = open,
R6 = 0 Ω,
R13 = open,
R15 = 0 Ω
C8 = open,
C9 = 0.1 μF,
R5 = 0 Ω
C3 = open
R9 = open,
R12 = open
R17 = open,
R18 = open
AD8363
07368-060
07368-058
ASSEMBLY DRAWINGS
Figure 72. Evaluation Board Assembly, Top Side
07368-059
07368-061
Figure 70. Evaluation Board Layout, Top Side
Figure 73. Evaluation Board Assembly, Bottom Side
Figure 71. Evaluation Board Layout, Bottom Side
Rev. 0 | Page 32 of 36
AD8363
OUTLINE DIMENSIONS
4.00
BSC SQ
0.60 MAX
0.60 MAX
13
12° MAX
1.00
0.85
0.80
0.65 BSC
TOP
VIEW
12
0.50
0.40
0.30
0.80 MAX
0.65 TYP
(BOTTOM VIEW)
9
8
5
4
0.25 MIN
1.95 BSC
0.05 MAX
0.02 NOM
SEATING
PLANE
2.50
2.35 SQ
2.20
EXPOSED
PAD
3.75
BSC SQ
0.35
0.30
0.25
PIN 1
INDICATOR
1
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
082008-A
PIN 1
INDICATOR
16
Figure 74. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4mm Body, Very Thin Quad
(CP-16-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8363ACPZ-R7 1
AD8363ACPZ-WP1
AD8363-EVALZ1
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 33 of 36
Package Option
CP-16-10
CP-16-10
Ordering Quantity
1,500
64
AD8363
NOTES
Rev. 0 | Page 34 of 36
AD8363
NOTES
Rev. 0 | Page 35 of 36
AD8363
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07368-0-5/09(0)
Rev. 0 | Page 36 of 36