HIGH SPEED 36K (4K X 9) SYNCHRONOUS DUAL-PORT RAM Features ◆ ◆ ◆ ◆ High-speed clock-to-data output times – Commercial: 12/15/20ns (max.) Low-power operation – IDT70914S Active: 850 mW (typ.) Standby: 50 mW (typ.) Architecture based on Dual-Port RAM cells – Allows full simultaneous access from both ports Synchronous operation – 4ns setup to clock, 1ns hold on all control, data, and address inputs ◆ ◆ ◆ ◆ ◆ ◆ IDT70914S – Data input, address, and control registers – Fast 12ns clock to data out – Self-timed write allows fast cycle times – 16ns cycle times, 60MHz operation Clock Enable feature TTL-compatible, single 5V (+ 10%) power supply Guaranteed data output hold times Available in 68-pin PLCC, and 80-pin TQFP Industrial temperature range (-40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram WRITE LOGIC WRITE LOGIC MEMOR MEMORY Y ARRAY ARRAY REGISTER REGISTER I/O0-8L I/O0-8R SENSE SENSE AMPS DECODER DECODER AMPS OEL CLKL CLKENL R/WL REG en REG en REG CEL Selftimed Write Logic OER CLKR CLKENR Selftimed Write Logic A0L-A11L A0R-A11R REG R/WR CER 3490 drw 01 APRIL 2016 1 ©2016 Integrated Device Technology, Inc. DSC-3490/10 IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range Description The IDT70914 is a high-speed 4K x 9 bit synchronous Dual-Port RAM. The memory array is based on Dual-Port memory cells to allow simultaneous access from both ports. Registers on control, data, and address inputs provide low set-up and hold times. The timing latitude provided by this approach allow systems to be designed with very short cycle times. With an input data register, this device has been optimized for applications having unidirectional data flow or bidirectional data flow in bursts. The IDT70914 utilizes a 9-bit wide data path to allow for parity at the user's option. This feature is especially useful in data communication applications where it is necessary to use a parity bit for transmission/ reception error checking. Fabricated using CMOS high-performance technology, these DualPorts typically operate on only 850mW of power at maximum high-speed clock-to-data output times as fast as 12ns. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT70914 is packaged in a 68-pin PLCC, and an 80-pin TQFP. I/O6L I/O7L I/O8L GND CEL N/C N/C R/WL VCC N/C OEL A11L A10L A9L A8L A7L A6L Pin Configurations(1,2,3) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 27 28 8 29 7 30 6 31 5 32 4 33 3 2 34 70914 J68(4) 35 36 1 68 37 67 38 66 39 65 40 64 41 63 42 62 43 61 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I/O6R I/O7R I/O8R GND CER N/C N/C R/WR GND GND N/C OER A11R A10R A9R A8R A7R N/C I/O5L VCC I/O4L I/O3L I/O2L I/O1L I/O0L GND GND I/O0R I/O1R I/O2R I/O3R VCC I/O4R I/O5R NOTES: 1. All VCC pins must be connected to power supply. 2. All ground pins must be connected to ground supply. 3. J68-1 package body is approximately .95 in x .95 in x .17 in. 4. This package code is used to reference the package diagram. 6.42 2 A5L A4L A3L A2L A1L A0L CLKENL CLKL CLKR CLKENR A0R A1R A2R A3R A4R A5R A6R 3490 drw 03 , Comm IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range N/C A7R A8R A9R A10R A11R N/C OER N/C GND GND R/WR N/C N/C CER GND I/O8R I/O7R I/O6R N/C Pin Configuration(1,2,3) (con't.) INDEX 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 39 63 38 64 37 65 36 66 35 67 34 68 33 69 32 70 31 70914 PN80(4) 71 72 30 29 28 73 74 27 75 26 76 25 77 24 78 23 22 79 80 1 2 3 4 5 6 7 8 21 9 10 11 12 13 14 15 16 17 18 19 20 N/C A6L A7L A8L A9L A10L A11L N/C OEL N/C VCC R/WL N/C N/C CEL GND I/O8L I/O7L I/O6L N/C N/C A6R A5R A4R A3R A2R A1R A0R CLKENR CLKR CLKL CLKENL A0L A1L A2L A3L A4L A5L N/C N/C NOTES: 1. All VCC pins must be connected to power supply. 2. All ground pins must be connected to ground supply. 3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 3 6.42 N/C N/C I/O5R I/O4R VCC I/O3R I/O2R I/O1R I/O0R GND GND I/O0L I/O1L I/O2L I/O3L I/O4L VCC I/O5L N/C N/C 3490 drw 04 IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range Absolute Maximum Ratings(1) Symbol (2) V TERM Rating Com'l Only Terminal Voltage with Respect to GND -0.5 to +7.0 V TERM Terminal Voltage -0.5 to V CC V TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -65 to +150 o IOUT DC Output Current (2) Maximum Operating Temperature and Supply Voltage(1,2) Unit Grade V Commercial Ambient Temperature GND VCC 0OC to +70OC 0V 5.0V + 10% 3490 tbl 02 NOTES: 1. This is the parameter TA. This is the "instant on" casae temperature 2. Industrial temperature: for specific speeds, packages and powers contact your C C 50 mA 3490 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Recommended DC Operating Conditions Symbol Capacitance Symbol CIN COUT VCC Supply Voltage GND Ground VIH Input High Voltage VIL (TA = +25°C, f = 1.0MHz) TQFP Only Parameter Conditions Max. Unit VIN = 3dV 8 pF VOUT = 3dV 9 pF Input Capacitance Output Capacitance Parameter Input Low Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ (1) -0.5 ____ (2) 6.0 0.8 V V 3490 tbl 03 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed VCC + 10%. 3490 tbl 04 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 70914S Symbol Parameter Min. Max. Unit VCC = 5.5V, VIN = 0V to V CC ___ 10 µA Output Leakage Current CE = VIH, VOUT = 0V to V CC ___ 10 µA VOL Output Low Voltage IOL = +4mA ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ V |ILI| (1) Input Leakage Current |ILO| Test Conditions 3490 tbl 05 NOTE: 1. At VCC < 2.0V, input leakages are undefined 6.42 4 Comm IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) (VCC = 5V ± 10%) 70914S12 Com'l Only Symbol Parameter Test Condition Version 70914S15 Com'l Only Typ.(2) Max. Typ.(2) Max. Unit ICC Dynamic Operating Current (Both Ports Active) CEL and CER = V IL, Outputs Disabled f = fMAX(1) COM'L 190 310 180 300 mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL and CER = V IH f = fMAX(1) COM'L 95 150 90 140 mA ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = V IL and CE"B" = V IH(3) Active Port Outputs Disabled, f=fMAX(1) COM'L 170 220 160 210 mA Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CER and CEL > V CC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V, f = 0(2) COM'L 10 15 10 15 mA Full Standby Current (One Port - All CMOS Level Inputs) CE"A" < 0.2V and CE"B" > V CC - 0.2V (3) V IN > V CC - 0.2V or V IN < 0.2V, Active Port Outputs Disabled f = fMAX(1) COM'L 165 210 155 200 mA ISB3 ISB4 3490 tbl 06a 70914S20 Com'l Only Symbol Parameter Test Condition Version Typ.(2) Max. Unit ICC Dynamic Operating Current (Both Ports Active) CEL and CER = V IL, Outputs Disabled f = fMAX(1) COM'L 170 290 mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL and CER = V IH f = fMAX(1) COM'L 85 130 mA ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = V IL and CE"B" = V IH(3) Active Port Outputs Disabled, f=fMAX(1) COM'L 150 200 mA Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CER and CEL > V CC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V, f = 0(2) COM'L 10 15 mA Full Standby Current (One Port - All CMOS Level Inputs) CE"A" < 0.2V and CE"B" > V CC - 0.2V (3) V IN > V CC - 0.2V or V IN < 0.2V, Active Port Outputs Disabled f = fMAX(1) COM'L 145 190 mA ISB3 ISB4 3490 tbl 06b NOTES: 1. At fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC = 150mA (Typ) 5. Industrial temperature: for specific speeds, packages and powers contact your sales office. 5 6.42 IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1,2 and 3 3490 tbl 07 5V 5V 893Ω 893Ω DATAOUT DATAOUT 30pF 347Ω 5pF* 347Ω 3490 drw 05 3490 drw 06 Figure 1. AC Output Test load. 8 7 Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig. 9pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 6 ∆tCD (Typical, ns) 5 4 3 2 1 0 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 3490 drw 07 Figure 3. Typical Output Derating (Lumped Capacitive Load). 6.42 6 , Comm IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C) 70914S12 Com'l Only Symbol Parameter 70914S15 Com'l Only Min. Max. Min. Max. Unit ns tCYC Clock Cycle Time 16 ____ 20 ____ tCH Clock High Time 6 ____ 6 ____ ns tCL Clock Low Time 6 ____ 6 ____ ns tCD Clock High to Output Valid ____ 12 ____ 15 ns tS Registered Signal Set-up Time 4 ____ 4 ____ ns tH Registered Signal Hold Time 1 ____ 1 ____ ns tDC ns Data Output Hold After Clock High 3 ____ 3 ____ tCKLZ Clock High to Output Low-Z(1,2) 2 ____ 2 ____ ns tCKHZ (1,2) Clock High to Output High-Z ____ 7 ____ 7 ns tOE Output Enable to Output Valid ____ 7 ____ 8 ns tOLZ Output Enable to Output Low-Z(1,2) 0 ____ 0 ____ ns ____ 7 ____ 7 ns ns (1,2) tOHZ Output Disable to Output High-Z tSCK Clock Enable, Disable Set-up Time 4 ____ 4 ____ tHCK Clock Enable, Disable Hold Time 2 ____ 2 ____ ns ns Port-to-Port Delay tCWDD Write Port Clock High to Read Data Delay ____ 25 ____ 30 tCSS Clock-to-Clock Setup Time ____ 13 ____ 15 ns 3490 tbl 08a 70914S20 Com'l Only Symbol Min. Max. Unit tCYC Clock Cycle Time Parameter 20 ____ ns tCH Clock High Time 8 ____ ns tCL Clock Low Time 8 ____ ns tCD Clock High to Output Valid ____ 20 ns tS Registered Signal Set-up Time 5 ____ ns tH Registered Signal Hold Time 1 ____ ns tDC Data Output Hold After Clock High 3 ____ ns ns (1,2) tCKLZ Clock High to Output Low-Z 2 ____ tCKHZ Clock High to Output High-Z(1,2) ____ 9 ns tOE Output Enable to Output Valid ____ 10 ns 0 ____ ns ____ tOLZ Output Enable to Output Low-Z (1,2) (1,2) tOHZ Output Disable to Output High-Z 9 ns tSCK Clock Enable, Disable Set-up Time 5 ____ ns tHCK Clock Enable, Disable Hold Time 2 ____ ns Write Port Clock High to Read Data Delay ____ 35 ns Clock-to-Clock Setup Time ____ 15 ns Port-to-Port Delay tCWDD tCSS NOTES: 1. Transition is measured 0mV from Low or High impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. Industrial temperature: for specific speeds, packages and powers contact your sales office. 7 6.42 3490 tbl 08b IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range Timing Waveform of Read Cycle, Either Side tCYC tCH CLK tCL tSCK tSCK tHCK CLKEN tS tH CE R/W ADDRESS An An + 1 An + 3 tCKHZ (1) tDC tCD DATAOUT An + 2 Qn tCKLZ (1) Qn + 1 tOHZ Qn + 1 (1) tOLZ (1) tOE OE 3490 drw 08 Timing Waveform of Write with Port-to-Port Read(2,3,4) CLK "A" R/W "A" ADDR "A" DATA IN "A" NO MATCH MATCH VALID tCCS (5) CLK "B" tCD R/W "B" ADDR "B" NO MATCH MATCH tCWDD tCD DATA OUT "B" VALID VALID tDC 3490 drw 09 NOTES: 1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. CEL = CER = VIL, CLKENL = CLKENR = VIL. 3. OE = VIL for the reading port, port 'B'. 4. All timing is the same for left and right ports. Ports "A" may be either the left or right port. Port "B" is opposite from port "A". 5. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD. tCWDD does not apply in this case. 6.42 8 Comm IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range Timing Waveform of Read-to-Write Cycle No. 1(1,2) (tCYC = min.) tCYC tCH CLK tCYC tCL tCH tCL CLKEN tS tH (1) CE R/W ADDRESS An An + 1 An + 1 (1) An + 2 (1) Dn + 1 DATAIN Dn + 2 tCKHZ (3) tCD DATAOUT Qn tCKLZ (3) 3490 drw 10 Timing Waveform of Read-to-Write Cycle No. 2(4) (tCYC > min.) tCYC (4) tCH CLK tCL CLKEN tS tH CE R/W ADDRESS An An + 1 DATAIN Dn + 1 tCD DATAOUT tCKLZ Qn (3) tOHZ OE 3490 drw 11 NOTES: 1. For tCYC = min.; data out coincident with the rising edge of the subsequent write clock can occur. To ensure writing to the correct address location, the write must be repeated on the second write clock rising edge. If CE = VIL, invalid data will be written into array. The An+1 must be rewritten on the following cycle. 2. OE LOW throughout. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. For tCYC > min.; OE may be used to avoid data out coincident with the rising edge of the subsequent write clock. Use of OE will eliminate the need for the write to be repeated. 9 6.42 IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range Functional Description The IDT70914 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide very short set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. The internal write pulse width is dependent on the LOW to HIGH transitions of the clock signal allowing the shortest possible realized cycle times. Clock enable inputs are provided to stall the operation of the address and data input registers without introducing clock skew for very fast interleaved memory applications. A HIGH on the CE input for one clock cycle will power down the internal circuitry to reduce static power consumption. Truth Table I: Read/Write Control(1) Inputs (3) Outputs Asynchronous Synchronous Mode CLK CE R/W OE I/O0-8 ↑ H X X High-Z Deselected, Power-Down ↑ L L X DATAIN Selected and Write Enabled ↑ L H L DATAOUT ↑ X X H High-Z Read Selected and Data Output Enable Read Outputs Disabled 3490 tbl 09 Truth Table II: Clock Enable Function Table(1) Inputs Register Outputs(4) Register Inputs Mode CLK(3) CLKEN(2) ADDR DATAIN ADDR DATAOUT Load "1" ↑ L H H H H Load "0" ↑ L L L L L Hold (do nothing) ↑ H X X NC NC X H X X NC NC 3490 tbl 10 NOTES: 1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change 2. CLKEN = VIL must be clocked in during Power-Up. 3. Control signals are initiated and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH transition of the CLK. 4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN. 6.42 10 Comm IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range Ordering Information XXXXX A 99 A Device Type Power Speed Package A A A Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank Commercial (0°C to +70°C) G(2) Green J PF 68-pin PLCC (J68) 80-pin TQFP (PN80) 12 15 20 Commercial Only Commercial Only Commercial Only S Standard Power 70914 36K (4K x 9-Bit) Synchronous Dual-Port RAM Speed in nanoseconds 3490 drw 12 NOTES: 1. Industrial temperature range is available on selected TQFP packages in standard power. For specific speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your sales office. Datasheet Document History 3/10/99: 6/7/99: 11/10/99: 5/24/00: 1/12/01: 10/21/08: 05/24/10: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Page 2 and 3 Added additional notes to pin configurations Changed drawing format Replaced IDT logo Page 4 Increased storage temperature parameter Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes Removed PGA pinout (obsolete package) Changed cycle time of 12ns part from 17ns (58MHz) to 16ns (60MHz) Page 11 Removed "IDT" from orderable part number Page 1 Added green parts availability to features Page 11 Added green indicator to ordering information 11 6.42 IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range Datasheet Document History (con't.) 06/05/15: 04/28/16: Pages 1-12 Removed Military and Industrial Temperature Ranges from datasheet header Page 1 Removed Military speed offerings from the Features Page 2 Removed MIL-PRF 38535 QML support information Pages 2 ,3 &11 The package codes J68-1 and PN80-1 changed to J68 and PN80 respectively to match the standard package codes Page 4 Removed the military and industrial offerings in the Absolute Max Ratings & the Max Operating Temp tables Page 5 Removed the military and industrial offerings in the DC Elec Chars tables Page 6 Corrected typo in the Typical Output Derating drawing Page 7 Removed military offering for the 20 & 25 speed grades in the AC Elec Chars table Removed the military temp range information from the AC Elec Chars table title Page 11 Added Tape and Reel to and removed military offering & 25ns speed grade from the Ordering Information Page 2 Changed diagram for the J68 pin configuration by rotating package pin labels and pin numbers 90 degrees clockwise to reflect pin1 orientation and added pin 1 dot at pin 1 Removed all four chamfers from J68 and aligned the top and bottom pin labels in the standard direction Page 3 Changed diagram for the PN80 pin configuration by rotating package pin labels and pin numbers 90 degrees counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1 Added the IDT logo, changed the text to be in alignment with new diagram marking specs for all pin configurations and updated footnote references for the J68 & the PN80 pin configurations Page 11 Removed Industrial temp range information from the Ordering Information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 12 for Tech Support: 408-284-2794 [email protected]