IDT IDT79R3051E-40J Riscontroller Datasheet

IDT79R3051 , 79R3051E
IDT79R3052 , 79R3052E
IDT79R3051/79R3052
RISControllers
Integrated Device Technology, Inc.
FEATURES:
• Instruction set compatible with IDT79R3000A and
IDT79R3001 MIPS RISC CPUs
• High level of integration minimizes system cost, power
consumption
— IDT79R3000A /IDT79R3001 RISC Integer CPU
— R3051 features 4KB of Instruction Cache
— R3052 features 8KB of Instruction Cache
— All devices feature 2kB of Data Cache
— “E” Versions (Extended Architecture) feature full
function Memory Management Unit, including 64entry Translation Lookaside Buffer (TLB)
— 4-deep write buffer eliminates memory write stalls
— 4-deep read buffer supports burst refill from slow
memory devices
Clk2xIn
Clock
Generator
Unit
•
•
•
•
•
•
— On-chip DMA arbiter
— Bus Interface minimizes design complexity
Single clock input with 40%-60% duty cycle
35 MIPS, over 64,000 Dhrystones at 40MHz
Low-cost 84-pin PLCC packaging that's pin-/packagecompatible with thermally enhanced 84-pin MQUAD.
Flexible bus interface allows simple, low-cost designs
20, 25, 33, and 40MHz operation
Complete software support
— Optimizing compilers
— Real-time operating systems
— Monitors/debuggers
— Floating Point Software
— Page Description Languages
BrCond(3:0)
Master Pipeline Control
System Control
Coprocessor
Integer
CPU Core
Exception/Control
Registers
General Registers
(32 x 32)
Memory Management
Registers
ALU
Shifter
Int(5:0)
Mult/Div Unit
Translation
Lookaside Buffer
(64 entries)
Address Adder
PC Control
Virtual Address
32
Physical Address Bus
Instruction
Cache
(8kB/4kB)
32
Data
Cache
(2kB)
Data Bus
Bus Interface Unit
4-deep
Write
Buffer
4-deep
Read
Buffer
Address/
Data
DMA
Arbiter
DMA
Ctrl
BIU
Control
Rd/Wr
Ctrl
SysClk
2874 drw 01
Figure 1. R3051 Family Block Diagram
The IDT logo is a registered trademark, and RISChipset, RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400 and R4600 are trademarks of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1995 Integrated Device Technology, Inc.
SEPTEMBER 1995
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DSC-3000/5
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INTRODUCTION
The IDT IDT79R3051 family is a series of high-performance 32-bit microprocessors featuring a high level of integration which are targeted to high-performance, but costsensitive embedded processing applications. The IDT79R3051
family is designed to bring the high-performance inherent in
the MIPS RISC architecture into low-cost, simplified, powersensitive applications.
Functional units were integrated onto the CPU core in order
to reduce the total system cost, without significantly degrading
system performance. Thus, the IDT79R3051 family is able to
offer 35MIPS of integer performance at 40MHz without requiring external SRAM or caches.
Furthermore, the IDT79R3051 family brings dramatic power
reduction to these embedded applications, allowing the use of
low-cost packaging for devices up to 25 MHz. The IDT79R3051
family allows customer applications to bring maximum performance at minimum cost.
Figure 1 shows a block-level representation of the functional units within the IDT79R3051 family. The IDT79R3051
family could be viewed as the embodiment of a discrete
solution built around the IDT79R3000A or IDT79R3001.
However, by integrating this functionality on a single chip,
dramatic cost and power reductions are achieved.
Currently, there are four members of the IDT79R3051
family. All devices are pin- and software-compatible: the
differences lie in the amount of instruction cache, and in the
memory management capabilities of the processor:
• The IDT79R3052"E” incorporates 8kB of Instruction Cache,
and features a full-function Memory Management Unit
(MMU), including a 64-entry fully-associative Translation
Lookaside Buffer (TLB). This is the same MMU incorporated
into the IDT79R3000A and IDT79R3001.
• The IDT79R3052 also incorporates 8kB of Instruction Cache.
However, the MMU is a much simpler subset of the capabilities of the enhanced versions of the architecture, and in fact
does not use a TLB.
• The IDT79R3051"E” incorporates 4KB of Instruction Cache.
Additionally, this device features the same full-function
MMU (including TLB file) as the IDT79R3052"E”, and
IDT79R3000A.
• The IDT79R3051 incorporates 4KB of Instruction Cache,
and uses the simpler memory management model of the
IDT79R3052.
An overview of the functional blocks incorporated in these
devices follows.
CPU Core
The CPU core is a full 32-bit RISC integer execution
engine, capable of sustaining close-to single cycle execution
rate. The CPU core contains a five stage pipeline and 32
orthogonal 32-bit registers. The IDT79R3051 family implements the MIPS ISA. In fact, the execution engine of the
IDT79R3051 family is the same as the execution engine of the
IDT79R3000A (and IDT79R3001). Thus the IDT79R3051
family is binary-compatible with those CPU engines.
5.3
The execution engine of the IDT79R3051 family uses a
five-stage pipeline to achieve close-to single cycle execution.
A new instruction can be started in every clock cycle; the
execution engine actually processes five instructions concurrently (in various pipeline stages). Figure 2 shows the
concurrency achieved by the IDT79R3051 family pipeline.
I#1
IF
I#2
RD
ALU MEM
WB
IF
RD
ALU MEM
I#3
IF
RD
ALU MEM
I#4
IF
RD
I#5
IF
WB
WB
ALU MEM
RD
WB
ALU MEM
Current
CPU
Cycle
WB
2874 drw 02
Figure 2. R3051 Family 5-Stage Pipeline
System Control Co-Processor
The R3051 family also integrates on-chip the System
Control Co-processor, CP0. CP0 manages both the exception handling capability of the IDT79R3051 family, as well as
the virtual to physical mapping of the IDT79R3051 family.
There are two versions of the IDT79R3051 family architecture: the Extended Architecture Versions (the IDT79R3051E
and IDT79R3052E) contain a fully associative 64-entry TLB
which maps 4KB virtual pages into the physical address
space. The virtual to physical mapping thus includes kernel
segments which are hard mapped to physical addresses, and
kernel and user segments which are mapped on a page basis
by the TLB into anywhere within the 4GB physical address
space. In this TLB, 8-page translations can be “locked” by the
kernel to insure deterministic response in real-time applications. These versions thus use the same MMU structure as
that found in the IDT79R3000A and IDT79R3001. Figure 3
shows the virtual-to-physical address mapping found in the
Extended Architecture versions of the processor family.
The Extended Architecture devices allow the system
designer to implement kernel software to dynamically manage
User task utilization of memory resources, and also allow the
Kernel to effectively “protect” certain resources from user
tasks. These capabilities are important in a number of
embedded applications, from process control (where resource
protection may be extremely important) to X-Window display
systems (where virtual memory management is extremely
important), and can also be used to simplify system debugging.
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VIRTUAL
PHYSICAL
0xffffffff
Kernel Mapped
(kseg2)
Any
0xc0000000
Kernel Uncached
(kseg1)
Physical
Memory
0xa0000000
3548MB
Kernel Cached
(kseg0)
0x80000000
User Mapped
Cacheable
(kuseg)
Any
Memory
512MB
0x00000000
2874 drw 03
Figure 3. Virtual-to-Physical Mapping of Extended Architecture Versions
The base versions of the architecture (the IDT79R3051
and IDT79R3052) remove the TLB and institute a fixed
address mapping for the various segments of the virtual
address space. The base processors support distinct kernel
and user mode operation without requiring page management
software, leading to a simpler software model. The memory
mapping used by these devices is illustrated in Figure 4. Note
that the reserved address spaces shown are for compatibility
with future family members; in the current family members,
references to these addresses are translated in the same
fashion as their respective segments, with no traps or exceptions taken.
When using the base versions of the architecture, the
system designer can implement a distinction between the
user tasks and the kernel tasks, without having to execute
page management software. This distinction can take the
form of physical memory protection, accomplished by address decoding, or in other forms. In systems which do not
wish to implement memory protection, and wish to have the
kernel and user tasks operate out of a single unified memory
space, upper address lines can be ignored by the address
decoder, and thus all references will be seen in the lower
gigabyte of the physical address space.
VIRTUAL
0xffffffff
PHYSICAL
1MB Kernel Rsvd
Kernel Cached
(kseg2)
Kernel Cacheable
Tasks
1024MB
Kernel/User
Cacheable
Tasks
2048MB
Inaccessible
512MB
Kernel Boot
and I/O
512MB
0xc0000000
Kernel Uncached
(kseg1)
0xa0000000
Kernel Cached
(kseg0)
0x80000000
1MB User Rsvd
User
Cached
(kuseg)
0x00000000
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Figure 4. Virtual-to-Physical Mapping of Base Architecture Versions
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of the memory system. The write buffers capture and FIFO
processor address and data information in store operations,
and presents it to the bus interface as write transactions at the
rate the memory system can accommodate.
The IDT79R3051/52 read interface performs both single
word reads and quad word reads. Single word reads work with
a simple handshake, and quad word reads can either utilize
the simple handshake (in lower performance, simple systems) or utilize a tighter timing mode when the memory system
can burst data at the processor clock rate. Thus, the system
designer can choose to utilize page or nibble mode DRAMs
(and possibly use interleaving), if desired, in high-performance systems, or use simpler techniques to reduce complexity.
In order to accommodate slower quad-word reads, the
IDT79R3051 family incorporates a 4-deep read buffer FIFO,
so that the external interface can queue up data within the
processor before releasing it to perform a burst fill of the
internal caches. Depending on the cost vs. performance
tradeoffs appropriate to a given application, the system design
engineer could include true burst support from the DRAM to
provide for high-performance cache miss processing, or utilize the read buffer to process quad word reads from slower
memory systems.
Clock Generation Unit
The IDT79R3051 family is driven from a single input clock,
capable of operating in a range of 40%-60% duty cycle. On
chip, the clock generator unit is responsible for managing the
interaction of the CPU core, caches, and bus interface. The
clock generator unit replaces the external delay line required
in IDT79R3000A and IDT79R3001 based applications.
Instruction Cache
The current family includes two different instruction cache
sizes: the IDT79R3051 family (the IDT79R3051 and
IDT79R3051E) feature 4KB of instruction cache, and the
IDT79R3052 and IDT79R3052E each incorporate 8KB of
Instruction Cache. For all four devices, the instruction cache
is organized as a line size of 16 bytes (four words). This
relatively large cache achieves a hit rate well in excess of 95%
in most applications, and substantially contributes to the
performance inherent in the IDT79R3051 family. The cache is
implemented as a direct mapped cache, and is capable of
caching instructions from anywhere within the 4GB physical
address space. The cache is implemented using physical
addresses (rather than virtual addresses), and thus does not
require flushing on context switch.
Data Cache
SYSTEM USAGE
All four devices incorporate an on-chip data cache of 2KB,
organized as a line size of 4 bytes (one word). This relatively
large data cache achieves hit rates well in excess of 90% in
most applications, and contributes substantially to the performance inherent in the IDT79R3051 family. As with the instruction cache, the data cache is implemented as a direct mapped
physical address cache. The cache is capable of mapping any
word within the 4GB physical address space.
The data cache is implemented as a write through cache,
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance.
The IDT79R3051 family has been specifically designed to
easily connect to low-cost memory systems. Typical low-cost
memory systems utilize slow EPROMs, DRAMs, and application-specific peripherals. These systems may also typically
contain large, slow Static RAMs, although the IDT79R3051
family has been designed to not specifically require the use of
external SRAMs.
Figure 5 shows a typical system block diagram. Transparent latches are used to de-multiplex the IDT79R3051/52
address and data busses from the A/D bus. The data paths
between the memory system elements and the R3051 family
A/D bus is managed by simple octal devices. A small set of
simple PALs can be used to control the various data path
elements, and to control the handshake between the memory
devices and the CPU.
Bus Interface Unit
DEVELOPMENT SUPPORT
The IDT79R3051 family uses its large internal caches to
provide the majority of the bandwidth requirements of the
execution engine, and thus can utilize a simple bus interface
connected to slow memory devices.
The IDT79R3051 family bus interface utilizes a 32-bit
address and data bus multiplexed onto a single set of pins.
The bus interface unit also provides an ALE signal to demultiplex the A/D bus, and simple handshake signals to
process processor read and write requests. In addition to the
read and write interface, the IDT79R3051 family incorporates
a DMA arbiter, to allow an external master to control the
external bus.
The IDT79R3051 family incorporates a 4-deep write buffer
to decouple the speed of the execution engine from the speed
The IDT79R3051 family is supported by a rich set of
development tools, ranging from system simulation tools
through prom monitor support, logic analysis tools, and subsystem modules.
Figure 7 is an overview of the system development process
typically used when developing IDT79R3051 family-based
applications. The IDT79R3051 family is supported by powerful tools through all phases of project development. These
tools allow timely, parallel development of hardware and
software for IDT79R3051/52 based applications, and include
tools such as:
• A program, Cache-3051, which allows the performance of
an IDT79R3051 family based system to be modeled and
understood without requiring actual hardware.
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• Sable, an instruction set simulator.
• Optimizing compilers from MIPS, the acknowledged leader
in optimizing compiler technology.
• IDT Cross development tools, available in a variety of
development environments.
• The IDT Laser Printer System board, which directly drives
a low-cost print engine, and runs Microsoft TrueImage
Page Description Language on top of PeerlessPage Advanced Printer Controller BIOS.
• Adobe PostScript Page Description Language, ported to
the R3000 instruction set, runs on the IDT79R3051 family.
• The IDT Prom Monitor, which implements a full prom
monitor (diagnostics, remote debug support, peek/poke,
etc.).
• An In-Circuit Emulator, developed and sold by Embedded
Performance, Inc.
• The high-performance IDT floating point library software,
which has been integrated into the compiler toolchain to
allow software floating point to replace hardware floating
point without modifying the original source code.
• The IDT Evaluation Board, which includes RAM, EPROM,
I/O, and the IDT Prom Monitor.
Reset
Clk2xIn
Int(5:0)
IDT R3051 Family
RISController
BrCond(3:0)
BusReq
BusGnt
AD(31:0)
Wr
ALE
Addr(3:2)
SysClk Rd
Burst/
RdCEn WrNear
Ack DataEn BErr
Memory and Interface
Control PALs
FCT373T
Address
Decode
PAL
DRAM Control
PALs
I/O Devices/
Peripherals
EPROM
System I/O
DRAM
FCT245T
2874 drw 05
Figure 5. Typical R3051 Family Based System
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Clk2xIn
IDT79R3051 Family
RISController
Address/
Data
Control
R3051 Family
Local Bus
DRAM
Controller
I/O Controller
PROM
I/O
I/O
DRAM
DRAM
IDT73720
Bus Exchanger
(2)
2874 drw 06
Figure 6. R3051 Family Chip Set Based System
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IDT79R3051/79R3052 INTEGRATED RISControllers
System
Architecture
Evaluation
COMMERCIAL TEMPERATURE RANGE
System
Development
Phase
System
Integration
and Verification
Software
Cache-R305x
Benchmarks
Evaluation Board
Laser Printer System
SABLE Simulator
DBG Debugger
PIXIE Profiler
MIPS Compiler Suite
Stand-Alone Libraries
Floating Point Library
Cross Development Tools
Adobe PostScript PDL
MicroSoft TrueImage PDL
Ada
Logic Analysis
Diagnostics
IDT PROM Monitor
Remote Debug
Real-Time OS
In-Circuit Emulator
Hardware
Cache-R305x
Hardware Models
General CAD Tools
RISC Sub-systems
Evaluation Board
Laser Printer System
2874 drw 07
Figure 7. R3051 Family Development Toolchain
5.3
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PERFORMANCE OVERVIEW
THERMAL CONSIDERATIONS
The IDT79R3051 family achieves a very high level of
performance. This performance is based on:
• An efficient execution engine. The CPU performs ALU
operations and store operations at a single cycle rate, and
has an effective load time of 1.3 cycles, and a branch
execution rate of 1.5 cycles (based on the ability of the
compilers to avoid software interlocks). Thus, the execution
engine achieves over 35MIPS performance when operating
out of cache.
The IDT79R3051 family utilizes special packaging techniques to improve the thermal properties of high-speed processors. Thus, all versions of the IDT79R3051 family are
packaged in cavity-down packaging.
The lowest cost members of the family use a standard
cavity-down, injection molded PLCC package (the "J" package). This package, coupled with the power reduction techniques employed in the design of the IDT79R3051 family,
allows operation at speeds to 25MHz. However, at higher
speeds, additional thermal care must be taken.
For this reason, the IDT79R3051 family is also available in
the MQUAD package (the "MJ" package), which is an allaluminum package with the die attached to a normal copper
lead-frame, mounted to the aluminum casing. The MQUAD
allows for more efficient thermal transfer between the die and
the case of the part due to the heat-spreading effect of the
aluminum. The aluminum offers less internal resistance from
one end of the package to the other, which reduces the
temperature gradient across the package, and, therefore,
presents a greater area for convection and conduction to the
PCB for a given temperature. Even nominal amounts of
airflow will dramatically reduce the junction temperature of the
die, resulting in cooler operation. The MQUAD package is
available at all frequencies, and is pin- and form-compatible
with the PLCC package. Thus, designers can choose to utilize
this package without changing their PCB.
The members of the IDT79R3051 family are guaranteed in
a case temperature range of 0°C to +85°C. The type of
package, speed (power) of the device, and airflow conditions
affect the equivalent ambient conditions which meet this
specification.
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(ØCA) of the given package. The following equation relates
ambient and case temperature:
TA = TC - P * ØCA
where P is the maximum power consumption at hot temperature, calculated by using the maximum ICC specification for
the device.
Typical values for ØCA at various airflows are shown in
Table 1 for the various packages.
• Large on-chip caches. The IDT79R3051 family contains
caches which are substantially larger than those on the
majority of today’s embedded microprocessors. These large
caches minimize the number of bus transactions required,
and allow the R3051 family to achieve actual sustained
performance, very close to its peak execution rate.
• Autonomous multiply and divide operations. The
IDT79R3051 family features an on-chip integer multiplier/
divide unit which is separate from the other ALU. This allows
the IDT79R3051 family to perform multiply or divide operations in parallel with other integer operations, using a single
multiply or divide instruction rather than “step” operations.
• Integrated write buffer. The IDT79R3051 family features a
four-deep write buffer, which captures store target addresses and data at the processor execution rate and retires
it to main memory at the slower main memory access rate.
Use of on-chip write buffers eliminates the need for the
processor to stall when performing store operations.
• Burst read support. The IDT79R3051 family enables the
system designer to utilize page mode or nibble mode RAMs
when performing read operations to minimize the main
memory read penalty and increase the effective cache hit
rates.
These techniques combine to allow the processor to achieve
35MIPS integer performance, and over 64,000 dhrystones at
40MHz without the use of external caches or zero wait-state
memory devices.
SELECTABLE FEATURES
The IDT79R3051 family allows the system designer to
configure some aspects of operation. These aspects are
established when the device is reset and include:
• Big Endian vs. Little Endian operation: The part can be
configured to operate with either byte ordering convention,
and in fact may also be dynamically switched between the
two conventions. This facilitates the porting of applications
from other processor architectures, and also permits intercommunications between various types of processors and
databases.
• Data cache refill of one or four words: The memory
system must be capable of performing 4-word transfers to
satisfy cache misses. This option allows the system designer to choose between one- and four-word refill on data
cache misses, depending on the performance each option
brings to his application.
Airflow (ft/min)
ØCA
0
200
400
600
800
1000
"J" Package
29
26
21
18
16
15
"MJ" Package*
22
14
12
11
9
8
2874 tbl 01
Table 1. Thermal Resistance (ØCA) at Various Airflows
(*estimated: final values tbd)
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PIN DESCRIPTION
PIN NAME
I/O
A/D(31:0)
I/O
DESCRIPTION
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction
in one phase, and which is used to transmit data between the CPU and external memory resources during
the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:
Address(31:4):
BE(3:0):
The high-order address for the transfer is presented on A/D(31:4).
These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are represented on A/D(3:0).
During write cycles, the bus contains the data to be stored and is driven from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in either a single data transaction
or in a burst of four words, and places it into the on-chip read buffer.
Addr(3:2)
O
Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the processor.
Specifically, this two bit bus presents either the address bits for the single word to be transferred (writes
or single datum reads) or functions as a two bit counter starting at ‘00’ for burst read operations.
Diag(1)
O
Diagnostic Pin 1. This output indicates whether the current bus read transaction is due to an onchip cache miss, and also presents part of the miss address. The value output on this pin is time
multiplexed:
Diag(0)
O
Cached:
During the phase in which the A/D bus presents address information, this
pin is an active high output which indicates whether the current read is
a result of a cache miss. The value of this pin at this time in other than
read cycles is undefined.
Miss Address (3):
During the remainder of the read operation, this output presents address
bit (3) of the address the processor was attempting to reference when the
cache miss occurred. Regardless of whether a cache miss is being
processed, this pin reports the transfer address during this time.
Diagnostic Pin 0. This output distinguishes cache misses due to instruction references from those due
to data references, and presents the remaining bit of the miss address. The value output on this pin is
also time multiplexed:
I/D:
Miss Address (2):
If the “Cached” Pin indicates a cache miss, then a high on this pin at this
time indicates an instruction reference, and a low indicates a data
reference. If the read is not due to a cache miss but rather an uncached
reference, then this pin is undefined during this phase.
During the remainder of the read operation, this output presents address
bit (2) of the address the processor was attempting to reference when the
cache miss occurred. Regardless of whether a cache miss is being
processed, this pin reports the transfer address during this time.
ALE
O
Address Latch Enable: Used to indicate that the A/D bus contains valid address information for the bus
transaction. This signal is used by external logic to capture the address for the transfer, typically using
transparent latches.
DataEn
O
External Data Enable: This signal indicates that the A/D bus is no longer being driven by the processor
during read cycles, and thus the external memory system may enable the drivers of the memory system
onto this bus without having a bus conflict occur. During write cycles, or when no bus transaction is
occurring, this signal is negated, thus disabling the external memory drivers.
2874 tbl 02
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PIN DESCRIPTION (Continued):
PIN NAME
Burst/
WrNear
I/O
O
DESCRIPTION
Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current bus read
is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles
due to cache misses; it is asserted for all I-Cache miss read cycles, and for D-Cache miss read cycles
if selected at device reset time.
On write transactions, the WrNear output tells the external memory system that the bus interface unit
is performing back-to-back write transactions to an address within the same 256 word page as the prior
write transaction. This signal is useful in memory systems which employ page mode or static column
DRAMs, and allows near writes to be retired quickly.
Rd
Wr
Ack
O
Read: An output which indicates that the current bus transaction is a read.
O
Write: An output which indicates that the current bus transaction is a write.
I
Acknowledge: An input which indicates to the device that the memory system has sufficiently
processed the bus transaction, and that the CPU may either terminate the write cycle or process the read
data from this read transfer.
RdCEn
I
Read Buffer Clock Enable: An input which indicates to the device that the memory system has placed
valid data on the A/D bus, and that the processor may move the data into the on-chip Read Buffer.
SysClk
O
System Reference Clock: An output from the CPU which reflects the timing of the internal processor
"Sys" clock. This clock is used to control state transitions in the read buffer, write buffer, memory
controller, and bus interface unit.
BusReq
I
DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus interface
signals so that they may be driven by an external master.
BusGnt
O
SBrCond(3:2)
BrCond(1:0)
DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has been
detected, and that the bus is relinquished to the external master.
I
Branch Condition Port: These external signals are internally connected to the CPU signals
CpCond(3:0). These signals can be used by the branch on co-processor condition instructions as input
ports. There are two types of Branch Condition inputs: the SBrCond inputs have special internal logic
to synchronize the inputs, and thus may be driven by asynchronous agents. The direct Branch Condition
inputs must be driven synchronously.
BErr
I
Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error.
This signal is only sampled during read and write operations. If the bus transaction is a read operation,
then the CPU will take a bus error exception.
Int(5:3)
SInt(2:0)
I
Processor Interrupt: During normal operation, these signals are logically the same as the Int(5:0)
signals of the R3000. During processor reset, these signals perform mode initialization of the CPU, but
in a different (simpler) fashion than the interrupt signals of the R3000.
There are two types of interrupt inputs: the SInt inputs are internally synchronized by the processor, and
may be driven by an asynchronous external agent. The direct interrupt inputs are not internally
synchronized, and thus must be externally synchronized to the CPU. The direct interrupt inputs have
one cycle lower latency than the synchronized interrupts.
Clk2xIn
I
Master Clock Input: This is a double frequency input used to control the timing of the CPU.
Reset
I
Master Processor Reset: This signal initializes the CPU. Mode selection is performed during the last
cycle of Reset.
Rsvd(4:0)
I/O
Reserved: These five signal pins are reserved for testing and for future revisions of this device. Users
must not connect these pins.
2874 tbl 03
5.3
10
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1, 3)
Symbol
VTERM
TC
TBIAS
TSTG
VIN
Rating
Terminal Voltage
with Respect
to GND
Operating Case
Temperature
Temperature
Under Bias
Storage
Temperature
Input Voltage
Commercial
–0.5 to +7.0
Unit
V
0 to +85
°C
–55 to +125
°C
–55 to +125
°C
–0.5 to +7.0
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Temperature
0°C to +85°C
(Case)
GND
0V
VCC
5.0 ±5%
2874 tbl 06
OUTPUT LOADING FOR AC TESTING
+4mA
NOTES:
2874 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VIN minimum = –3.0V for pulse width less than 15ns.
VIN should not exceed VCC +0.5V.
3. Not more than one output should be shorted at a time. Duration of the short
should not exceed 30 seconds.
VREF
+1.5V
To Device
Under Test
–
+
25pF
–4mA
2874 drw 08
AC TEST CONDITIONS
Symbol
Parameter
Min.
Max.
Unit
VIH
Input HIGH Voltage
3.0
—
V
VIL
Input LOW Voltage
—
0
V
VIHS
Input HIGH Voltage
3.5
—
V
VILS
Input LOW Voltage
—
0
V
2874 tbl 05
DC ELECTRICAL CHARACTERISTICS (TC = 0°C to +85°C, VCC = +5.0V ±5%)
20MHz
25MHz
33.33MHz
40MHz
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Min.
VOH
Output HIGH Voltage
VCC = Min., IOH = –4mA
3.5
—
3.5
—
3.5
—
3.5
—
V
VOL
Output LOW Voltage
VCC = Min., IOL = 4mA
—
0.4
—
0.4
—
0.4
—
0.4
V
VIH
VIL
VIHS
VILS
CIN
Max. Unit
Input HIGH
Voltage(3)
—
2.0
—
2.0
—
2.0
—
2.0
—
V
Input LOW
Voltage(1)
—
—
0.8
—
0.8
—
0.8
—
0.8
V
Input HIGH
Voltage(2,3)
—
3.0
—
3.0
—
3.0
—
3.0
—
V
Input LOW
Voltage(1,2)
—
—
0.4
—
0.4
—
0.4
—
0.4
V
—
—
10
—
10
—
10
—
10
pF
—
—
10
—
10
—
10
—
10
pF
Input
Capacitance(4)
Capacitance(4)
COUT
Output
ICC
Operating Current
VCC = 5V, TC = 25°C
—
350
—
400
—
450
—
500
mA
IIH
Input HIGH Leakage
VIH = VCC
—
100
—
100
—
100
—
100
µA
IIL
Input LOW Leakage
VIL = GND
–100
—
–100
—
–100
—
–100
—
µA
IOZ
Output Tri-state Leakage
VOH = 2.4V, VOL = 0.5V
–100
100
–100
100
–100
100
–100
100
µA
NOTES:
1. VIL Min. = –3.0V for pulse width less than 15ns. VIL should not fall below –0.5V for larger periods.
2. VIHS and VILS apply to CIk2xIn and Reset.
3. VIH should not be held above VCC + 0.5V.
4. Guaranteed by design.
5.3
2874 tbl 07
11
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(1, 2, 3)
(TC = 0°C to +85°C, VCC = +5.0V ±5%)
20MHz
Symbol
t1
t1a
t2
t2a
Signals
BusReq, Ack, BusError,
RdCEn,
A/D
BusReq, Ack, BusError,
RdCEn,
A/D
Description
25MHz
33.33MHz
40MHz
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Set-up to SysClk rising
6
—
5
—
4
—
3
—
ns
Set-up to SysClk falling
7
—
6
—
5
—
4.5
—
ns
Hold from SysClk rising
4
—
4
—
3
—
3
—
ns
Hold from SysClk falling
2
—
2
—
1
—
1
—
Tri-state from SysClk rising
—
10
—
10
—
10
—
10
ns
Driven from SysClk falling
—
10
—
10
—
10
—
10
ns
Asserted from SysClk rising
—
8
—
7
—
6
—
5
ns
—
8
—
7
—
6
—
5
ns
—
5
—
5
—
4
—
3.5
ns
—
4
—
4
—
3
—
3
ns
t7
A/D, Addr, Diag, ALE, Wr
Burst/WrNear, Rd, DataEn
A/D, Addr, Diag, ALE, Wr
Burst/WrNear, Rd, DataEn
BusGnt
BusGnt
Wr, Rd, Burst/WrNear, A/D
t8
ALE
t9
ALE
Negated from SysClk falling
—
4
—
4
—
3
—
3
ns
t10
A/D
Hold from ALE negated
2
—
2
—
1.5
—
1.5
—
ns
Asserted from SysClk falling
—
15
—
15
—
13
—
12
ns
t12
DataEn
DataEn
0
—
0
—
0
—
0
—
ns
t14
A/D
0
—
0
—
0
—
0
—
ns
t15
Wr, Rd, DataEn, Burst/WrNear
—
7
—
6
—
5
—
4
ns
t16
Addr(3:2)
—
6
—
6
—
5
—
4.5
ns
t17
Diag
—
12
—
11
—
10
—
9
ns
t18
A/D
Tri-state from SysClk falling
—
10
—
10
—
9
—
8
ns
t3
t4
t5
t6
t11
Negated from SysClk falling
Valid from SysClk rising
Asserted from SysClk rising
Asserted from A/D
tri-state(4)
Driven from SysClk rising(4)
Negated from SysClk falling
Valid from SysClk
Valid from SysClk
t19
A/D
SysClk falling to data out
—
12
—
11
—
10
—
9
ns
t20
Clk2xIn
Pulse Width HIGH
10
—
8
—
6.5
—
5.6
—
ns
t21
Clk2xIn
Pulse Width LOW
10
—
8
—
6.5
—
5.6
—
ns
t22
Clk2xIn
t33
Reset
Reset
Reset
Int
Int
SInt, SBrCond
SInt, SBrCond
Int, BrCond
Int, BrCond
SysClk
SysClk
SysClk
tderate
All outputs
t23
t24
t25
t26
t27
t28
t29
t30
t31
tsys
t32
Clock Period
25
250
20
250
15
250
12.5
250
ns
Pulse Width from Vcc valid
200
—
200
—
200
—
200
—
µs
Minimum Pulse Width
32
—
32
—
32
—
32
—
tsys
Set-up to SysClk falling
Mode set-up to Reset rising
Mode hold from Reset rising
Set-up to SysClk falling
Hold from SysClk falling
Set-up to SysClk falling
Hold from SysClk falling
Pulse Width
6
—
5
—
4
—
3
—
ns
6
—
5
—
4
—
3
—
ns
2.5
—
2.5
—
2.5
—
2.5
—
ns
6
—
5
—
4
—
3
—
ns
3
—
3
—
2
—
2
—
ns
6
—
5
—
4
—
3
—
ns
ns
3
—
3
—
2
—
2
—
2*t22
2*t22
2*t22
2*t22
2*t22
2*t22
2*t22
2*t22
Clock HIGH Time
t22 – 2 t22 + 2 t22 – 2 t22 + 2 t22 – 1 t22 + 1 t22 – 1 t22 + 1
Clock LOW Time
t22 – 2 t22 + 2 t22 – 2 t22 + 2 t22 – 1 t22 + 1 t22 – 1 t22 + 1
Timing deration for loading
over 25pf(4, 5)
—
0.5
—
0.5
—
0.5
—
0.5
ns
ns
ns/
25pF
NOTES:
2874 tbl 08
1. All timings referenced to 1.5V, with a rise and fall time of less than 2.5ns.
2. All outputs tested with 25pF loading.
3. The AC values listed here reference timing diagrams contained in the R3051 Family Hardware User's Manual.
4. Guaranteed by design.
5. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
5.3
12
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
VSS
A/D(15)
A/D(16)
A/D(17)
A/D(18)
A/D(19)
A/D(20)
VSS
84
VCC
A/D(22)
1
A/D(21)
A/D(23)
A/D(24)
A/D(25)
A/D(26)
VCC
VSS
A/D(27)
A/D(28)
A/D(29)
A/D(30)
A/D(31)
PIN CONFIGURATIONS
75
12
VSS
VCC
VCC
Clk2xIn
A/D(14)
Rsvd(4)
A/D(13)
Rsvd(3)
A/D(12)
Rsvd(2)
A/D(11)
Rsvd(1)
A/D(10)
Rsvd(0)
A/D(9)
Int(5)
VCC
VSS
VSS
VCC
A/D(8)
Int(4)
A/D(7)
Int(3)
SInt(2)
A/D(6)
A/D(5)
SInt(1)
SInt(0)
A/D(4)
A/D(3)
SBrCond(3)
VSS
SBrCond(2)
VCC
BrCond(1)
A/D(2)
VSS
A/D(1)
54
VCC
A/D(0)
Burst/WrNear
Addr(3)
Addr(2)
VCC
VSS
Diag(1)
Diag(0)
ALE
DataEn
Wr
Rd
VCC
VSS
BusGnt
SysClk
Reset
BusError
BusReq
RdCEn
ACK
BrCond(0)
33
2874 drw 09
84-Pin PLCC/MQUAD
Top View
NOTE:
Reserved Pins must not be connected.
5.3
13
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
t22
Clk2xIn
SysClk
t20
t21
t32
t33
2874 drw 11
tsys
Figure 8. R3051 Family Clocking
VCC
ClkIn
Reset
t23
2874 drw 12
Figure 9. Power-On Reset Sequence
SysClk
Reset
t24
2874 drw 13
Figure 10. Warm Reset Sequence
SysClk
Reset
t25
SInt(n),
Int(n)
t26
t27
2874 drw 14
Figure 11. Mode Selection and Negation of Reset
5.3
14
IDT79R3051/79R3052 INTEGRATED RISControllers
Run/
Fixup/
Stall
Stall
COMMERCIAL TEMPERATURE RANGE
Stall
Stall
Stall
Stall
Fixup
PhiClk
SysClk
t7
t15
Rd
t14
t18
A/D(31:0)
t16
t14
t1a
Addr
BE
Data Input
t2a
t10
Addr(3:2)
Word Address
t8
ALE
t9
t12
DataEn
t15
t11
t7
Burst
t1
RdCEn
t2
ACK
t17
t17
Diag(1)
Cached?
Miss Address(3)
Diag(0)
I/D
Miss Address(2)
Start
Read
Turn
Bus
ACK?
ACK?
ACK/
RdCen
Sample
Data
End
Read
2874 drw 15
Figure 12. Single Datum Read in R3051 Family
5.3
15
IDT79R3051/79R3052 INTEGRATED RISControllers
Run/
Fixup/
Stall
Stall
COMMERCIAL TEMPERATURE RANGE
Stall
Stall
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Word 0
Word 1
Word 2
Word 3
PhiClk
SysClk
t7
t15
Rd
t14
t18
t1a
Addr
BE
A/D(31:0)
t16
t1a
Word 0
Word 1
t2a
t10
t16
t9
t8
Word 3
t2a
'01'
t2a
'10'
t16
t14
t1a
Word 2
t2a
'00'
Addr(3:2)
t1a
'11'
t16
ALE
t12
DataEn
t15
t11
t7
Burst
t1
t1
t1
RdCEn
t2
t2
t1
t2
t2
ACK
t17
t17
Diag(1)
Cached?
Miss Address(3)
Diag(0)
I/D
Miss Address(2)
Start
Read
Turn
Bus
ACK/ Sample RdCEn Sample RdCEn Sample RdCEn Sample
New
Data
Data
Data Transaction
RdCen Data
2874 drw 16
Figure 13. R3051 Family Burst Read
5.3
16
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
Stall
Stall
Stall
Stall
PhiClk
SysClk
Rd
t1a
t1a
Word 0
A/D(31:0)
Word 1
t2a
Addr(3:2)
t2a
'00'
'01'
'10'
t16
t16
ALE
DataEn
Burst
t1
t1
t1
RdCEn
t2
t2
t2
ACK
RdCEn
Sample
Data
RdCEn
Sample
Data
RdCEn
Sample
Data
2874 drw 17
Figure 14 (a). Start of Throttled Quad Read
5.3
17
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
Stall
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Word 0
Word 1
Word 2
Word 3
PhiClk
SysClk
t15
Rd
t1a
Word 2
A/D(31:0)
Word 3
t2a
t2a
'01'
Addr(3:2)
t14
t1a
'11'
t16
ALE
t15
DataEn
Burst
t1
t1
t1
RdCEn
t2
t2
t1
t2
ACK
t2
ACK
RdCEn
Sample
Data
RdCEn
Sample
Data
New
Transaction
2874 drw 18
Figure 14 (b). End of Throttled Quad Read
5.3
18
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
SysClk
t7
t15
Wr
t14
t19
t14
Addr
BE
A/D(31:0)
t16
Data
Out
t10
Word Address
Addr(3:2)
t8
ALE
t9
t7
t15
WrNear
t2
ACK
Start
Write
Data
Out
ACK
ACK
t1
ACK
Negate
Wr
New
Transfer
2874 drw 19
Figure 15. R3051 Family Write Cycle
SysClk
t2
BusReq
t1
t5
BusGnt
t3
A/D(31:0)
Addr(3:2)
Diag(1:0)
Rd
Wr
ALE
Burst/
WrNear
2874 drw 20
Figure 16. Request and Relinquish of R3051 Family Bus to External Master
5.3
19
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
SysClk
BusReq
t2
t1
BusGnt
t6
t4
A/D(31:0)
Addr(3:2)
Diag(1:0)
Rd
Wr
ALE
Burst/
WrNear
2874 drw 21
Figure 17. R3051 Family Regaining Bus Mastership
5.3
20
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
Run Cycle
Exception Vector
Phi
SysClk
SInt(n)
t 28
t 29
2874 drw 22
Figure 18. Synchronized Interrupt Input Timing
Run Cycle
Exception Vector
Phi
SysClk
Int(n)
t 30
2874 drw 23
t 31
Figure 19. Direct Interrupt Input Timing
Run Cycle
Capture BrCond
BCzT/F Instruction
Phi
SysClk
SBrCond(n)
t 28
t 29
2874 drw 24
Figure 20. Synchronized Branch Condition Input Timing
Run Cycle
Capture BrCond
BCzT/F Instruction
Phi
SysClk
BrCond(n)
t 30
t 31
2874 drw 25
Figure 21. Direct Branch Condition Input Timing
5.3
21
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
84 LEAD PLCC/MQUAD(7) (SQUARE)
A
D
D1
A1
PIN 1
45° x .045
C
D3/E3
E1
E
D2/E2
b1
B
e
C1
SEATING PLANE
2874 drw 27
NOTES:
1. All dimensions are in inches, unless otherwise noted.
2. BSC—Basic lead Spacing between Centers.
3. D & E do not include mold flash or protutions.
4. Formed leads shall be planar with respect to one another and within .004” at the seating plane.
5. ND & NE represent the number of leads in the D & E directions respectively.
6. D1 & E1 should be measured from the bottom of the package.
7. MQUAD is pin & form compatible with PLCC.
DWG #
J84-1
MJ84-1
# of Leads
84
84
Symbol
Min.
Max.
Min.
Max.
A
165
.180
165
.180
A1
.095
.115
.094
.114
B
.026
.032
.026
.032
b1
.013
.021
.013
.021
C
.020
.040
.020
.040
C1
.008
.012
.008
.012
D
1.185
1.195
1.185
1.195
D1
1.150
1.156
1.140
1.150
D2/E2
1.090
1.130
1.090
1.130
D3/E3
1.000 REF
1.000 REF
E
1.185
1.195
1.185
1.195
E1
1.150
1.156
1.140
1.150
e
.050 BSC
.050 BSC
ND/NE
21
21
5.3
22
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXXXX
-
XX
X
X
IDT
Device Type
Speed Package
Process/
Temp. Range
Blank
Commercial Temperature Range
'J'
'MJ'
84-Pin PLCC
84-Pin MQUAD
'20'
'25'
'33'
'40'
20.0 MHz
25.0 MHz
33.33 MHz
40.0 MHz
79R3051
79R3051E
79R3052
79R3052E
4kB Instruction Cache, No TLB
4kB Instruction Cache, With TLB
8kB Instruction Cache, No TLB
8kB Instruction Cache, With TLB
2874 drw 28
VALID COMBINATIONS
IDT 79R3051 - 20, 25
79R3051E - 20, 25
79R3052 - 20, 25
79R3052E - 20, 25
79R3051 - 33, 40
79R3051E - 33, 40
79R3052 - 33, 40
79R3052E - 33, 40
J Packages Only
J Packages Only
J Packages Only
J Packages Only
MJ Packages Only
MJ Packages Only
MJ Packages Only
MJ Packages Only
5.3
23