LINER LT3746 32-channel 20ma led driver with buck controller Datasheet

LT3746
32-Channel 20mA LED
Driver with Buck Controller
Features
n
n
n
n
n
n
n
n
Description
6V to 55V Power Input Voltage Range
32 Independent LED Outputs up to 30mA/13V
6-Bit Dot Correction Current Adjustment
12-Bit Grayscale PWM Dimming
0.5µs Minimum LED On Time
Adaptive LED Bus Voltage for High Efficiency
Cascadable 30MHz Serial Data Interface
Full Diagnostic and Protection: Individual Open/Short
LED and Overtemperature Fault
Applications
n
n
n
Large Screen Display LED Backlighting
Mono-, Multi-, Full-Color LED Displays
LED Billboards and Signboards
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
The LT®3746 integrates a 32-channel LED driver with a 55V
buck controller. The LED driver lights up to 30mA/13V of
LEDs in series per channel, and the buck controller generates an adaptive bus voltage supplying the parallel LED
strings. Each channel has individual 6-bit dot correction
current adjustment and 12-bit grayscale PWM dimming.
Both dot correction and grayscale are accessible via a
serial data interface in TTL/CMOS logic.
The LT3746 performs full diagnostic and protection
against open/short LED and overtemperature fault. The
fault status is sent back through the serial data interface.
The 30MHz fully-buffered, skew-balanced, cascadable
serial data interface makes the chip extremely suitable
for large screen LCD dynamic backlighting and mono-,
multi-, full-color LED displays.
Typical Application
32-Channel LED Driver, 1MHz Buck, 3 LEDs 10mA to 30mA per Channel, 500Hz 12-Bit Dimming
VIN
13V TO 42V
0.47µF
VIN
EN
VCC
3V TO 5.5V
EN/UVLO
22µH
100k
VCC
10µF
SS
GND
LT3746
10nF
2.048MHz CLOCK
10k
ISN
FB
ISET
60.4k
ISP
C1
2 × 47µF
.
..
RT
33mΩ
80.6k
SYNC
46.4k
4.7µF
CAP
GATE
TSET
32.4k
LED00
LED01
LED02
PWMCK
..
.
LED29
LED30
LED31
TTL/CMOS
SCKI
SCKO
SDI
SDO
LDI
LDO
TTL/CMOS
3746 TA01
3746fa
For more information www.linear.com/3746
1
LT3746
Absolute Maximum Ratings
Pin Configuration
(Note 1)
RT
SS
FB
ISN
ISP
CAP
GATE
VIN
TSET
TOP VIEW
ISET
VIN ........................................................................... 57V
CAP.......................................................... VIN – 8V to VIN
GATE...............................................................CAP to VIN
LED00 to LED31, ISP, ISN.......................................... 13V
ISP..................................................ISN – 1V to ISN + 1V
FB, RT, TSET, ISET........................................................ 2V
VCC................................................................–0.3V to 6V
SCKI, SCKO, SDI, SDO, LDI, LDO, PWMCK, SYNC,
SS, EN/UVLO.............................................. –0.3V to VCC
Operating Junction Temperature Range
(Notes 2, 3).............................................–40°C to 125°C
Storage Temperature Range...................–65°C to 125°C
56 55 54 53 52 51 50 49 48 47
EN/UVLO 1
46 SYNC
LED15 2
45 LED16
LED14 3
44 LED17
LED13 4
43 LED18
LED12 5
42 LED19
LED11 6
41 LED20
LED10 7
40 LED21
LED09 8
39 LED22
LED08 9
38 LED23
57
GND
LED07 10
37 LED24
LED06 11
36 LED25
LED05 12
35 LED26
LED04 13
34 LED27
LED03 14
33 LED28
LED02 15
32 LED29
LED01 16
31 LED30
LED00 17
30 LED31
GND 18
29 GND
SCKO
GND
SDO
LDO
PWMCK
VCC
LDI
SDI
GND
SCKI
19 20 21 22 23 24 25 26 27 28
UHH PACKAGE
56-LEAD (5mm × 9mm) PLASTIC QFN
TJMAX = 125°C, θJA = 32°C/W, θJC = 2.0°C/W
EXPOSED PAD (PIN 57) IS GND, MUST BE SOLDERED TO PCB
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3746EUHH#PBF
LT3746EUHH#TRPBF
3746
56-Lead (5mm × 9mm) Plastic QFN
–40°C to 125°C
LT3746IUHH#PBF
LT3746IUHH#TRPBF
3746
56-Lead (5mm × 9mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
3746fa
For more information www.linear.com/3746
LT3746
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V,
VISP = VISN = 0V, RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supply
VIN
VIN Operating Voltage
IVIN
VIN Supply Current
VCC
VCC Operating Voltage
IVCC
VCC Supply Current (Note 4)
l
6
VEN/UVLO = 0V
No Switching
55
0.2
0.4
l
3
VEN/UVLO = 0V
LED Channel Off, 30MHz Data Off
LED Channel On, 30MHz Data Off
LED Channel On, 30MHz Data On
2
0.55
V
µA
mA
5.5
V
0.1
3.3
10
19
1
4.0
µA
mA
mA
mA
Undervoltage Lockout (UVLO)
IEN/UVLO
VCC UVLO Threshold
VCC Rising
VCC Falling
2.82
2.61
2.89
2.68
2.96
2.75
V
V
EN/UVLO Shutdown Threshold
UVLO Threshold
IVCC <20µA
VEN/UVLO Rising
VEN/UVLO Falling
0.35
1.28
1.19
1.31
1.22
1.34
1.25
V
V
V
EN/UVLO Bias Current
VEN/UVLO = VCC
0.1
1
µA
(VIN – VCAP) UVLO Threshold
(VIN – VCAP) Rising
(VIN – VCAP) Falling
4.6
4.1
4.9
4.4
5.2
4.7
V
V
Soft Start Charge Current
VSS = 1V
–16
–12
–8
µA
Soft Start Discharge Current
VSS = VCC, VEN/UVLO = 1V
Soft Start (SS)
ISS
VSS(TH)
Soft Start Reset Threshold
330
µA
0.35
V
Oscillator
VRT
RT Pin Voltage
1.186
IRT
RT Pin Current Limit
VRT = 0V
fOSC
Oscillator Frequency
RT = 280k, VIN = 12V
RT = 105k, VIN = 12V
RT = 46.4k, VIN = 12V
185
470
950
fSYNC
Sync Frequency Range (Note 5)
RT = 348k, VIN = 12V
SYNC LOGIC
High Level Voltage
Low Level Voltage
VIN = 12V, VCC = 3V to 5.5V
1.205
1.224
–80
205
510
1050
V
µA
225
550
1150
kHz
kHz
kHz
200
1000
kHz
2.4
0
VCC
0.6
V
V
1.234
V
Error Amplifiers and Loop Dynamics
VFB
FB Regulation Voltage
VISP = VISN = 5V
l
1.186
1.210
FB Input Bias Current
VISP = VISN = 5V, VFB Regulated
LED Regulation Voltage
VISP = VISN = 5V, VFB = 1V
TOFF(MIN)
Minimum GATE Off Time
VIN = 12V, VISP = VISN = 5V, VFB = 1V
120
ns
TON(MIN)
Minimum GATE On Time
VIN = 12V, (VISP – VISN) = 60mV, VISN = 5V,
VFB = 1V
200
ns
IFB
–120
0.44
0.54
nA
0.64
V
Current Sense Amplifier
ISP/ISN Pin Common Mode
VISP = VISN
l
VIN to ISN Dropout Voltage (VIN – VISN)
VIN = 12V, VISP = VISN, VFB = 1V
l
IISP
Current Limit Sense Threshold (VISP – VISN) VFB = 1V
ISP Input Bias Current
IISN
ISN Input Bias Current
0
34
13
V
1.7
2
V
46.5
59
mV
–23
µA
–48
µA
3746fa
For more information www.linear.com/3746
3
LT3746
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V,
VISP = VISN = 0V, RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VBIAS
CAP Bias Voltage (VIN – VCAP)
7V < VIN < 55V
6.54
6.77
7.00
ICAP
CAP Bias Current Limit
(VIN – VCAP) = VBIAS – 0.5V
22
mA
GATE High Level (VIN – VGATE)
IGATE = –100mA
0.4
V
GATE Low Level (VGATE – VCAP)
IGATE = 100mA
0.3
V
GATE Rise Time
CGATE = 3.3nF to VIN, VIN = 12V
30
ns
GATE Fall Time
CGATE = 3.3nF to VIN, VIN = 12V
30
ns
Gate Driver
V
LED Driver
VISET
Trimmed ISET Pin Voltage
l
1.181
l
0
1.205
1.229
V
13
V
0.2
µA
11.5
21.5
30
16
27.5
37
mA
mA
mA
8
20
%
LEDxx Operating Voltage
VISP = VISN = VLEDxx
LEDxx Leakage Current
LED Channel Off, VISP = VISN = 5V,
VLEDxx = 3V
ILED
LED Constant Sink Current
VISP = VISN = 5V, VLEDxx = 0.5V
REGDC = 0x00
REGDC = 0x20
REGDC = 0x3F
∆ILEDC
Current Mismatch Between Channels
VISP = VISN = 5V, VLEDxx = 0.5V,
REGDC = 0x20 (Note 6)
∆ILEDD
Current Mismatch Between Devices
VISP = VISN = 5V, VLEDxx = 0.5V,
REGDC = 0x20 (Note 7)
–15
5
20
%
∆ILINE
LED Current Line Regulation
VISP = VISN = 5V, VLEDxx = 0.5V,
REGDC = 0x20, VCC = 3V to 5.5V (Note 8)
–0.2
0.2
1
%/V
∆ILOAD
LED Current Load Regulation
VISP = VISN = 5V, REGDC = 0x20,
VLEDxx = 0.5V to 2.5V (Note 9)
–1
1
3
%/V
VOPEN
Open LED Threshold
VISP = VISN = 5V, VLEDxx Falling
VSHT
Short LED Threshold
VISP = VISN = 5V, VLEDxx Rising
TLEDON
Minimum LED On Time
VISP = VISN = 5V, REGGS = 0x001
PWMCK LOGIC
High Level Voltage
Low Level Voltage
VCC = 3V to 5.5V
7
15.5
23
0.1
3.65
3.9
V
4.15
0.5
2.4
0
V
µs
VCC
0.6
V
V
20.6
µA
Thermal Protection
ITSET
TSET Output Current
V TSET = 1V
TSET Over Temperature Threshold
TA = 25°C
l
19.0
19.8
510
mV
Serial Data Interface
VSIH
VSIL
Single-Ended Input (Note 10)
High Level Voltage
Low Level Voltage
VCC = 3V to 5.5V
ISI
Single-Ended Input Current
VCC = 3V to 5.5V, SI = VCC or GND
VSOH
VSOL
Single-Ended Output (Note 10)
High Level Voltage
Low Level Voltage
VCC = 3V to 5.5V
ISO = –1mA
ISO = 1mA
4
2.4
0
VCC
0.6
V
V
–0.2
0.2
µA
0.1
V
V
V
VCC – 0.1
3746fa
For more information www.linear.com/3746
LT3746
TIMING Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, VCC = 3V to 5.5V, VEN/UVLO = 1.5V, VFB = 1.5V,
VISP = VISN = 5V, VLEDxx = 0.5V, RT = 105k, RISET = 60.4k, CCAP = 0.47µF to VIN, CSCKO = CSDO = CLDO = 27pF to GND, unless
otherwise noted.
SYMBOL
PARAMETER
fSCKI
Data Shift Clock Frequency
CONDITIONS
l
MIN
TYP
MAX
30
UNITS
MHz
fPWMCK
PWMCK Clock Frequency
l
25
MHz
tWH-CKI
tWL-CKI
SCKI Pulse Duration
tWH-PWM
tWL-PWM
SCKI = H (Figure 3)
SCKI = L (Figure 3)
l
l
16
16
ns
ns
PWMCK Pulse Duration
PWMCK = H (Figure 4)
PWMCK = L (Figure 4)
l
l
20
20
ns
ns
tWH-LDI
LDI Pulse Duration
LDI = H (Figure 3)
l
20
ns
tSU-SDI
SDI-SCKI Setup Time
SDI – SCKI ↑ (Figure 3)
l
2
ns
tHD-SDI
SCKI-SDI Hold Time
SCKI ↑ – SDI (Figure 3)
l
2
ns
tSU-LDI
SCKI-LDI Setup Time
SCKI ↓ – LDI ↑ (Figure 3)
l
5
ns
tHD-LDI
LDI-SCKI Hold Time
LDI ↓ – SCKI ↑ (Figure 3)
l
15
ns
tPD-SCK↑
SCKI-SCKO Propagation Delay (Rising) SCKI ↑ – SCKO ↑ (Figure 3)
l
l
27
44
30
50
ns
tPD-SCK↓
SCKI-SCKO Propagation Delay (Falling) SCKI ↓ – SCKO ↓ (Figure 3)
∆tPD-SCK
SCK Duty Cycle Change
∆tPD-SCK = tPD-SCK↑ – tPD-SCK↓
tPD-SD
SCKO-SDO Propagation Delay
SCKO ↑ – SDO (Figure 3)
l
tPD-LD↑
LDI-LDO Propagation Delay (Rising)
LDI ↑ – LDO ↑ (Figure 3)
tPD-LD↓
LDI-LDO Propagation Delay (Falling)
LDI ↓ – LDO ↓ (Figure 3)
∆tPD-LD
LD Duty Cycle Change
∆tPD-LD = tPD-LD↑ – tPD-LD↓
–3
ns
–3
2.2
ns
ns
4.5
7
ns
l
27
44
ns
l
30
50
ns
tPD-PWM
PWMCK-LED Propagation Delay
PWMCK ↑ – ILED (Figure 4)
80
ns
tR-SO
SCKO/SDO/LDO Rise Time
CLOAD = 27pF, 10% to 90%
3
ns
tF-SO
SCKO/SDO/LDO Fall Time
CLOAD = 27pF, 90% to 10%
3
ns
Table 1. Test Parameter Equations
IOUT(MAX)(0−31) – IOUT(MIN)(0−31)
2 • IOUTavg(0−31)
ΔILEDD(%) =
•100
IOUT(AVG)(0−31) – IOUT(CAL)
I OUT(CAL)
(1)
•100
(2)
⎛ 1.205V ⎞
IOUT(CAL) =1000 • ⎜
⎝ RISET ⎟⎠
∆ILINE(% / V) =
∆ILOAD(% / V) =
IOUTn
IOUTn
VCC = 5.5V
IOUTn
VCC = 3.0V
VCC = 3.0V
VOUTn= 2.5V
IOUTn
– IOUTn
– IOUTn
(3)
•
100
2.5V
VOUTn= 0.5V
•
VOUTn= 0.5V
100
2.0V
(4)
(5)
3746fa
For more information www.linear.com/3746
5
LT3746
Electrical Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3746E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3746I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: This IC includes thermal shutdown protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when thermal shutdown protection is
active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 4: The VCC supply current with LED channel on highly depends on
the LED current setting and LEDxx pin voltage; its test condition is
RISET = 60.4k, REGDC = 0x3F, REGGS = 0xFFF, VISP = VISN = 5V,
VLEDxx = 0.5V. The VCC supply current with serial data interface on highly
depends on VCC supply voltage, serial data interface clock frequency,
6
SCKO/SDO/LDO loading capacitance, and PWMCK clock frequency; its
test condition is VCC = 3.3V, fSCKI = 30MHz, CSCKO = CSDO = CLDO = 27pF,
fPWMCK = 409.6KHz.
Note 5: The SYNC frequency must be higher than the RT programmed
oscillator frequency, and is suggested to be around 20% higher.
Any SYNC frequency higher than the suggested value may introduce
sub-harmonic oscillation in the converter due to insufficient slope
compensation. See Application Information section.
Note 6: The Current Mismatch between Channels is calculated as
Equation 1 in Table 1.
Note 7: The Current Mismatch between Devices is calculated as
Equations 2 and 3 in Table 1.
Note 8: The LED Current Line Regulation is calculated as Equation 4 in
Table 1.
Note 9: The LED Current Load Regulation is calculated as Equation 5 in
Table 1.
Note 10: The specifications of single-ended input SI apply to SCKI, SDI,
and LDI pins; the specifications of single-ended output SO apply to
SCKO, SDO, and LDO pins.
3746fa
For more information www.linear.com/3746
LT3746
Typical Performance Characteristics
100Hz 8:1 GS Dimming
TA = 25°C, unless otherwise noted.
100Hz 4096:1 GS Dimming
ILED31
20mA/DIV
VOUT
2V/DIV
VLED31
2VDIV
VPWMCK
5V/DIV
500Hz 4096:1 GS Dimming
ILED31
20mA/DIV
VOUT
2V/DIV
VLED31
2VDIV
VPWMCK
5V/DIV
5ms/DIV
500ns/DIV
3746 G01
CIRCUIT OF FIGURE 7:
DC31 = 0×20,
GS31 = 0×200
500ns/DIV
3746 G02
CIRCUIT OF FIGURE 7:
DC31 = 0×20,
GS31 = 0×001
200Hz Two-Level DC Dimming
ILED31
20mA/DIV
VOUT
2V/DIV
VLED31
2VDIV
VSCKI
5V/DIV
VOUT
2V/DIV
VLED31
2VDIV
VSCKI
5V/DIV
(A) (B) (C)
1ms/DIV
CIRCUIT OF FIGURE 7:
(A) EN = 1, GS31 = 0×FF;
(B) EN = 1, DC31 = 0×3F;
(C) EN = 1, DC31 = 0×00
Adaptive LED Bus Voltage I
VOUT
0.2V/DIV
IL
0.5A/DIV
ILOAD
0.5A/DIV
(A)
(B)
(C)
(D)
0.5ms/DIV
3746 G04
3746 G05
2ms/DIV
CIRCUIT OF FIGURE 7:
(A) EN = 0, GS31 = 0×FFF,
(B) EN = 1, DC31 = 0×3F,
(C) EN = 1, DC31 = 0×00
(D) EN = 1, DC31 = 0×20
Adaptive LED Bus Voltage II
Adaptive LED Bus Voltage III
Adaptive LED Bus Voltage IV
VOUT
0.2V/DIV
VOUT
0.2V/DIV
IL
0.5A/DIV
IL
0.5A/DIV
IL
0.5A/DIV
ILOAD
0.5A/DIV
ILOAD
0.5A/DIV
ILOAD
0.5A/DIV
CIRCUIT OF FIGURE 7:
DC00-31 = 0×20,
GS00-31 = 0×800
3746 G07
2ms/DIV
3746 G06
CIRCUIT OF FIGURE 7:
DC00-31 = 0×3F,
GS00-31 = 0×FFF
VOUT
0.2V/DIV
2ms/DIV
3746 G03
CIRCUIT OF FIGURE 7:
DC31 = 0×20,
GS31 = 0×001
200Hz Four-Level DC Dimming
ILED31
20mA/DIV
(A) (B) (C)
ILED31
20mA/DIV
VOUT
2V/DIV
VLED31
2VDIV
VPWMCK
5V/DIV
3746 G08
CIRCUIT OF FIGURE 7:
DC00-31 = 0×3F, GS00-03 = 0×1FF, GS04-07 = 0×3FF,
GS08-11 = 0×5FF, GS12-15 = 0×7FF, GS16-19 = 0×9FF,
GS20-23 = 0×BFF, GS24-27 = 0×DFF, GS28-31 = 0×FFF
2ms/DIV
3746 G09
CIRCUIT OF FIGURE 7:
DC00-07 = 0×3F, GS00-07 = 0×3FF, DC08-15 = 0×2F,
GS08-15 = 0×7FF, DC16-23 = 0×1F, DC16-23 = 0×BFF,
DC24-31 = 0×0F, GS24-31 = 0×FFF
3746fa
For more information www.linear.com/3746
7
LT3746
Typical Performance Characteristics
Buck Efficiency
5
95
24VIN, 12VOUT at 1MHz
90
0.43
4
0.42
T = 125°C
12VIN, 4VOUT at 500kHz
80
75
3
IVIN (mA)
85
IVIN (µA)
EFFICIENCY (%)
Quiescent IVIN vs VIN
Shutdown IVIN vs VIN
100
2
48VIN, 4VOUT at 200kHz
70
T = –40°C
1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
0.39
0
10
20
30
VIN (V)
40
50
0.38
60
T = 125°C
10.30
T = 125°C
3.35
3.30
T = –40°C
3.5
4.0
4.5
VCC (V)
5.0
IVCC (mA)
IVCC (mA)
3.0
T = 25°C
3.25
3.20
3.05
5.5
10.20
T = 125°C
10.15
10.10
T = –40°C
T = –40°C
10.00
3.0
3.5
4.0
4.5
VCC (V)
5.0
9.95
5.5
3.0
VCC (V)
IVCC (mA)
T = 125°C
2.80
1.28
2.75
UVLO–
2.65
3.0
3.5
4.0
4.5
VCC (V)
5.0
5.5
3746 G16
8
1.30
2.70
17
15
2.85
VEN/UVLO (V)
T = 25°C
T = –40°C
5.0
2.60
–50
5.5
1.32
UVLO+
19
4.0
4.5
VCC (V)
EN/UVLO UVLO Threshold vs
Temperature
2.90
21
3.5
3746 G15
VCC UVLO Threshold vs
Temperature
27
60
T = 25°C
3746 G14
IVCC vs VCC – Channel On, Data On
23
50
10.05
3.10
3746 G13
25
40
10.25
3.15
T = 25°C
30
VIN (V)
10.35
3.40
8
2
20
IVCC vs VCC – Channel On, Data Off
3.45
4
10
3746 G12
IVCC vs VCC – Channel Off, Data Off
IVCC vs VCC – Shutdown Mode
6
0
3746 G11
10
IVCC (µA)
T = 25°C
0.40
T = –40°C
3746 G10
0
T = 125°C
0.41
T = 25°C
65
60
TA = 25°C, unless otherwise noted.
UVLO+
1.26
1.24
UVLO–
1.22
–25
0
25
50
75 100
JUNCTION TEMPERATURE (°C)
125
3746 G17
1.20
–50
–25
0
25
50
75 100
JUNCTION TEMPERATURE (°C)
125
3746 G18
3746fa
For more information www.linear.com/3746
LT3746
Typical Performance Characteristics
(VIN - VCAP) UVLO Threshold vs
Temperature
4.90
1000
TA = 25°C, unless otherwise noted.
Oscillator Frequency fOSC vs
Temperature
Oscillator Frequency fOSC vs RT
520
800
4.70
600
4.60
510
fOSC (kHz)
4.80
fOSC (kHz)
VIN - VCAP (V)
UVLO+
400
UVLO–
4.50
490
200
4.40
–50
–25
0
25
50
75 100
JUNCTION TEMPERATURE (°C)
0
125
20
60
100
140 180
RT (kΩ)
220
1.208
–10.0
–10.2
0.51
1.202
–10.4
ISS (µA)
VLEDxx (V)
VFB (V)
Soft-Start Charge Current ISS vs
Temperature
0.52
1.206
0.50
–10.6
0.49
1.200
200
400
600
800
LOAD CURRENT (mA)
0.48
1000
–10.8
0
200
400
600
800
LOAD CURRENT (mA)
3746 G22
1000
–11.0
–50
–25
0
25
50
75 100
JUNCTION TEMPERATURE (°C)
Current Sense Threshold
(VISP - VISN) vs VISN
CAP Bias Voltage (VIN - VCAP)
vs VIN
6.90
6.90
CAP Bias Voltage (VIN - VCAP)
vs ICAP
6.80
6.86
T = –40°C
47
T = 25°C
T = 125°C
6.82
T = 25°C
6.78
T = –40°C
6.60
T = 125°C
6.50
6.40
46
T = 125°C
6.74
6.30
T = –40°C
45
T = 25°C
6.70
VIN -VCAP (V)
VIN -VCAP (V)
VISP -VISN (mV)
48
125
3746 G24
3746 G23
49
125
3746 G21
LED Regulation Voltage vs
Load Current
1.204
–25
0
25
50
75 100
JUNCTION TEMPERATURE (°C)
3746 G20
FB Regulation Voltage vs
Load Current
0
480
–50
300
260
3746 G19
1.198
500
0
3
6
9
VISN (V)
12
15
3746 G25
6.70
0
10
20
30
VIN (V)
40
50
60
3746 G26
6.20
0
4
8
12
16
ICAP (mA)
20
24
3746 G27
3746fa
For more information www.linear.com/3746
9
LT3746
Typical Performance Characteristics
1.208
16
1.206
12
1.204
LED Current ILED vs
Dot Correction
Nominal LED Current vs RISET
30
25
20
ILED (mA)
20
ILED (mA)
VISET (V)
1.210
VISET Pin Voltage vs Temperature
TA = 25°C, unless otherwise noted.
8
15
10
1.202
4
1.200
–50
–25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
0
125
5
40
80
120
160 200
RISET (kΩ)
240
280
3746 G28
23
9
DC = 0×20
20
15
DC = 0×00
VLED (V)
21
20
6
19
10
3
18
5
0
0.5
1.0
1.5
2.0
VLED (V)
2.5
17
–50
3.0
3746 G31
16
VTSET (mV)
12
8
4
4
8
12
IISET (µA)
16
20
3746 G34
10
0
125
0
4
8
VISN (V)
35
650
30
600
25
550
500
20
15
450
10
400
5
–25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
16
LED Current Derating vs
Temperature
700
350
–50
12
3746 G33
T SET Threshold vs Temperature
20
0
–25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
3746 G32
T SET Current vs ISET Current
ITSET (µA)
Short LED Threshold vs VISN
22
ILED (mA)
ILED (mA)
12
DC = 0×3F
25
0
10 16 22 28 34 40 46 52 58 64
DOT CORRECTION +1
3746 G30
LED Current Variation ILED vs
Temperature
LED Current ILED vs LED Voltage
VLED
30
0
4
3746 G29
ILED (mA)
35
0
320
125
3746 G35
0
OT = 0
80
85
OT = 1
90 95 100 105 110 115 120
JUNCTION TEMPERATURE (°C)
3746 G36
3746fa
For more information www.linear.com/3746
LT3746
Pin Functions
EN/UVLO (Pin 1): Enable and Undervoltage Lockout
(UVLO) Pin. The pin can accept a digital input signal to
enable or disable the chip. Tie to 0.35V or lower to shut
down the chip or tie to 1.34V or higher for normal operation.
This pin can also be connected to VIN through a resistor
divider to program a power input UVLO threshold. If both
the enable and UVLO functions are not used, tie this pin
to VCC pin.
LED00 to LED31 (Pins 2-17, 30-45): LED Driver Output
Pins. Connect the cathodes of LED strings to these pins.
GND (Pin 18, 20, 27, 29): Ground Pin.
SCKI (Pin 19): Serial Interface TTL/CMOS Logic Clock
Input Pin.
SDI (Pin 21): Serial Interface TTL/CMOS Logic Data
Input Pin.
LDI (Pin 22): Serial Interface TTL/CMOS Logic Latch Input
Pin. An asynchronous input signal at this pin latches the
serial data in the shift registers into the proper registers
and the status information is ready to shift out with the
coming clock pulses. See more details in the Operation
section.
VCC (Pin 23): Logic and Control Supply Pin. The pin powers
serial data interface and internal control circuitry. Must be
locally bypassed with a capacitor to ground.
PWMCK (Pin 24): Grayscale PWM Dimming TTL/CMOS
Logic Clock Pin. Individual PWM dimming signal is generated by counting this clock pulse from zero to the bits in
its 12-bit grayscale PWM register.
LDO (Pin 25): Serial Interface TTL/CMOS Logic Latch
Output Pin.
SDO (Pin 26): Serial Interface TTL/CMOS Logic Data
Output Pin.
SCKO (Pin 28): Serial Interface TTL/CMOS Logic Clock
Output Pin.
SYNC (Pin 46): Switching Frequency Synchronization
Pin. Synchronizes the internal oscillator frequency to an
external clock applied to the SYNC pin. The SYNC pin is
TTL/CMOS logic compatible. Tie to ground or VCC if not
used.
RT (Pin 47): Timing Resistor Pin. Programs the switching
frequency from 200kHz to 1MHz. See Table 2 for the recommended RT values for common switching frequencies.
SS (Pin 48): Soft Start Pin. Placing a capacitor here programs soft start timing to limit inductor inrush current
during startup. The soft start cycle will not begin until all
the VCC, EN/UVLO, and (VIN - VCAP) voltages are higher
than their respective UVLO thresholds.
FB (Pin 49): Feedback Pin. The pin is regulated to the
internal band-gap reference 1.205V during startup and
precharging phases. Connect to a resistor divider from
the buck converter output to program the maximum LED
bus voltage. See more details in the Applications Information section.
ISN (Pin 50): Negative Inductor Current Sense Pin. The
pin is connected to one terminal of the external inductor
current sensing resistor and the buck converter output
supplying parallel LED channels.
ISP (Pin 51): Positive Inductor Current Sense Pin. The pin
is connected to the inductor and the other terminal of the
external inductor current sensing resistor.
CAP (Pin 52): VIN Referenced Regulator Supply Capacitor
Pin. The pin holds the negative terminal of an internal VIN
referenced 6.8V linear regulator used to bias the gate driver
circuitry. Must be locally bypassed with a capacitor to VIN.
GATE (Pin 53): Gate Driver Pin. The pin drives an external
P-channel power MOSFET with a typical peak current of 1A.
Connect this pin to the gate of the power MOSFET with a
short and wide PCB trace to minimize trace inductance.
VIN (Pin 54): Power Input Supply Pin. Must be locally
bypassed with a capacitor to ground.
TSET (Pin 55): Temperature Threshold Setting Pin. A
resistor to ground programs overtemperature threshold.
See more details in the Applications Information section.
ISET (Pin 56): Nominal LED Current Setting Pin. A resistor
to ground programs the nominal LED current for all the
channels. See more details in the Applications Information section.
Exposed Pad (Pin 57): Ground Pin. Must be soldered to a
continuous copper ground plane to reduce die temperature
and to increase the power capability of the device.
3746fa
For more information www.linear.com/3746
11
12
CVCC
VCC
RFB1
RFB2
CSS
For more information www.linear.com/3746
25
26
LDO
SDO
SCKO
SCKI
SDI
384
SCKO SDO
SHIFT
REGISTER
C1
x
STATUS
INFO
(FAULT
LEDXX)
C0
OT
SCKI SDI
384
R
S
Q
32X
6
12
POR
–
–
GM2
...
DELAY
6
12
FAULT LEDXX
DC REGISTER
FS
GS REGISTER
FS
FS
0.5V LED00 LED01
EN
+
RAMP
–
R
S
OPEN/SHORT
LED
+
–
+
–
IREF
DRIVER
TSET
ISET
CAP
GATE
VIN
VPTAT
OT
CONSTANT CURRENT
SINK
1.205V
6.8V
Q
PWMCK
12-BIT PWM
DIMMING
IREF
6-BIT DOT
CORRECTION
EN
LED31
+
–
SYNC
46
OSC
47
RT
55
56
52
53
54
3746 BD
GND
+
–
28
19
21
PRECHG
+
–
GM1
VSS < 1V
PG
1.205V
REFERENCE BIAS
(VIN - VCAP)
AND UVLO
UV
+
–
LDI
PWMCK
FB
VCC
EN/UVLO
SS
ISP
RT
+
–
22
24
49
23
1
48
12µA
ISN
50 51
D1
M1
L
CIN
RS
(18, 20, 27, 29, EXPOSED PAD 57)
LEDXX
RTSET
RISET
CCAP
VIN
32X
COUT
VOUT
LT3746
Block Diagram
3746fa
LT3746
OPERATION
The LT3746 integrates a single constant-frequency currentmode nonsynchronous buck controller with thirty-two
linear current sinks. The buck controller generates an
adaptive output LED bus voltage to supply parallel LED
strings and the thirty-two linear current sinks regulate
and modulate individual LED strings. Its operation is best
understood by referring to the Block Diagram.
Serial Data Interface
Start-Up
In a conventional 4-wire topology shown in Figure 1, the LDI
and SCKI signals need global routing while the SDI signal
only needs local routing between chips. Depending on the
number of chips in cascade and the size of system PCB
board, external clock-tree type buffers with corresponding
driving capability are needed for both the LDI and SCKI
signals to minimize signal skews. The propagation delay
caused by the buffer insertion on the SCKI signal yields
the clock skew between the SCKI and SDI signals, which
usually requires the customer end to balance it. Since both
the SDI and SDO signals require the same SCKI signal to
send and receive, the propagation delay between the SDI
and SDO signals limits the number of chips in cascade
and the series data interface clock frequency.
The LT3746 enters shutdown mode and drains almost zero
current when the EN/UVLO pin is lower than 0.35V. Once
the EN/UVLO pin is above 0.35V, the part starts to wake
up internal bias currents, generate various references,
and charge the capacitor CCAP towards 6.8V regulation
voltage. This VIN referenced voltage regulator (VIN - VCAP)
will supply the internal gate driver circuitry driving an
external P-channel MOSFET in normal operation. The
LT3746 remains in undervoltage lockout (UVLO) mode
as long as any one of the EN/UVLO, VCC, and (VIN - VCAP)
UVLO flags is high. Their UVLO thresholds are typically
1.31V, 2.89V, and 4.9V, respectively. After all the UVLO
flags are cleared, the buck controller starts to switch, and
the soft start SS pin is released and charged by a 12µA
current source, thereby smoothly ramping up the inductor
current and the output LED bus voltage.
Power-on-Reset (POR)
During start-up, an internal power-on-reset (POR) high
signal blocks the input signals to the serial data interface
and resets all the internal registers except the 386-bit shift
register. The 1-bit frame select (FS) register, 1-bit enable
LED channel (EN) register, individual 12-bit grayscale (GS)
registers, and individual 6-bit dot correction (DC) registers
are all reset to zero. Thus all the LED channels are turned
off initially with the default grayscale (0x000) and dot
correction (0x00) setting. Once the part completes its soft
start (i.e., the SS pin voltage is higher than 1V) and the
output LED bus voltage is power good (i.e., within 5% of
its FB programmed regulation level), the POR signal goes
low to allow the input signals to the serial data interface.
Any fault triggering the soft start will generate another
POR high signal and reset internal registers again.
The LT3746 has a 30MHz, fully-buffered, skew-balanced,
cascadable serial data interface. The interface uses a novel
6-wire (LDI, SCKI, SDI, LDO, SCKO, and SDO) topology
and can be connected to microcontrollers, digital signal
processors (DSPs), or field programmable gate arrays
(FPGAs).
The novel 6-wire topology eliminates the need for global
routing and buffer insertion for the LDI and SCKI signals.
Instead, it provides the LDO and SCKO signals along with
the SDO signal to drive the next chip. The skew inside the
chip among the LDI, SCKI, and SDI signals is balanced
internally. The skew outside the chip among the LDO, SCKO,
and SDO signals can be easily balanced by parallel routing
these three signals between chips. The SDI signal is sent
with the SCKI signal, and the SDO signal is received with the
SCKO signal. A slight duty cycle change between the SCKI
and SCKO signals may occur due to the process variation,
supply voltage and operating temperature. This duty cycle
change results from the difference in propagation delays of
the positive and negative edges of the SCKI/SCKO signals
and will affect the maximum number of cascadable chips,
depending on the SCKI speed. In summary, the 6-wire
topology extends the maximum number of cascadable
chips, boosts the series data interface clock frequency,
eliminates the need for buffer insertion for global signals,
and offers an easy PCB layout. In a low-speed application
with a small number of cascaded chips, the 6-wire topology can be simplified to the 4-wire topology by ignoring
the LDO and SCKO outputs.
3746fa
For more information www.linear.com/3746
13
LT3746
OPERATION
LT3746 6-WIRE TOPOLOGY
CHIP 1 LDO
LDI
CHIP 2 LDO
LDI
CHIP N LDO
LDO
LDI
SCKO
SCKI
SCKO
SCKI
SCKO
SCKI
SCKO
SDO
SDI
SDO
SDI
SDO
SDI
SDO
LDI
CHIP N LDO
CONTROLLER
SDI
SCKI
LDI
CONVENTIONAL 4-WIRE TOPOLOGY
CHIP 1 LDO
LDI
CHIP 2 LDO
LDO
LDI
SCKO
SCKI
SCKO
SCKI
SCKO
SCKI
SCKO
SDO
SDI
SDO
SDI
SDO
SDI
SDO
CONTROLLER
SDI
3746 F01
Figure 1. LT3746 6-Wire Topology vs Conventional 4-Wire Topology
x
x
MSB
DC 31, 6 BITS
0
0
0
0
0
S31
LSB
x
LSB
x
x
x
x
x
x
x
C1
C0
DC FRAME
LSB
MSB
MSB
DC 31, 6 BITS
C1
0
0
0
0
0
S0
0
F0
STATUS FRAME
GS 0, 12 BITS
MSB
x
GS 31, 12 BITS
DC 0, 6 BITS
MSB
LSB
LSB
x
LSB
MSB
386 BITS
DC 0, 6 BITS
C0
GS FRAME
3746 F02
COMMAND REGISTER:
STATUS REGISTER:
C1: ENABLE LED CHANNELS - ENABLE = 1, DISABLE = 0
C0: FRAME SELECT - GS FRAME = 0, DC FRAME = 1
S0-S31: LED 0-31 FAULT - FAULT = 1, OK = 0
F0:
OT - OVER TEMPERATURE = 1, OK = 0
Figure 2. Serial Data Frame Format
14
3746fa
For more information www.linear.com/3746
LT3746
OPERATION
tSU-LDI tWH-LDI tHD-LDI
LDI
tWH-CKI
SCKI
tSU-SDI
tWL-CKI
SDI
SR[0]
385
378
1
DC 31
MSB
SR[1]
384
1
385
386
1
tHD-SDI
DC 0
LSB
DC 31
MSB
386
C1
GS 31
MSB
C0 = 1
GS 0
LSB
C1
GS 31
MSB
C0 = 0
DC 0
LSB
C1
C0 = 1
F0
GS 31
MSB
GS 0
LSB
C1
C0 = 0
F0
DC 0
LSB + 1
x
C1
0
F0
GS 0
LSB + 1
GS 0
LSB
C1
0
GS 31
MSB
F0
tPD-LD↓
tPD-LD↑
LDO
tPD-SCK↑
SCKO
1
378
385
tPD-SCK↓
386
384
385
386
tPD-SD
DC 31
MSB
SDO/
SR[385]
1
DC 31
MSB
DC 31
MSB – 1
0
GS 31
MSB
F0
DC 31
MSB
3746 F03
INPUT DATA
STATUS DATA
Figure 3. Serial Data Input and Output Timing Chart
C1/EN
tWH-PWM
PWMCK
1
tPD-PWM
I(LED00)
REG = 0x002
I(LED01)
REG = 0xFFF
I(LED31)
REG = 0x000
PRECHG
2
3
3584
3585
4095
4096
1
2
tWL-PWM
TRACKING PHASE
PRECHARGING PHASE
3746 F04
Figure 4. Grayscale PWM Dimming and Precharging Signal Timing Chart
3746fa
For more information www.linear.com/3746
15
LT3746
OPERATION
Figure 2 shows two serial data input SDI frames (GS frame
and DC frame) and one serial data output SDO frame (status
frame). All the frames have the same 386-bit in length and
are transmitted with the MSB first and the LSB last. The SDI
frames are sent with the SCKI signal and the SDO frame is
received with the SCKO signal. The C0 bit (frame select)
determines any SDI frame to be either a GS frame (C0 = 0)
or a DC frame (C0 = 1), and the C1 bit (EN) enables (C1 = 1)
or disables (C1 = 0) all the LED channels. The status frame
reads back the TSET pin resistor-programmable overtemperature flag and individual open/short LED fault flags,
as well as the individual 6-bit DC setting.
Inside the part, there are one 386-bit shift register
SR[0:385], one 1-bit frame select (FS) register, one 1-bit
enable LED channel (EN) register, thirty-two 12-bit grayscale (GS) registers, thirty-two 6-bit dot correction (DC)
registers, one 1-bit over temperature (OT) flag register, and
thirty-two 1-bit LED fault flag registers. The input of the
386-bit shift register, i.e., the input of the first bit SR[0],
is connected to the SDI signal. The output of the 386-bit
shift register, i.e., the output of the last bit SR[385] is connected to the SDO signal. The SCKI signal shifts the SDI
frame (GS or DC frame) in and the SCKO signal shift the
SDO frame (status frame) out of the 386-bit shift register
with their rising edges. The LDI high signal latches the SDI
frame (GS or DC frame) from the 386-bit shift register into
corresponding FS, EN, GS or DC registers, and loads the
SDO frame (status frame) from the OT and LED fault flag
registers to the 386-bit shift register at the same time.
The LDO signal is a buffered version of the LDI signal
with certain delay added to match the delay between the
SCKI and SCKO signals. Therefore, a daisy-chain type loop
communication with simultaneous writing and reading
capability is implemented.
Figure 3 illustrates the timing relation among serial input
and serial output signals in more detail. One DC frame followed by another GS frame is sent through the LDI, SCKI,
and SDI signals. At the same time, two status frames are
received through the LDO, SCKO, and SDO signals. The
rising edges of the SCKI signal shift a frame of 386-bit
data at the SDI pin into the 386-bit shift register SR[0:385].
After 386 clock cycles, all the 386-bit data sit in the right
place waiting for the LDI signal. An asynchronous LDI high
signal latches the 1-bit FS register, 1-bit EN register, and
individual 12-bit GS registers (when FS = 0) or 6-bit DC
registers (when FS = 1) for each channel. At the same time,
a frame of status information, including over temperature
flag and individual open/short LED fault flags, is parallel
loaded into the 386-bit shift register and will be shifted
out with the coming clock cycles.
Constant Current Sink
Each LED channel has a local constant current sink regulating its own LED current independent of the LED bus
voltage VOUT. The recommended LED pin voltage ranges
from 0.5V to 2.5V. As shown in the Typical Performance
Characteristics ILED vs VLED curves, the LED current ILED
has the best load regulation when the LED pin voltage VLED
sits between 0.5V to 2.5V. A lower LED bus voltage VOUT
may not regulate all the LED channels across temperature, current, and manufacturing variation, while a higher
4096*TPWMCK
PWM1
VOUT = 4.4V
PWM2
PRECHG
IDEAL VOUT
4.0V
4.4V
3.6V
4.0V
3.6V
+
3.5V
–
4.4V
(3)
+
3.1V
PWM3
LT3746 VOUT
(2)
(1)
+
+
3.9V
–
+
–
+
1.3V
0.9V
0.5V
–
–
–
4.4V
CONSTANT VOUT
3746 F05
t1
t2
t3 t4
Figure 5. Adaptive-Tracking-plus-Precharging LED Bus Voltage Technique
16
3746fa
For more information www.linear.com/3746
LT3746
OPERATION
LED bus voltage VOUT will force a higher LED pin voltage
across the current sink, thereby dissipating more power
inside the part. See more details about the choice of the
LED bus voltage and the power dissipation calculation in
the Application Information section.
Dot Correction and Grayscale Digital-to-Analog
Conversion
The resistor on the ISET pin programs the nominal LED
current (4mA to 20mA) for all the channels. Individual LED
channel can be adjusted to a different current setting by
its own 6-bit dot correction register. The adjustable LED
current ranges from 0.5X to 1.5X of the nominal LED
current in 63 linear steps. See more details about setting
nominal LED current and dot correction in the Applications
Information section.
In addition to the dot correction current adjustment,
individual LED channels can also be modulated by their
own grayscale PWM dimming signal. To achieve a better
performance, all the grayscale PWM dimming signals
are synchronized to the same frequency with no phase
shift between rising edges. Each constant current sink is
enabled or disabled when its grayscale PWM dimming
signal goes high or low. This periodic grayscale PWM
dimming signal is generated by its own 12-bit grayscale
register with a duty cycle from 0/4096 to 4095/4096 and
a period equal to 4096 PWMCK clock cycles.
The generation of the grayscale PWM dimming signal
is best understood by referring to Figure 4. After EN = 1
is set, the first rising edge of the PWMCK signal will increase the internal 12-bit grayscale counter from zero to
one and turn on all the LED channels with grayscale value
not zero. Each following rising edge of the PWMCK signal
increases the grayscale counter by one. Any LED channel
will be turned off when its 12-bit grayscale register value
is equal to the value in the grayscale counter. To generate
a 100% duty cycle for all the grayscale PWM dimming
signals, the PWMCK signal can be paused before counting
to the value in any individual 12-bit grayscale registers.
Setting EN = 0 will reset the grayscale counter to zero and
turn off all the LED channels immediately.
Dual-Loop Analog OR Control
The switching frequency can be programmed from 200kHz
to 1MHz with the resistor connected to the RT pin and it
can be synchronized to an external clock using the SYNC
pin. Each switching cycle starts with the gate driver
turning on the external P-channel MOSFET M1 and the
inductor current is sampled through the sense resistor RS
between the ISP and ISN pins. This current is amplified
and added to a slope compensation ramp signal, and the
resulting sum is fed into the positive terminal of the PWM
comparator. When this voltage exceeds the level at the
negative terminal of the PWM comparator, the gate driver
turns off M1. The level at the negative terminal of the PWM
comparator is set by either of two error amplifiers GM1
and GM2. In this dual-loop analog OR control, the FB loop
GM1 regulates the FB pin voltage to 1.205V and the LED
loop GM2 regulates the minimum active LED pin voltage
(LED00 to LED31) to 0.5V. In the startup phase, the GM2
is disabled and the output LED bus voltage is regulated
towards the feedback resistor programmed LED bus voltage. This FB programmed voltage defines the maximum
LED bus voltage and should be programmed high enough
to supply the worst case LED string across temperature,
current, and manufacturing variation.
Adaptive-Tracking-Plus-Precharging
Higher system efficiency and faster transient response
are two highly anticipated specifications in an individually-modulated multi-channel LED driver chip.
The LT3746 uses a patent pending adaptive-trackingplus-precharging technique to achieve both of them
simultaneously.
Besides 32 internal grayscale PWM dimming signals,
the part also generates another internal precharging
signal PRECHG. As shown in Figure 4, the PRECHG
signal divides any grayscale PWM dimming cycle
into two phases: tracking phase when PRECHG = 0
and precharging phase when PRECHG = 1. During
each grayscale PWM dimming cycle – 4096 PWMCK
clock cycles, the PRECHG signal stays low for the first
3584 clock cycles (7/8 of the grayscale PWM dimming
3746fa
For more information www.linear.com/3746
17
LT3746
OPERATION
period) and goes high for the rest 512 clock cycles (1/8
of the grayscale PWM dimming period). In the event of
all the LED channels being not active (i.e., either fault
or off) before the 3585th PWMCK clock, the PRECHG
signal will go high immediately.
To better explain the operation of the adaptive-trackingplus-precharging technique, a simplified application
system with 3-channel LED array is presented in
Figure 5. Each channel consists of a single LED with
the forward voltage drop equal to 3.1V, 3.5V, and 3.9V,
respectively. Three internal grayscale PWM dimming
signals PWM1, PWM2, and PWM3 are used to modulate
each LED channel.
At the beginning of each grayscale PWM dimming cycle,
all three LED channels are turned on and the tracking
phase starts with PRECHG = 0. The amplifier GM2 is
enabled and takes the control from the amplifier GM1,
regulating the minimum active LED pin voltage to 0.5V.
With the VLED3 equal to 0.5V, the output LED bus voltage
is tracked to 4.4V. Subsequently, at a certain time instant
t1 when the third channel is turned off, the minimum
active LED pin voltage goes to VLED2, 0.9V. Then the
amplifier GM2 tracks the output LED bus voltage down
to 4V to maintain the minimum active LED pin voltage
18
equal to 0.5V again. Similarly at the next time instant t 2,
the output LED bus voltage is tracked down to 3.6V. In
this manner, the adaptive-tracking technique eliminates
unnecessary power dissipation across the current sinks
and yields superior system efficiency when compared
to a constant 4.4V output voltage.
At a later time instant t3 when the PRECHG signal goes
high, the amplifier GM2 is disabled and gives the control
back to the amplifier GM1. The amplifier GM1 regulates
the output LED bus voltage towards the FB programmed
maximum value 4.4V to guarantee shorter minimum
LED on-time for the next grayscale PWM dimming
cycle. Without the precharging phase, the output LED
bus voltage will stay at 3.6V before the next grayscale
PWM dimming cycle, when all the 3 LED channels will be
turned on again. At that time the 3.6V LED bus voltage
is too low to keep all the LED channels in regulation,
and the minimum LED on time is greatly increased to
accommodate the slow transient response of the switching buck converter charging the output capacitor from
3.6V to 4.4V. This adaptive-tracking-plus-precharging
LED bus voltage technique simultaneously lowers the
power dissipation in the LT3746 and maintains a shorter
minimum LED on-time.
3746fa
For more information www.linear.com/3746
LT3746
Applications Information
Globally, the LT3746 converts a higher input voltage to a
single lower LED bus voltage (VOUT ) supplying 32 parallel
LED strings with the adaptive-tracking-plus-precharging
technique. Locally, the part regulates and modulates the
current of each string to an independent dot correction and
grayscale PWM dimming setting sent by TTL/CMOS logic
serial data interface. This Application Information section
serves as a guideline of selecting external components
(refer to the Block Diagram) and avoiding common pitfalls
for the typical application.
Programming Maximum VOUT
The adaptive-tracking-plus-precharging technique regulates VOUT to its maximum value during the startup and
precharging phases, and adaptively lowers the voltage
to keep the minimum active LED pin voltage around 0.5V
during the tracking phase. Therefore, the maximum VOUT
should be programmed high enough to keep all the LED
pin voltages higher than 0.5V to maintain LED current
regulation across temperature, current, and manufacturing variation. As a starting point, the maximum LED bus
voltage, VOUT(MAX), can be calculated as:
VOUT(MAX) =0.5V +n • VF(MAX)
where n is the number of LED per string and VF(MAX) is
the maximum LED forward voltage rated at the highest
operating current and the lowest operating temperature.
The VOUT(MAX) is programmed with a resistor divider
between the output and the FB pin. The resistor values
are calculated as:
Ê VOUT(MAX) ˆ
RFB2 =RFB1Á
- 1˜
Ë 1.205V
¯
Another restriction on the minimum input voltage VIN(MIN)
is the 2V minimum dropout voltage between the VIN and
ISN pins, and thus the VIN(MIN) is calculated as:
VIN(MIN) = VOUT(MAX) + 2V
Choosing Switching Frequency
Selection of the switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
and gate charge losses. However, lower frequency operation requires larger inductor and capacitor values.
Another restriction on the switching frequency comes
from the input and output voltage range caused by the
minimum switch on and switch off time. The highest
switching frequency fSW(MAX) for a given application can
be calculated as:
 D
1– DMAX 

fSW(MAX) =MIN  MIN ,

t
t
 ON(MIN) OFF(MIN) 
where the minimum duty cycle DMIN and the maximum
duty cycle DMAX are determined by:
D MIN =
VOUT(MIN) + VD
VIN(MAX) + VD
and D MAX =
VOUT(MAX) + VD
VIN(MIN) + VD
tON(MIN) is the minimum switch on time (~200ns), tOFF(MIN)
is the minimum switch off time (~120ns), VOUT(MIN) is the
minimum adaptive output voltage, VIN(MAX) is the maximum input voltage, and VD is the catch diode forward voltage (~0.5V). The calculation of fSW(MAX) simplifies to:
fSW(MAX) =
Tolerance of the feedback resistors will add additional errors
to the output voltage, so 1% resistor values should be used.
The FB pin output bias current is typically 120nA, so use of
extremely high value feedback resistors could also cause
bias current errors. A typical value for RFB1 is 10k.
VIN Power Input Supply Range
The power input supply for the LT3746 can range from 6V
to 55V, covering a wide variety of industrial power supplies.
 V
VIN(MIN) – VOUT(MAX)
OUT(MIN) + VD
MHz
MIN 5 •
, 8.33 •
VIN(MAX) + VD
VIN(MIN) + VD 

Obviously, lower frequency operation accommodates both
extremely high and low VOUT to VIN ratios.
Besides these common considerations, the specific
application also plays an important role in switching frequency choice. In a noise-sensitive system, the switching
3746fa
For more information www.linear.com/3746
19
LT3746
Applications Information
frequency is usually chosen to keep the switching noise
out of a sensitive frequency band.
Switching Frequency Setting and Synchronization
The LT3746 uses a constant switching frequency that can
be programmed from 200kHz to 1MHz with a resistor
from the RT pin to ground. Table 2 shows RT values for
common switching frequencies.
Table 2. Switching Frequency fSW vs RT Value
f SW (kHz)
RT * (kΩ)
200
280
300
182
400
133
500
105
600
84.5
700
71.5
800
60.4
900
53.6
1000
46.4
* Recommend 1% Standard Values
Synchronizing the LT3746 oscillator to an external frequency can be achieved using the SYNC pin. The square
wave amplitude, compatible to TTL/CMOS logic, should
have valleys that are below 0.6V and peaks that are above
2.4V. The synchronization frequency also ranges from
200kHz to 1MHz, in which the RT resistor should be chosen
to set the internal switching frequency around 20% below
the synchronization frequency. In the case of 200kHz
synchronization frequency, RT = 348k is recommended.
It is also important to note that when the synchronization frequency is much higher than the RT programmed
internal frequency, the internal slope compensation will
be significantly reduced, which may trigger sub-harmonic
oscillation at duty cycles greater than 50%.
Inductor Current Sense Resistor RS and Current Limit
The current sense resistor, RS, monitors the inductor
current between the ISP and ISN pins, which are the inputs to the internal current sense amplifier. The common
mode input voltage of the current sense amplifier ranges
20
from 0V to (VIN – 2V) or 13V absolute maximum value,
whichever is lower. The current sense amplifier not only
provides current information to form the current-mode
control, but also a 46.5mV threshold. The 46.5mV threshold
across the RS resistor imposes an accurate current limit
to protect both P-channel MOSFET M1 and catch diode
D1, and also to prevent inductor current saturation. Good
Kelvin sensing is required for accurate current limit. The
RS resistor value can be determined by:
I OUT(MAX) =I L(MAX) –
Δ IL
2
where the maximum inductor current IL(MAX) is set by:
I L(MAX) =
46.5mV
RS
IOUT(MAX) is the maximum output load current, and ∆IL
is the inductor peak-to-peak ripple current. Allowing adequate margin for ripple current and external component
tolerances, RS can be estimated as:
RS =
35mV
I OUT(MAX)
Inductor Selection
The critical parameters for selection of an inductor are
inductance value, DC or RMS current, saturation current,
and DCR resistance. For a given input and output voltage,
the inductor value and switching frequency will determine
the peak-to-peak ripple current, ∆IL. The ∆IL value usually
ranges from 20% to 50% of the maximum output load
current, IOUT(MAX). Lower values of ∆IL require larger and
more costly inductors; higher values of ∆IL increase the
peak currents and the inductor core loss. An inductor
current ripple of 30% to 40% offers a good compromise
between inductor performance and inductor size and cost.
However, for high duty cycle applications, a ∆IL value of
~20% should be used to prevent sub-harmonic oscillation
due to insufficient slope compensation.
3746fa
For more information www.linear.com/3746
LT3746
Applications Information
The largest inductor ripple current occurs at the highest
VIN. To guarantee that the ripple current stays below the
specified maximum, the inductor value should be chosen
according to the following equation:
L≥
VIN(MAX) – VOUT
VOUT + VD
•
VIN(MAX) + VD
f SW • ΔI L
The inductor DC or RMS current rating must be greater
than the maximum output load current IOUT(MAX) and its
saturation current should be higher than the maximum
inductor current IL(MAX). To achieve high efficiency, the DCR
resistance should be less than 0.1Ω, and the core material
should be intended for high frequency applications.
Power MOSFET Selection
Important parameters for the external P-channel MOSFET
M1 include drain-to-source breakdown voltage (V(BR)DSS),
maximum continuous drain current (ID(MAX)), maximum
gate-to-source voltage (VGS(MAX)), total gate charge (QG),
drain-to-source on resistance (RDS(ON)), reverse transfer
capacitance (CRSS). The MOSFET V(BR)DSS specification
should exceed the maximum voltage across the source to
the drain of the MOSFET, which is VIN(MAX) plus VD. The
ID(MAX) should exceed the peak inductor current, IL(MAX).
Since the gate driver circuit is supplied by the internal 6.8V
VIN referenced regulator, the VGS(MAX) rating should be
at least 10V.
Each switching cycle the MOSFET is switched off and on,
a packet of gate charge QG is transferred from the VIN pin
to the GATE pin, and then from the GATE pin to the CAP
pin. The resulting dQG/dt is a current that must be supplied to the CCAP capacitor by the internal regulator. The
maximum 20mA current capability of the internal regulator
limits the maximum QG(MAX) it can deliver to:
Q G(MAX)=
20mA
f SW
Therefore, the QG at VGS = 6.8V from the MOSFET data
sheet should be less than QG(MAX).
For maximum efficiency, both RDS(ON) and CRSS should
be minimized. Lower RDS(ON) means less conduction loss
while lower CRSS reduces transition loss. Unfortunately,
RDS(ON) is inversely related to CRSS. Thus balancing the
conduction loss with the transition loss is a good criterion
in selecting a MOSFET. For applications with higher VIN
voltages (≥24V) a lower CRSS is more important than a
low RDS(ON).
Catch Diode Selection
The catch diode D1 carries load current during the switch
off time. Important parameters for the catch diode includes
peak repetitive reverse voltage (VRRM), forward voltage
(VF), and maximum average forward current (IF(AV)). The
diode VRRM specification should exceed the maximum
reverse voltage across it, i.e., VIN(MAX). A fast switching
schottky diode with lower VF should be used to yield lower
power loss and higher efficiency.
In continuous conduction mode, the average current
conducted by the catch diode is calculated as:
I D(AVG) =I OUT • (1–D)
The worst-case condition for the diode is when VOUT is
shorted to ground with maximum VIN and maximum IOUT
at present. In this case, the diode must safely conduct
the maximum load current almost 100% of the time. To
improve efficiency and to provide adequate margin for
short circuit operation, a schottky diode rated to at least
the maximum output current is recommended.
CIN, CVCC, and CCAP Capacitor Selection
A local input bypass capacitor CIN is required for buck
converters because the input current is pulsed with fast
rise and fall times. The input capacitor selection criteria are
based on the voltage rating, bulk capacitance, and RMS
current capability. The capacitor voltage rating must be
greater than VIN(MAX). The bulk capacitance determines the
input supply ripple voltage and the RMS current capability
is used to keep from overheating the capacitor.
3746fa
For more information www.linear.com/3746
21
LT3746
Applications Information
The bulk capacitance is calculated based on maximum
input ripple, ∆VIN:
C IN =
D MAX • I OUT(MAX)
ΔVIN • f SW
∆VIN is typically chosen at a level acceptable to the user.
100mV is a good starting point. For ceramic capacitors,
only X5R or X7R type should be used because they retain
their capacitance over wider voltage and temperature
ranges than other types such as Y5V or Z5U. Aluminum
electrolytic capacitors are a good choice for high voltage,
bulk capacitance due to their high capacitance per unit
area.
The capacitor RMS current is:
I CIN(RMS) = I OUT •
VOUT •( VIN – VOUT )
VIN2
If applicable, calculate at the worst case condition,
VIN=2 • VOUT. The capacitor RMS current rating specified by the manufacturer should exceed the calculated
ICIN(RMS). Due to their low ESR, ceramic capacitors are
a good choice for high voltage, high RMS current handling. Note that the ripple current ratings from aluminum
electrolytic capacitor manufacturers are based on 2000
hours of life. This makes it advisable to further derate
the capacitor or to choose a capacitor rated at a higher
temperature than required.
For a larger high voltage capacitor value, the combination
of aluminum electrolytic capacitors and ceramic capacitors
is an economical approach. Multiple capacitors may also
be paralleled to meet size or height requirements in the
design. Locate the capacitor very close to the MOSFET
switch and the catch diode, and use short, wide PCB traces
to minimize parasitic inductance.
The general discussion above also applies to the capacitor
CVCC at the VCC pin and the capacitor CCAP between the VIN
and CAP pins. Typically, a 10µF 10V-rated ceramic capacitor for CVCC and a 0.47µF 16V-rated ceramic capacitor for
CCAP should be sufficient.
22
COUT Capacitor Selection
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LT3746 to produce the DC output containing a controlled voltage ripple. It also stores energy to satisfy load
transients and to stabilize the dual-loop operation. Thus
the selection criteria for COUT are based on the voltage
rating, the equivalent series resistance ESR, and the bulk
capacitance. As always, choose the COUT with a voltage
rating greater than VOUT(MAX).
The LT3746 utilizes the output as the dominant pole to stabilize the dual loop operation, so the COUT value determines
the unity gain frequency fUGF, which is set around 1/10 of
the switching frequency. To stabilize the FB loop during the
startup and precharging phases and the LED loop during
the tracking phase, a low-ESR capacitor (tens of mΩ)
should be used and its minimum COUT is calculated as:

 0.25
1.5

C OUT = MAX
,

R
V
•
f
•
R
•
f
S
UGF
OUT(MAX)
S
UGF


The adaptive-tracking-plus-precharging technique moves
the VOUT with the grayscale PWM dimming frequency to
improve system efficiency, choosing a ceramic capacitor
as the COUT inevitably generates acoustic noise due to the
piezo effect of the ceramic material. In an acoustic noise
sensitive application, low ESR tantalum or aluminum
capacitors are preferred. When choosing a capacitor,
look carefully through the data sheet to find out what the
actual capacitance is under operating conditions (applied
voltage and temperature). A physically larger capacitor, or
one with a higher voltage rating, may be required.
Undervoltage Lockout (UVLO) and Shutdown
LT3746 has three UVLO thresholds with hysteresis for
the EN/UVLO, VCC, and CAP pins. The part will remain in
UVLO mode not switching until all the EN/UVLO, VCC, and
(VIN - VCAP) voltages pass their respective typical thresholds (1.31V, 2.89V, and 4.9V). As shown in Figure 6, the
EN/UVLO pin can be controlled in two different ways. The
EN/UVLO pin can accept a digital input signal to enable or
disable the chip. Tie to 0.35V or lower to shut down the
chip or tie to 1.34V or higher for normal operation. This
3746fa
For more information www.linear.com/3746
LT3746
Applications Information
pin can also be connected to a resistor divider between VIN
and ground to program a power input VIN UVLO threshold.
After RUV1 is selected, RUV2 can be calculated by:
Ê VIN(ON) ˆ
R UV2 = R UV1 • Á
– 1˜
Ë 1.3V
¯
FROM µCONTROLLER
VIN
VCC
VIN
RUV2
VCC
EN/UVLO
EN/UVLO
RUV1
where VIN(ON) is the power input voltage above which the
part goes into normal operation. It is important to check
the EN/UVLO pin voltage not to exceed its 6V absolute
maximum rating:
R UV1
VIN(MAX) •
< 6V
R UV1+R UV2
(A)
3746 F06
(B)
Figure 6. Methods of Controlling the EN/UVLO Pin
ILED(NOM) must be set between 4mA and 20mA. Typical
RISET resistor values for various nominal LED currents
are listed in Table 3.
Table 3. Nominal LED Current ILED(NOM) vs. RISET Value
Soft-Start
During soft-start, the SS pin voltage smoothly ramps up
inductor current and output voltage. The effective voltage
range of SS pin is from 0V to 1V. Therefore, the typical
soft-start period is:
RISET * (kΩ)
4
301
10
121
15
80.6
20
60.4
Setting Dot Correction
where CSS is the capacitor connected at SS pin and
12µA is the soft-start charge current. Whenever a UVLO
or thermal shutdown occurs, the SS pin will be discharged
and the part will stop switching until the UVLO event has
disappeared and the SS pin has reached it reset threshold,
0.35V. The part then initiates a new soft-start cycle.
Setting Nominal LED Current
The nominal LED current is defined as the average LED
current across 32-channel when all the individual dot correction registers are set to 0x20. The nominal LED current
is programmed by a single resistor, RISET, between the
ISET pin and ground. The voltage at the ISET pin, VISET,
is trimmed to an accurate 1.205V, generating a current
inversely proportional to RISET. The nominal LED current,
ILED(NOM), can be calculated as:
VISET
•1000
R ISET
ILED(NOM) (mA)
* Recommend 1% Standard Values
C •1V
t SS = SS
12µA
ILED(NOM) =
VIN
The LT3746 can adjust the LED current for each channel
independently. This fine current adjustment, also called
dot correction, is mainly used to calibrate the brightness
deviation between LED channels. The 6-bit (64 steps) dot
correction setting adjusts each LED current from 0.5X to
1.5X of the nominal LED current according to:
 DC + 32 
ILEDn = ILED(NOM) •  n

 64 
where ILEDn is the nth LED current and DCn is the nth
programmed dot correction setting (DCn = 0 to 63). The
fine current step over the nominal LED current gives an
excellent resolution:
ΔILED
ILED(NON)
=
1
≈ 1.56%
64
which enhances the relative LED current match accuracy
if used as calibration.
3746fa
For more information www.linear.com/3746
23
LT3746
Applications Information
Setting Grayscale
Although adjusting the LED current changes its luminous
intensity, or brightness, it will also affect the color matching between LED channels by shifting the chromaticity
coordinate. The best way to adjust the brightness is to
control the amount of LED on/off time by pulse width
modulation (PWM).
The LT3746 can adjust the brightness for each channel
independently. The 12-bit grayscale PWM dimming results
in 4096 linear brightness steps from 0% to 99.98%. The
brightness level GSn% for channel n can be calculated as:
GS n
GS n% =
•100%
4096
where GSn is the nth programmed grayscale setting
(GSn = 0 to 4095).
Open/Short LED Fault
The LT3746 has individual LED fault diagnostic circuitry that
detects both open and short LED faults for each channel.
The open LED fault is defined as any LED string is open
or disconnected from the circuit; and the short LED fault
is defined as any LED string is shorted across itself. The
open LED flag is set if the LED pin voltage is lower than
0.1V (typical) during on status with initial 500ns blanking.
The short LED flag is set if the LED pin voltage is higher
than 75% of the LED bus voltage VOUT any time. If one
LED channel is shorted across itself, the channel will be
turned off to eliminate unnecessary power dissipation.
The function can also be used to disable LED channels
by connecting their LED pins to the output directly. Both
the open and short LED flags are combined to set the LED
fault bits (S0 to S31) in the status frame to 1.
Thermal Protection
The LT3746 has two over temperature thresholds: one
is the fixed internal thermal shutdown and the other one
is programmed by a resistor, RTSET, between the TSET
pin and ground. When the junction temperature exceeds
165°C, the part will enter thermal shutdown mode, shut
down serial data interface, turn off LED channels, and stop
switching. After the junction temperature drops below
155°C, the part will initiate a new soft start.
24
When the RTSET is placed at the TSET pin, a current equal
to the current flowing through the RISET passes the
RTSET, generating a voltage V TSET at the TSET pin, which
is calculated as:
VTSET = 1.205V •
R TSET
R ISET
Then the V TSET is compared to an internal proportionalto-absolute-temperature voltage VPTAT,
VPTAT = 1.72mV •(TJ + 273.15)
where TJ is the LT3746 junction temperature in °C. When
VPTAT is higher than V TSET, an overtemperature flag
OT = 1 is set. Once the RTSET programmed temperature is
exceeded, the part will also gradually derate the nominal
LED current ILED(NOM) to limit the total power dissipation
without interrupting its normal operation.
Cascading Devices and Determining Serial Data
Interface Clock
In a large LCD backlighting or LED display system, multiple LT3746 chips can be easily cascaded to drive all the
LED strings. The LT3746 adopts a 6-wire topology, which
balances the internal clock skew and matches the external
trace capacitance with an easy PCB layout.
The minimum serial data interface clock frequency fSCKI
for a large display system can be calculated as:
f SCKI = N LT3746 • 386 • f REFRESH
where NLT3746 is the number of LT3746 chips and fREFRESH
is the refresh rate of the whole system.
Calculating Power Dissipation
The total power dissipation inside the chip can be calculated as:
P TOTAL =
31
V IN•(I VIN+ f SW •Q G)+ V CC •I VCC + ∑ GS n% •I LEDn • VLEDn
For more information www.linear.com/3746
n=0
3746fa
LT3746
Applications Information
where IVIN is the power input VIN quiescent current, IVCC
is the VCC supply current, and VLEDn is the LED pin voltage for channel n.
Keep TJ below the maximum operating junction temperature 125°C.
From the total power dissipation PTOTAL, the junction
temperature TJ can be calculated as:
TJ = T A +PTOTAL • θ JA
Typical Application
VIN
10V TO 30V
0.47µF
16V
VIN
EN/UVLO
EN
VCC
3V TO 5.5V
CAP
GATE
100k
VCC
D1
SYNC
RT
105k
SS
409.6kHz CLOCK
4V MAXIMUM OUTPUT VOLTAGE
33mΩ
23.2k
GND
LT3746
10nF
ISP
C1
220µF
10k
ISN
FB
ISET
60.4k
M1 L1
22µH
.
..
10µF
10V
4.7µF
50V
TSET
32.4k
LED00
LED01
LED02
PWMCK
LED03
LED04
LED05
..
.
LED26
LED27
LED28
LED29
LED30
LED31
TTL/CMOS
SCKI
SCKO
SDI
SDO
LDI
LDO
TTL/CMOS
3746 TA02
M1: VISHAY Si9407BDY
D1: DIODES DFLS160
L1: WÜRTH ELECTRONIK 7447779122
C1: SANYO 6TPE220MI
Figure 7. 32-Channel LED Driver, 500kHz Buck, 1 LED 10mA to 30mA per Channel, 100Hz 12-Bit Dimming
3746fa
For more information www.linear.com/3746
25
LT3746
Package Description
UHH Package
UHH Package
56-Lead
Plastic
QFN (5mm × 9mm)
56-Lead Plastic QFN (5mm × 9mm)
(Reference
LTCLTC
DWG
# 05-08-1727
Rev Rev
A) A)
(Reference
DWG
# 05-08-1727
0.70 ± 0.05
5.50 ± 0.05
(2 SIDES)
4.10 ± 0.05
(2 SIDES)
3.60 REF
(2 SIDES)
3.45 ±0.05
7.13 ±0.05
PACKAGE
OUTLINE
0.20 ± 0.05
0.40 BSC
6.80 REF (2 SIDES)
8.10 ± 0.05 (2 SIDES)
9.50 ± 0.05 (2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 ± 0.05
5.00 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.60 REF
55 56
0.00 – 0.05
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
9.00 ± 0.10
(2 SIDES)
6.80 REF
7.13 ±0.10
3.45 ±0.10
(UH) QFN 0406 REV A
0.200 REF
0.200 REF
0.00 – 0.05
0.75 ± 0.05
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
26
0.20 ± 0.05
R = 0.115
TYP
0.40 BSC
BOTTOM VIEW—EXPOSED PAD
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3746fa
For more information www.linear.com/3746
LT3746
Revision History
REV
DATE
DESCRIPTION
A
04/13
Clarified fOSC and IVCC specifications
PAGE NUMBER
3
Clarified ILED, Line/Load delta specifications
4
Clarified Table 1 Equations
5
Clarified FB Pin description
11
3746fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaForofmore
information
www.linear.com/3746
tion that the interconnection
its circuits
as described
herein will not infringe on existing patent rights.
27
LT3746
Typical Application
VIN
13V TO 42V
0.47µF
16V
VIN
EN
VCC
3V TO 5.5V
CAP
GATE
EN/UVLO
100k
D1
SYNC
SS
80.6k
GND
LT3746
10nF
ISP
C1
2 × 47µF
10k
ISN
FB
ISET
LED00
TSET
LED01
32.4k
2.048MHz CLOCK
11V MAXIMUM OUTPUT VOLTAGE
33mΩ
.
..
RT
60.4k
M1 L1
22µH
VCC
10µF
10V
46.4k
4.7µF
50V
LED02
..
.
PWMCK
LED29
LED30
LED31
TTL/CMOS
SCKI
SCKO
SDI
SDO
LDI
TTL/CMOS
LDO
M1: VISHAY Si9407BDY
D1: DIODES DFLS160
L1: WÜRTH ELECTRONIK 7447779122
C1: SANYO 16TQC47M
3746 TA03
Figure 8. 32-Channel LED Driver, 1MHz Buck, 3 LEDs 10mA to 30mA per Channel, 500Hz 12-Bit Dimming
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LT3476
Quad Output 1.5A, 2MHz High Current LED Driver with
1,000:1 Dimming
VIN: 2.8V to 16V, VOUT(MAX) = 36, True Color PWM Dimming = 1000:1,
ISD < 10µA, 5mm × 7mm QFN-10 Package
LT3486
Dual 1.3A , 2MHz High Current LED Driver
VIN: 2.5V to 24V, VOUT(MAX) = 36, True Color PWM Dimming = 1000:1,
ISD < 1µA, 5mm × 3mm DFN-16 TSSOP-16E Package
LT3496
Triple Output 750mA, 2.1 MHz High Current LED Driver
with 3,000:1 Dimming
VIN: 3V to 30V, VOUT(MAX) = 60, True Color PWM Dimming = 3000:1,
ISD < 1µA, 4mm × 5mm QFN-28 Package
LT3595
45V, 2.5MHz 16-Channel Full Featured LED Driver
VIN: 4.5V to 45V, VOUT(MAX) = 45, True Color PWM Dimming = 5000:1,
ISD < 1µA, 5mm × 9mm QFN-56 Package
LT3598
44V, 1.5A, 2.5MHz Boost 6-Channel 30mA LED Driver
VIN: 3V to 40V, VOUT(MAX) = 44, True Color PWM Dimming = 1000:1,
ISD < 1µA, 4mm × 4mm QFN-24 Package
LT3599
44V, 2A, 2.5MHz Boost 4-Channel 120mA LED Driver
VIN: 3V to 40V, VOUT(MAX) = 44, True Color PWM Dimming = 1000:1,
ISD < 1µA, 4mm × 4mm QFN-24 Package
LT3754
60V, 1MHz Boost 16-Channel 50mA LED Driver with True
Color 3,000:1 PWM Dimming and 2.8% Current Matching
VIN: 4.5V to 40V, VOUT(MAX) = 60, True Color PWM Dimming = 3000:1,
ISD < 1µA, 5mm × 5mm QFN-32 Package
LT3755/
LT3755-1
High Side 40V, 1MHz LED Controller with True Color
3,000:1 PWM Dimming
VIN: 4.5V to 40V, VOUT(MAX) = 60, True Color PWM Dimming = 3000:1,
ISD < 1µA, 3mm × 3mm QFN-16 MSOP-16E Package
LT3756/
LT3756-1
High Side 100V, 1MHz LED Controller with True Color
3,000:1 PWM Dimming
VIN: 6V to 100V, VOUT(MAX) = 100, True Color PWM Dimming = 3000:1,
ISD < 1µA, 3mm × 3mm QFN-16 MSOP-16E Package
LT3760
60V, 1MHz Boost 8-Channel 100mA LED Driver with True
Color 3,000:1 PWM Dimming and 2.8% Current Matching
VIN: 4.5V to 40V, VOUT(MAX) = 60, True Color PWM Dimming = 3000:1,
ISD < 1µA, TSSOP-28E Package
28 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/3746
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/3746
3746fa
LT 0413 REV A • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2011