ISSI IS41C16128-35TI 128k x 16 (2-mbit) dynamic ram with edo page mode Datasheet

ISSI®
ISSI
IS41C16128
IS41C16128
128K x 16 (2-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
®
AUGUST 1998
FEATURES
DESCRIPTION
• Extended Data-Out (EDO) Page Mode
access cycle
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode : RAS-Only, CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single +5V ± 10% power supply
• Byte Write and Byte Read operation via two CAS
• Available in 40-pin SOJ and TSOP (Type II)
• Industrial temperature available
The ISSI IS41C16128 is a 131,072 x 16-bit high-performance
CMOS Dynamic Random Access Memory. The IS41C16128
offers an accelerated cycle access called EDO Page Mode.
EDO Page Mode allows 256 random accesses within a
single row with access cycle time as short as 12 ns per 16bit word. The Byte Write control, of upper and lower byte,
makes the IS41C16128 ideal for use in 16-, 32-bit wide data
bus systems.
These features make the IS41C16128 ideally suited for
high band-width graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The IS41C16128 is packaged in a 40-pin 400-mil SOJ and
TSOP (Type II).
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
CAS
WE
OE
CONTROL
LOGIC
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
ADDRESS
BUFFERS
A0-A8
ROW DECODER
REFRESH
COUNTER
MEMORY ARRAY
131,072 x 16
DATA I/O BUFFERS
RAS
CLOCK
GENERATOR
RAS
RAS
I/O0-I/O15
This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We
assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
1
ISSI
IS41C16128
®
KEY TIMING PARAMETERS
Parameter
-35
-40
-45
-50
-60
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. EDO Page Mode Cycle Time (tPC)
35 ns
10 ns
18 ns
12 ns
40 ns
12 ns
20 ns
15 ns
45 ns
13 ns
22 ns
17 ns
50 ns
14 ns
25 ns
20 ns
60 ns
15 ns
30 ns
25 ns
Min. Read/Write Cycle Time (tRC)
60 ns
75 ns
80 ns
90 ns
110 ns
PIN CONFIGURATIONS
40-Pin TSOP (Type II)
40-Pin SOJ
VCC
1
40
GND
I/O0
2
39
I/O15
VCC
1
40
GND
I/O1
3
38
I/O14
I/O0
2
39
I/O15
I/O2
4
37
I/O13
I/O1
3
38
I/O14
I/O3
5
36
I/O12
I/O2
4
37
I/O13
GND
I/O3
5
36
I/O12
6
35
GND
VCC
6
35
I/O4
7
34
I/O11
VCC
I/O5
8
33
I/O10
I/O4
7
34
I/O11
I/O6
9
32
I/O9
I/O5
8
33
I/O10
I/O7
10
31
I/O8
I/O6
9
32
I/O9
I/O7
10
31
I/O8
NC
11
30
NC
NC
12
29
LCAS
WE
13
28
UCAS
RAS
14
27
OE
NC
15
26
A8
A0
16
25
A7
A1
17
24
A6
18
23
A5
NC
11
30
NC
NC
12
29
LCAS
WE
13
28
UCAS
RAS
14
27
OE
NC
15
26
A8
A0
16
25
A7
17
24
A2
18
23
A5
A2
A3
19
22
A4
A3
19
22
A4
VCC
20
21
GND
VCC
20
21
GND
A1
A6
PIN DESCRIPTIONS
A0-A8
Address Inputs
I/O0-15
Data Inputs/Outputs
WE
OE
RAS
UCAS
LCAS
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Vcc
Power
GND
Ground
NC
No Connection
2
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
ISSI
IS41C16128
®
TRUTH TABLE
RAS
Function
Standby
Read: Word
Read: Lower Byte
LCAS UCAS
WE
OE
H
L
L
H
L
L
H
L
H
X
H
H
X
L
L
Address tR/tC
X
ROW/COL
ROW/COL
Read: Upper Byte
L
H
L
H
L
ROW/COL
Write: Word (Early Write)
Write: Lower Byte (Early Write)
L
L
L
L
L
H
L
L
X
X
ROW/COL
ROW/COL
Write: Upper Byte (Early Write)
L
H
L
L
X
ROW/COL
L
H→L
H→L
L→H
H→L
H→L
H→L
H→L
L
L
H
L
L
H→L
H→L
L→H
H→L
H→L
H→L
H→L
L
L
H
L
H→L
H
H
H
L
L
H→L
H→L
H
L
X
X
L→H
L
L
L
X
X
L→H
L→H
L
X
X
X
ROW/COL
ROW/COL
NA/COL
NA/NA
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
ROW/COL
ROW/NA
X
Read-Write(1,2)
EDO Page-Mode Read(2)
EDO Page-Mode Write(1)
EDO Page-Mode
Read-Write(1,2)
Hidden Refresh2)
RAS-Only Refresh
CBR Refresh(3)
L
1st Cycle:
L
2nd Cycle:
L
Any Cycle:
L
1st Cycle:
L
2nd Cycle:
L
1st Cycle:
L
2nd Cycle:
L
Read L→H→L
Write L→H→L
L
H→L
I/O
High-Z
DOUT
Lower Byte, DOUT
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DOUT
DIN
Lower Byte, DIN
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DIN
DOUT, DIN
DOUT
DOUT
DOUT
DIN
DIN
DOUT, DIN
DOUT, DIN
DOUT
DOUT
High-Z
High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
3
ISSI
IS41C16128
Functional Description
The IS41C16128 is a CMOS DRAM optimized for highspeed bandwidth, low power applications. During READ
or WRITE cycles, each bit is uniquely addressed through
the 17 address bits. The row address is latched by the
Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS). RAS is
used to latch the first nine bits and CAS is used to latch the
latter nine bits.
The IS41C16128 has two CAS controls, LCAS and UCAS.
The LCAS and UCAS inputs internally generates a CAS
signal functioning in an identical manner to the single CAS
input on the other 128K x 16 DRAMs. The key difference
is that each CAS controls its corresponding I/O tristate
logic (in conjunction with OE and WE and RAS). LCAS
controls I/O0 through I/O7 and UCAS controls I/O8
through I/O15.
The IS41C16128 CAS function is determined by the first
CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41C16128 both BYTE READ and BYTE WRITE cycle
capabilities.
®
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory.
1. By clocking each of the 512 row addresses (A0 through
A8) with RAS at least once every 8 ms. Any read, write,
read-modify-write or RAS-only cycle refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 256 columns within
a selected row to be randomly accessed at a high data
rate.
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
Read Cycle
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
Memory Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
4
The EDO page mode allows both read and write operations during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
ISSI
IS41C16128
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
VT
VCC
IOUT
PD
TA
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Operation Temperature
Com.
Ind.
Storage Temperature
TSTG
Rating
Unit
–1.0 to +7.0
–1.0 to +7.0
50
1
0 to +70
–40 to +85
–55 to +125
V
V
mA
W
°C
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
VCC
VIH
VIL
TA
Parameter
Min.
Typ.
Max.
Unit
Supply Voltage
Input High Voltage
Input Low Voltage
Ambient Temperature
4.5
2.4
–1.0
0
–40
5.0
—
—
—
—
5.5
VCC + 1.0
+0.8
+70
+85
V
V
V
°C
Com.
Ind.
CAPACITANCE(1,2)
Symbol
Parameter
CIN1
CIN2
CIO
Input Capacitance: A0-A8
Input Capacitance: RAS, UCAS, LCAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O15
Max.
Unit
5
7
7
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V + 10%.
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
5
ISSI
IS41C16128
®
ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
IIL
Input Leakage Current
IIO
Output Leakage Current
VOH
VOL
Output High Voltage Level
Output Low Voltage Level
Any input 0V < VIN < 5.5V
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V < VOUT < 5.5V
IOH = –2.5 mA
IOL = +2.1 mA
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
Stand-by Current: TTL
RAS, LCAS, UCAS ≥ VIH
Stand-by Current: CMOS
RAS, LCAS, UCAS ≥ VCC – 0.2V
Operating Current:
RAS, LCAS, UCAS,
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
Operating Current:
RAS = VIL, LCAS, UCAS,
EDO Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
Refresh Current:
RAS Cycling, LCAS, UCAS ≥ VIH
RAS-Only(2,3)
tRC = tRC (min.)
Average Power Supply Current
Refresh Current:
RAS, LCAS, UCAS Cycling
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
Speed
-35
-40
-45
-50
-60
-35
-40
-45
-50
-60
-35
-40
-45
-50
-60
-35
-40
-45
-50
-60
Min.
Max.
Unit
–10
10
µA
–10
10
µA
2.4
—
—
0.4
V
V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
1
230
130
120
110
100
220
90
85
80
70
230
130
120
100
100
230
130
120
100
100
mA
mA
mA
mA
mA
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
ISSI
IS41C16128
®
AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
tRC
tRAC
tCAC
tAA
tRAS
tRP
tCAS
tCP
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
RAS Precharge Time
CAS Pulse Width(26)
CAS Precharge Time(9, 25)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
Column-Address Hold Time
(referenced to RAS)
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time(27)
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 28, 29)
Output Enable Time(15, 16)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
Read Command Hold Time
(referenced to RAS)(12)
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17, 27)
Write Command Hold Time
(referenced to RAS)(17)
Write Command Pulse Width(17)
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
tRAD
tRAL
tRPC
tRSH
tCLZ
tCRP
tOD
tOE
tOEHC
tOEP
tOES
tRCS
tRRH
tRCH
tWCH
tWCR
tWP
tWPZ
tRWL
tCWL
tWCS
tDHR
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
-35
Min. Max.
-40
Min. Max.
-45
Min. Max.
-50
Min. Max.
-60
Min. Max.
Units
60
—
—
—
35
20
6
5
35
11
0
6
0
6
30
—
35
10
18
10K
—
10K
—
—
28
—
—
—
—
—
75
—
—
—
40
25
6
5
40
17
0
6
0
6
30
—
40
12
20
10K
—
10K
—
—
28
—
—
—
—
—
80
—
—
—
45
25
7
7
45
18
0
7
0
7
35
—
45
13
22
10K
—
10K
—
—
32
—
—
—
—
—
90
—
—
—
50
30
8
8
50
19
0
8
0
8
40
—
50
14
25
10K
—
10K
—
—
36
—
—
—
—
—
110
—
—
—
60
40
10
10
60
20
0
10
0
10
40
—
60
15
30
10K
—
10K
—
—
45
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
18
0
8
3
5
3
—
10
10
5
0
0
20
—
—
—
—
—
15
10
—
—
—
—
—
12
20
0
12
3
5
3
—
10
10
5
0
0
20
—
—
—
—
—
15
10
—
—
—
—
—
13
22
0
13
3
5
3
—
10
10
5
0
0
22
—
—
—
—
—
15
12
—
—
—
—
—
14
25
0
14
3
5
3
—
10
10
5
0
0
25
—
—
—
—
—
15
15
—
—
—
—
—
15
30
0
15
3
5
3
—
10
10
5
0
0
30
—
—
—
—
—
15
15
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
—
0
—
0
—
0
—
0
—
ns
5
30
—
—
6
30
—
—
7
35
—
—
8
40
—
—
10
50
—
—
ns
ns
5
10
8
8
0
30
—
—
—
—
—
—
6
10
12
12
0
30
—
—
—
—
—
—
7
10
13
13
0
35
—
—
—
—
—
—
8
10
14
14
0
40
—
—
—
—
—
—
10
10
15
15
0
40
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
7
ISSI
IS41C16128
®
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.)
Symbol
tACH
tOEH
tDS
tDH
tRWC
tRWD
tCWD
tAWD
tPC
tRASP
tCPA
tPRWC
tCOH
tOFF
tWHZ
tCLCH
tCSR
tCHR
tORD
tREF
tT
8
Parameter
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
OE Hold Time from WE during
READ-MODIFY-WRITE cycle(18)
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
EDO Page Mode READ or WRITE
Cycle Time(24)
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
EDO Page Mode READ-WRITE
Cycle Time(24)
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 29)
Output Disable Delay from WE
Last CAS going LOW to First CAS
returning HIGH(23)
CAS Setup Time (CBR REFRESH)(30, 20)
CAS Hold Time (CBR REFRESH)(30, 21)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
Refresh Period (512 Cycles)
Transition Time (Rise or Fall)(2, 3)
-35
Min. Max.
-40
Min. Max.
-45
Min. Max.
-50
Min. Max.
-60
Min. Max.
Units
15
—
15
—
15
—
15
—
15
—
ns
8
—
8
—
8
—
10
—
15
—
ns
0
6
80
45
—
—
—
—
0
6
100
50
—
—
—
—
0
7
115
60
—
—
—
—
0
8
125
70
—
—
—
—
0
10
140
80
—
—
—
—
ns
ns
ns
ns
25
30
12
—
—
—
30
30
15
—
—
—
32
40
17
—
—
—
34
42
20
—
—
—
36
49
25
—
—
—
ns
ns
ns
35
—
40
100K
21
—
40
—
45
100K
23
—
45
—
46
100K
25
—
50
—
47
100K
27
—
60
—
56
100K
34
—
ns
ns
ns
3
3
—
15
3
3
—
15
3
3
—
15
3
3
—
15
3
3
—
15
ns
ns
3
10
15
—
3
10
15
—
3
10
15
—
3
10
15
—
3
10
15
—
ns
ns
8
8
0
—
—
—
10
10
0
—
—
—
10
10
0
—
—
—
10
10
0
—
—
—
10
10
0
—
—
—
ns
ns
ns
—
1
8
50
—
1
8
50
—
1
8
50
—
1
8
50
—
1
8
50
ms
ns
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
IS41C16128
ISSI
®
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by
the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≥ tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD
(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
9
ISSI
IS41C16128
®
READ CYCLE
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
tRRH
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tASC
Row
Column
Row
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLZ
I/O
tOFF(1)
Open
Open
Valid Data
tOE
tOD
OE
tOES
Undefined
Don't Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
10
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
ISSI
IS41C16128
®
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
UCAS/LCAS
tAR
tRAD
tRAH
tASR
ADDRESS
tRAL
tCAH
tACH
tASC
Row
Column
Row
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE
tDS
I/O
tDH
Valid Data
Don't Care
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
11
ISSI
IS41C16128
®
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
UCAS/LCAS
tAR
tRAD
tASR
tRAH
tRAL
tCAH
tASC
tACH
ADDRESS
Row
Column
Row
tRWD
tCWL
tRWL
tCWD
tAWD
tRCS
tWP
WE
tAA
tRAC
tCAC
tCLZ
I/O
tDS
Open
Valid DOUT
tOE
tDH
Open
Valid DIN
tOD
tOEH
OE
Undefined
Don't Care
12
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
ISSI
IS41C16128
®
EDO-PAGE-MODE READ CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tPC(1)
tCAS,
tCLCH
tRCD
tCAS,
tCLCH
tCP
tCP
tRSH
tCAS,
tCLCH
tCP
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tASC
tCAH tASC
Row
Column
tRAL
tCAH
tCAH tASC
Column
Column
Row
tRAH
tRRH
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLZ
I/O
Open
tAA
tCPA
tCAC
tCOH
Valid Data
tOE
tOES
tAA
tCPA
tCAC
tCLZ
tOFF
Valid Data
tOEHC
Valid Data
Open
tOE
tOD
tOES
tOD
OE
tOEP
Undefined
Don't Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
13
ISSI
IS41C16128
®
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tPC
tCAS,
tCLCH
tRCD
tCP
tCAS,
tCLCH
tCP
tRSH
tCAS,
tCLCH
tCP
UCAS/LCAS
tAR
tACH
tCAH tASC
tRAD
tASR
ADDRESS
tASC
Row
Column
tRAH
tACH
tRAL
tCAH
tACH
tCAH tASC
Column
tCWL
tWCS
Column
tCWL
tWCS
tWCH
tCWL
tWCS
tWCH
tWCH
tWP
tWP
Row
tWP
WE
tWCR
tDHR
tRWL
tDS
tDS
tDH
I/O
Valid Data
tDS
tDH
Valid Data
tDH
Valid Data
OE
Don't Care
14
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
ISSI
IS41C16128
®
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
tRASP
tRP
RAS
tCSH
tCRP
tCAS, tCLCH
tRCD
tCP
tPC / tPRWC(1)
tCAS, tCLCH
tRSH
tCAS, tCLCH
tCP
tCP
UCAS/LCAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
tCAH
Row
tASC
tCAH
Column
tRWD
tRCS
tRAL
tCAH
tASC
Column
tCWL
tWP
Column
tRWL
tCWL
tWP
tCWL
tWP
tAWD
tCWD
Row
tAWD
tCWD
tAWD
tCWD
WE
tAA
tAA
tCPA
tDH
tDS
tRAC
tCAC
tCLZ
I/O
Open
tCAC
tCLZ
DOUT
DIN
DIN
DOUT
tOD
tOE
tDH
tDS
tCAC
tCLZ
DOUT
tOD
tOE
tAA
tCPA
tDH
tDS
Open
DIN
tOD
tOE
tOEH
OE
Undefined
Don't Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
15
ISSI
IS41C16128
®
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
tRASP
tRP
RAS
tCSH
tPC
tPC
tCRP
tCAS
tRCD
tCAS
tCP
tRSH
tCAS
tCP
tCP
UCAS/LCAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
Row
tCAH
tASC
tCAH
Column (A)
tASC
Column (B)
tRCS
tACH
tRAL
tCAH
Column (N)
Row
tRCH
tWCS
tWCH
WE
tAA
tRAC
tCAC
I/O
Open
tCPA
tCAC
tCOH
Valid Data (A)
tAA
tWHZ
tDS
Valid Data (B)
tDH
DIN
Open
tOE
OE
Don't Care
16
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
ISSI
IS41C16128
®
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
tCSH
tCRP
tRCD
tCP
tCAS
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tRAH
tCAH
tASC
Row
tASC
Column
Column
tRCS
tRCH
tRCS
WE
tAA
tWPZ
tRAC
tCAC
tCLZ
Open
I/O
tWHZ
tCLZ
Valid Data
Open
tOE
tOD
OE
Undefined
Don't Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCRP
tRPC
UCAS/LCAS
tASR
ADDRESS
I/O
tRAH
Row
Row
Open
Don't Care
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
17
ISSI
IS41C16128
®
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tCHR
tRPC
tCP
tCHR
tRPC
tCSR
tCSR
UCAS/LCAS
Open
I/O
HIDDEN REFRESH CYCLE (WE = HIGH; OE = LOW)(1)
tRAS
tRP
tRAS
RAS
tCRP
tRCD
tRSH
tCHR
UCAS/LCAS
tAR
tRAD
tRAH tASC
tASR
ADDRESS
Row
tRAL
tCAH
Column
tAA
tRAC
tOFF(2)
tCAC
tCLZ
I/O
Open
Open
Valid Data
tOE
tOD
tORD
OE
Undefined
Don't Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
18
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
ISSI
IS41C16128
®
400-MIL PLASTIC SOJ
Package Code: K
N
E1
1
E
SEATING PLANE
D
b
A
C
A2
e
400-mil Plastic SOJ (K)
Inches
Millimeters
Symbol Min Max
Min Max
Ref. Std.
N
40
A
— 0.144
—
3.66
A1
0.025 —
0.66
—
A2
0.082 —
2.08
—
B
0.015 0.019
0.38 0.48
b
0.026 0.032
0.66 0.81
C
0.007 0.013
0.18 0.33
D
1.020 1.030
25.91 26.16
E
0.430 0.450
10.92 11.43
E1
0.395 0.405
10.03 10.28
E2
0.346 0.386
8.79 9.80
e
0.050 BSC
1.27 BSC
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
B
A1
E2
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the
package.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
19
ISSI
IS41C16128
®
PLASTIC TSOP
Package Code: T (Type 2)
N
N/2+1
H
E
1
N/2
D
SEATING PLANE
A
e
Plastic TSOP (T - Type II)
Inches
Millimeters
Symbol Min Max
Min Max
Ref. Std.
N
40/44
A
0.039 0.047
1.00 1.20
A1
0.002 0.008
0.05 0.20
B
0.012 0.016
0.30 0.40
C 0.0047 0.0083
0.12 0.21
D
0.721 0.729
18.313 18.517
E
0.462 0.470
11.735 11.938
e
0.0315 BSC
0.800 BSC
H
0.396 0.404
10.058 10.262
L
0.017 0.023
0.432 0.584
α
0°
5°
0°
5°
20
B
L
A1
α
C
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions
and should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
ISSI
IS41C16128
®
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Speed (ns)
35
35
40
40
45
45
50
50
60
60
Order Part No.
Package
IS41C16128-35K
IS41C16128-35T
IS41C16128-40K
IS41C16128-40T
IS41C16128-45K
IS41C16128-45T
IS41C16128-50K
IS41C16128-50T
IS41C16128-60K
IS41C16128-60T
400-mil SOJ
400-mil TSOP (Type 2)
400-mil SOJ
400-mil TSOP (Type 2)
400-mil SOJ
400-mil TSOP (Type 2)
400-mil SOJ
400-mil TSOP (Type 2)
400-mil SOJ
400-mil TSOP (Type 2)
Industrial Range: –40°C to 85°C
Speed (ns)
35
35
40
40
45
45
50
50
60
60
Order Part No.
Package
IS41C16128-35KI
IS41C16128-35TI
IS41C16128-40KI
IS41C16128-40TI
IS41C16128-45KI
IS41C16128-45TI
IS41C16128-50KI
IS41C16128-50TI
IS41C16128-60KI
IS41C16128-60TI
400-mil SOJ
400-mil TSOP (Type 2)
400-mil SOJ
400-mil TSOP (Type 2)
400-mil SOJ
400-mil TSOP (Type 2)
400-mil SOJ
400-mil TSOP (Type 2)
400-mil SOJ
400-mil TSOP (Type 2)
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Fax: (408) 588-0806
Toll Free: 1-800-379-4774
email: [email protected]
http://www.issi.com
Integrated Silicon Solution, Inc.
PRELIMINARY DR002-1D
08/20/98
21