Intersil HM1-6561B/883 256 x 4 cmos ram Datasheet

HM-6561/883
256 x 4 CMOS RAM
March 1997
Features
Description
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high performance and low power operation.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
On-chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays. The data inputs
and outputs are multiplexed internally for common I/O bus
compatibility.
The HM-6561/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
• High Output Drive - 1 TTL Load
• On-Chip Address Registers
• Common Data In/Out
• Three-State Output
• Easy Microprocessor Interfacing
Ordering Information
PACKAGE TEMPERATURE RANGE
CERDIP
-55oC to +125oC
220ns
300ns
HM1-6561B/883
HM1-6561/883
PKG. NO.
F18.3
Pinout
HM-6561/883 (CERDIP)
TOP VIEW
A3
1
18 VCC
A2
2
17 A4
A1
3
16 W
A0
4
15 S1
A5
5
14 DQ3
A6
6
13 DQ2
A7
7
12 DQ1
GND
8
11 DQ0
E
9
10 S2
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
S
Chip Select
DQ
Data In/Out
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-117
File Number
2990.1
HM-6561/883
Functional Diagram
A0
A1
A5
A6
A7
A
LATCHED
ADDRESS
REGISTER
GATED
ROW
DECODER
5
A
32 x 32
MATRIX
32
5
L
G
8
A
8
8
8
G
D
DQ0
A
Q
LATCH
L
A
GATED COLUMN
DECODER
D
DQ1
A
Q
A
Q
LATCH
L
AND DATA I / O
A
D
DQ2
LATCH
L
A
D
DQ3
A
Q
LATCH
3
L
3
A
L
A
LATCHED ADDRESS
REGISTER
W
E
A2
A3
S1
S2
NOTES:
1. All lines positive logic-active high.
2. Three-state Buffers: A high → output active.
3. Data Latches: L high → Q = D and Q latches on falling edge of L.
4. Address Latches and Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
6-118
A4
HM-6561/883
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input or Output Voltage. . . . . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
CERDIP Package . . . . . . . . . . . . . . . . 74oC/W
18oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . VCC - 2.0V to VCC
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
TABLE 1. HM-6561/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
LIMITS
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
Output Low Voltage
VOL
VCC = 4.5V,
IOL = 1.6mA
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
0.4
V
Output High Voltage
VOH
VCC = 4.5V,
IOH = -0.4mA
1, 2, 3
-55oC ≤ TA ≤ +125oC
2.4
-
V
VCC = 5.5V,
VI = GND or VCC
1, 2, 3
-55oC ≤ TA ≤ +125oC
-1.0
+1.0
µA
VCC = 5.5V,
VIO = GND or
VCC
1, 2, 3
-55oC ≤ TA ≤ +125oC
-1.0
+1.0
µA
Input Leakage Current
II
Input/Output Leakage Current
IIOZ
Data Retention Supply Current
ICCDR
VCC = 2.0V,
E = VCC,
IO = 0mA,
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
10
µA
Operating Supply Current
ICCOP
VCC = 5.5V,
(Note 2),
E = 1MHz,
W = GND,
VI = VCC or GND
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
4
mA
Standby Supply Current
ICCSB
VCC = 5.5V,
IO = 0mA,
VI = VCC or GND
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
10
µA
NOTES:
1. All voltages referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
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HM-6561/883
TABLE 2. HM-6561/883 A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
LIMITS
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
GROUP A
SUBGROUPS
HM-6561B/883
HM-6561/883
TEMPERATURE
MIN
MAX
MIN
MAX
UNITS
-
220
-
300
ns
Chip Enable
Access Time
(1) TELQV
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
Address Access
Time
(2) TAVQV
VCC = 4.5 and
5.5V, (Note 3)
9, 10, 11
-55oC ≤ TA ≤ +125oC
-
220
-
300
ns
Chip Select
Output Enable
Time
(3) TSLQX
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
5
-
5
-
ns
Chip Select
Output Disable
Time
(4) TSHQZ
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
-
120
-
150
ns
Chip Enable Pulse
Negative Width
(5) TELEH
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
220
-
300
-
ns
Chip Enable Pulse
Positive Width
(6) TEHEL
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
100
-
100
-
ns
Address Setup
Time
(7) TAVEL
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
0
-
0
-
ns
Address Hold Time
(8) TELAX
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
40
-
50
-
ns
Data Setup Time
(9) TDVWH
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
100
-
150
-
ns
Data Hold Time
(10) TWHDX
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
0
-
0
-
ns
Write Data Delay
Time
(11) TWLDV
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
20
-
30
-
Chip Select Write
Pulse Setup Time
(12) TWLSH
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
120
-
180
-
ns
Chip Enable Write
Pulse Setup Time
(13) TWLEH
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
120
-
180
-
ns
Chip Select Write
Pulse Hold Time
(14) TSLWH
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
120
-
180
-
ns
Chip Enable Write
Pulse Hold Time
(15) TELWH
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
120
-
180
-
ns
Write Enable Pulse
Width
(16) TWLWH
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
120
-
180
-
ns
Read or Write
Cycle Time
(17) TELEL
VCC = 4.5 and
5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
320
-
400
-
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
IOL = 1.6mA, IOH = -0.4mA, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
6-120
HM-6561/883
TABLE 3. HM-6561/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
NOTE
TEMPERATURE
MIN
MAX
UNITS
CI
Input Capacitance
VCC = Open, f = 1MHz,
All Measurements
Referenced to Device
Ground
1
TA = +25oC
-
8
pF
CO
Output Capacitance
VCC = Open, f = 1MHz,
All Measurements
Referenced to Device
Ground
1
TA = +25oC
-
10
pF
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major
process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%/5004
1
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Group A
Samples/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D
Samples/5005
1, 7, 9
Test Load Circuit
DUT
(NOTE 1) CL
IOH
+
-
1.5V
EQUIVALENT CIRCUIT
NOTE:
1. Test head capacitance includes stray and jig capacitance.
6-121
IOL
HM-6561/883
Timing Waveforms
(8)
TELAX
(7) TAVEL
A
(7) TAVEL
VALID
(17) TELEL
(6) TEHEL
(5) TELEH
(6) TEHEL
E
HIGH
W
(1) TELQV
(2) TAVQV
HIGH Z
DQ
HIGH Z
PREVIOUS DATA
VALID DATA LATCHED
(4)
TSHQZ
(4)
TSHQZ
(4)
TSLQX
S1, S2
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 1. READ CYCLE
TRUTH TABLE
INPUTS
OUTPUT
TIME
REFERENCE
E
S1
W
A
DQ
-1
H
H
X
X
Z
Memory Disabled
X
H
V
Z
Cycle Begins, Addresses are Latched
0
FUNCTION
1
L
L
H
X
X
Output Enabled
2
L
L
H
X
V
Output Valid
L
H
X
V
Output Latched
H
X
X
Z
Device Disabled, Prepare for Next Cycle (Same as -1)
X
H
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
3
4
5
H
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
The HM-6561/883 Read Cycle is initiated on the falling edge
of E. This signal latches the input address word into on-chip
registers. Minimum address setup and hold times must be
met. After the required hold time, the address lines may
change state without affecting device operation. In order to
read the output data E, S1 and S2 must be low and W must
be high. The output data will be valid at access time
(TELQV).
The HM-6561/883 has output data latches that are controlled by E. On the rising edge of E the present data is
latched and remains latched until E falls. Either or both S1 or
S2 may be used to force the output buffers into a high
impedance state.
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HM-6561/883
Timing Waveforms (Continued)
(8)
TELAX
(7) TAVEL
A
(7) TAVEL
VALID
NEXT
(17) TELEL
(6) TEHEL
(5) TELEH
(6) TEHEL
E
(13) TWLEH
(15) TELWH
(16) TWLWH
W
(11) TWLDV
(10) TWHDX
(9) TDVWH
VALID DATA
DQ
(14) TSLWH
(12) TWLSH
S1, S2
TIME
REFERENCE
-1
0
1
2
3
4
5
FIGURE 2. WRITE CYCLE
TRUTH TABLE
INPUTS
TIME
REFERENCE
E
S1
W
A
DQ
-1
H
H
X
X
X
Memory Disabled
X
X
V
X
Cycle Begins, Addresses are Latched
L
X
X
Write Period Begins
X
V
Data In is Written
0
1
L
L
2
L
L
3
4
5
H
FUNCTION
X
H
X
X
Write is Completed
H
X
X
X
Prepare for Next Cycle (Same as -1)
X
X
V
X
Cycle Ends, Next Cycle Begins (Same as 0)
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
The write cycle begins with the E falling edge latching the
address. The write portion of the cycle is defined by E, S1,
S2 and W all being low simultaneously. The write portion of
the cycle is terminated by the first rising edge of any control
line, E, S1, S2 or W. The data setup and data hold times
(TDVWH and TWHDX) must be referenced to the terminating signal. For example, if S2 rises first, data setup and hold
times become TDVS2H and TS2HDX; and are numerically
equal to TDVWH and TWHDX.
Data input/output multiplexing is controlled by W. Care must
be taken to avoid data bus conflicts, where the RAM outputs
become enabled when another device is driving the data
inputs. The following two examples illustrate the timing
required to avoid bus conflicts.
Case 1: Both S1 and S2 Fall Before W Falls.
If both selects fall before W falls, the RAM outputs will
become enabled. W is used to disable the outputs, so a disable time (TWLQZ = TWLDV) must pass before any other
device can begin to drive the data inputs. This method of
operation requires a wider write pulse, because TWLDV +
TDVWH is greater than TWLWH. In this case TWLSL +
TSHWH are meaningless and can be ignored.
Case 2: W Falls Before Both S1 and S2 Fall.
If one or both selects are high until W falls, the outputs are
guaranteed not to enable at the beginning of the cycle. This
eliminates the concern for data bus conflicts and simplifies
data input timing. Data input may be applied as early as
convenient, and TWLDV is ignored. Since W is not used to
disable the outputs it can be shorter than in Case 1; TWLWH
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HM-6561/883
is the minimum write pulse. At the end of the write period, if
W rises before either select the outputs will enable reading
data just written. They will not disable until either select goes
high (TSHQZ).
IF
OBSERVE
IGNORE
CASE 1
Both S1 and S2 = Low
Before W = Low
TWLQZ
TWLDV
TDVWH
TWLWH
CASE 2
W = Low Before Both
S1 and S2 = Low
TWLWH
TDVWH
TWLQZ
TWLDV
If a series of consecutive write cycles are to be performed,
W may remain low until all desired locations are written. This
is an extension of Case 2.
Read-Modify-Write cycles and Read-Write-Read cycles can
be performed (extension of Case 1). In fact data may be
modified as many times as desired with E remaining low.
Burn-In Circuit
HM-6561/883
CERDIP
VCC
C1
F6
1
A3
VCC 18
F5
2
A2
A4 17
F7
F4
3
A1
W 16
F1
F3
4
A0
S1 15
F0
F8
5
A5
DQ3 14
F2
F9
6
A6
DQ2 13
F2
F10
7
A7
DQ1 12
F2
8
GND
DQ0 11
F2
9
E
S2 10
F0
F0
NOTES:
All resistors 47kΩ ±5%.
F0 = 100kHz ±10%.
F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F12 = F11 ÷ 2.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
C1 = 0.01µF Min.
6-124
HM-6561/883
Die Characteristics
DIE DIMENSIONS:
132 x 160 x 19 ±1mils
WORST CASE CURRENT DENSITY:
1.337 x 105 A/cm2
METALLIZATION:
Type: Si - Al
Thickness: 11kÅ ±2kÅ
LEAD TEMPERATURE (10s soldering):
≤ 300oC
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
Metallization Mask Layout
HM-6561/883
S1
DQ3 DQ2
W
DQ1
DQ0
S2
A4
VCC
A3
A2
E
A1
GND
A0
A5
A6
A7
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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