TI OPA659IDBVR Wideband, unity-gain stable, jfet-input operational amplifier Datasheet

OPA659
OP
A6
59
www.ti.com........................................................................................................................................................................................... SBOS342 – DECEMBER 2008
Wideband, Unity-Gain Stable, JFET-Input
OPERATIONAL AMPLIFIER
FEATURES
DESCRIPTION
1
•
•
•
•
•
•
•
•
•
2
HIGH BANDWIDTH: 650MHz (G = +1V/V)
HIGH SLEW RATE: 2550V/µs (4V Step)
EXCELLENT THD: –78dBc at 10MHz
LOW INPUT VOLTAGE NOISE: 8.9nV/√Hz
FAST OVERDRIVE RECOVERY: 8ns
FAST SETTLING TIME (1% 4V Step): 8ns
LOW INPUT OFFSET VOLTAGE: ±1mV
LOW INPUT BIAS CURRENT: ±10pA
HIGH OUTPUT CURRENT: 70mA
APPLICATIONS
•
•
•
•
HIGH-IMPEDANCE DATA ACQUISITION INPUT
AMPLIFIER
HIGH-IMPEDANCE OSCILLOSCOPE INPUT
AMPLIFIER
WIDEBAND PHOTODIODE TRANSIMPEDANCE
AMPLIFIER
WAFER SCANNING EQUIPMENT
TRANSIMPEDANCE GAIN
vs FREQUENCY (CD = 22pF)
The OPA659 combines a very wideband, unity-gain
stable, voltage-feedback operational amplifier with a
JFET-input stage to offer an ultra-high dynamic range
amplifier for high impedance buffering in data
acquisition applications such as oscilloscope
front-end amplifiers and machine vision applications
such as photodiode transimpedance amplifiers used
in wafer inspection.
The wide 650MHz unity-gain bandwidth is
complemented by a very high 2550V/µs slew rate.
The high input impedance and low bias current
provided by the JFET input are supported by the low
8.9nV/√Hz input voltage noise to achieve a very low
integrated
noise
in
wideband
photodiode
transimpedance applications.
Broad transimpedance bandwidths are possible with
the high 350MHz gain bandwidth product of this
device.
Where lower speed with lower quiescent current is
required, consider the OPA656. Where unity-gain
stability is not required, consider the OPA657.
+6V
0.1mF
VOUT
RELATED
OPERATIONAL AMPLIFIER
PRODUCTS
10mF
ROUT
RF
Photo
Diode
l
ID
DEVICE
VS
(V)
BW
(MHz)
SLEW
RATE
(V/µs)
VOLTAGE
NOISE
(nV/√Hz)
OPA356
+5
200
300
5.80
Unity-Gain
Stable CMOS
OPA653
±6
500
2675
6.1
Fixed Gain of
+2V/V
JFET-Input
OPA656
±5
500
290
7
Unity-Gain
Stable
JFET-Input
OPA657
±5
1600
700
4.8
Gain of +7
Stable
JFET-Input
OPA627
±15
16
55
4.5
Unity-Gain
Stable
DI-FET-Input
THS4631
±15
105
900
7
Unity-Gain
Stable
JFET-Input
50W Load
OPA659
CD
CF
0.1mF
-VB
-6V
130
RF = 1MW, CF = Open
Transimpedance Gain (dBW)
120
RF = 100kW, CF = Open
110
RF = 10kW,
CF = Open
100
90
10mF
RF = 100kW,
CF = 0.5pF
80
70
RF = 10kW, CF = 1.5pF
RF = 1kW, CF = Open
60
50
40
100k
AMPLIFIER
DESCRIPTION
RF = 1kW, CF = 4.7pF
10M
1M
100M
Frequency (Hz)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
OPA659
SBOS342 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
OPA659
SOT23-5
DBV
–40°C to +85°C
BZX
OPA659
VSON-8
DRB
–40°C to +85°C
OBFI
(1)
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA659IDBVT
Tape and reel, 250
OPA659IDBVR
Tape and reel, 3000
OPA659IDRBT
Tape and reel, 250
OPA659IDRBR
Tape and reel, 3000
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).
OPA653
UNIT
Power Supply Voltage VS+ to VS–
±6.5
V
Input Voltage
±VS
V
Input Current
100
mA
100
mA
Output Current
Continuous Power Dissipation
See Thermal Characteristics
Operating Free Air Temperature Range, TA
–40 to +85
°C
Storage Temperature Range
–65 to +150
°C
Lead Temperature (soldering, 10s)
+260
°C
Maximum Junction Temperature, TJ
+150
°C
Maximum Junction Temperature, TJ (continuous operation for long term reliability)
+125
°C
Human Body Model (HBM)
4000
V
Charge Device Model (CDM)
1000
V
Machine Model
200
V
ESD
Rating:
DRB PACKAGE
VSON-8
(TOP VIEW)
Note:
2
DRV PACKAGE
SOT23-5
(TOP VIEW)
NC
1
8
NC
Inverting Input
2
7
+VS
Noninverting Input
3
6
Output
-VS
4
5
NC
Output
1
-VS
2
Noninverting Input
3
5
+VS
4
Inverting Input
NC: Not connected.
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ELECTRICAL CHARACTERISTICS: VS = ±6V
At RF = 0Ω, G = +1V/V, and RL = 100Ω, TA = +25°C, unless otherwise noted.
OPA659
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
Small-Signal Bandwidth
VO = 200mVPP, G = +1V/V
650
MHz
C
VO = 200mVPP, G = +2V/V
335
MHz
C
VO = 200mVPP, G = +5V/V
75
MHz
C
VO = 200mVPP, G = +10V/V
35
MHz
C
G > +10V/V
350
MHz
C
Bandwidth for 0.1dB Flatness
G = +2V/V, VO = 2VPP
55
MHz
C
Large-Signal Bandwidth
VO = 2VPP, G = +1V/V
575
MHz
B
Slew Rate
VO = 4V Step, G = +1V/V
2550
V/µs
B
Rise and Fall Time
VO = 4V Step, G = +1V/V
1.3
ns
C
Settling Time to 1%
VO = 4V Step, G = +1V/V
8
ns
C
Pulse Response Overshoot
VO = 4V Step, G = +1V/V
12
%
C
2nd harmonic
–79
dBc
C
3rd harmonic
–100
dBc
C
–72
dBc
C
Gain Bandwidth Product
Harmonic Distortion
Intermodulation Distortion
VO = 2VPP, G = +1V/V, f = 10MHz
VO= 2VPP Envelope (each tone 1VPP),
G = +2V/V, f1 = 10MHz, f2 = 11MHz
2nd intermodulation
–96
dBc
C
Input Voltage Noise
3rd intermodulation
f > 100kHz
8.9
nV/√Hz
C
Input Current Noise
f < 10MHz
1.8
fA/√Hz
C
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Average input bias current drift
Input Offset Current
TA = +25°C, VCM = 0V, RL = 100Ω
52
58
dB
A
TA = –40°C to +85°C, VCM = 0V, RL = 100Ω
49
55
dB
B
TA = +25°C, VCM = 0V
±1
±5
mV
A
TA = –40°C to +85°C, VCM = 0V
±1.5
±7.6
mV
B
TA = –40°C to +85°C, VCM = 0V
±10
±40
µV/°C
B
TA = +25°C, VCM = 0V
±10
±50
pA
A
TA = 0°C to +70°C, VCM = 0V
±240
±1200
pA
B
TA = –40°C to +85°C, VCM = 0V
±640
±3200
pA
B
TA = 0°C to +70°C, VCM = 0V
±5
±26
pA/°C
B
TA = –40°C to +85°C, VCM = 0V
±7
±34
pA/°C
B
TA = +25°C, VCM = 0V
±5
±25
pA
A
TA = 0°C to +70°C, VCM = 0V
±120
±600
pA
B
TA = –40°C to +85°C, VCM = 0V
±320
±1600
pA
B
INPUT
Common-Mode Input Range
Common-Mode Rejection Ratio
TA = +25°C
±3
±3.5
V
A
TA = –40°C to +85°C
±2.87
±3.37
V
B
TA = +25°C, VCM = ±0.5V
68
70
dB
A
TA = –40°C to +85°C, VCM = ±0.5V
64
66
dB
B
Input Impedance
1012
Differential
1012
Common-mode
(1)
1
Ω
pF
C
2.5
Ω
pF
C
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
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OPA659
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ELECTRICAL CHARACTERISTICS: VS = ±6V (continued)
At RF = 0Ω, G = +1V/V, and RL = 100Ω, TA = +25°C, unless otherwise noted.
OPA659
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
OUTPUT
Output Voltage Swing
Output Current, Sourcing, Sinking
Closed-Loop Output Impedance
TA = +25°C, No Load
±4.6
±4.8
V
A
TA = +25°C, RL = 100Ω
±3.8
±4.0
V
A
TA = –40°C to +85°C, No Load
±4.45
±4.65
V
B
TA = –40°C to +85°C, RL = 100Ω
±3.65
±3.85
V
B
TA = +25°C
±60
±70
mA
A
TA = –40°C to +85°C
±56
±65
mA
B
0.04
Ω
C
G = +1V/V, f = 100kHz
POWER SUPPLY
Operating Voltage
Quiescent Current
Power-Supply Rejection Ratio (PSRR)
±3.5
±6
±6.5
V
B
TA = +25°C
30.5
32
33.5
mA
A
TA = –40°C to +85°C
28.3
35.7
mA
B
TA = 25°C, VS = ±5.5V to ±6.5V
58
62
dB
A
TA = –40°C to 85°C, VS = ±5.5V to ±6.5V
56
60
dB
A
°C
C
THERMAL CHARACTERISTICS
Specified Operating Range
DRB and DRV Packages
–40
Thermal Resistance, θJA
4
+85
Junction-to-ambient
DRB
VSON-8
55
°C/W
C
DRV
SOT23-5
105
°C/W
C
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TYPICAL CHARACTERISTICS
Table of Graphs
TITLE
FIGURE
Noninverting Small-Signal Frequency Response
VO = 200mVPP
Figure 1
Noninverting Large-Signal Frequency Response
VO = 2VPP
Figure 2
Noninverting Large-Signal Frequency Response
VO = 6VPP
Figure 3
Inverting Small-Signal Frequency Response
VO = 200mVPP
Figure 4
Inverting Large-Signal Frequency Response
VO = 2VPP
Figure 5
Inverting Large-Signal Frequency Response
VO = 6VPP
Figure 6
Noninverting Transient Response
0.5V Step
Figure 7
Noninverting Transient Response
2V Step
Figure 8
Noninverting Transient Response
5V Step
Figure 9
Inverting Transient Response
0.5V Step
Figure 10
Inverting Transient Response
2V Step
Figure 11
Inverting Transient Response
5V Step
Figure 12
Harmonic Distortion vs Frequency
Figure 13
Harmonic Distortion vs Noninverting Gain
Figure 14
Harmonic Distortion vs Inverting Gain
Figure 15
Harmonic Distortion vs Load Resistance
Figure 16
Harmonic Distortion vs Output Voltage
Figure 17
Harmonic Distortion vs ±Supply Voltage
Figure 18
Two-Tone, Second- and Third-Order Intermodulation Distortion vs Frequency
Figure 19
Overdrive Recovery
Gain = +2V/V
Figure 20
Overdrive Recovery
Gain = –2V/V
Figure 21
Input-Referred Voltage Spectral Noise Density
Figure 22
Common-Mode Rejection Ratio and Power-Supply Rejection Ratio vs Frequency
Figure 23
Recommended RISO vs Capacitive Load
Figure 24
Frequency Response vs Capacitive Load
Figure 25
Open-Loop Gain and Phase
Figure 26
Closed-Loop Output Impedance vs Frequency
Figure 27
Transimpedance Gain vs Frequency
CD = 10pF
Figure 28
Transimpedance Gain vs Frequency
CD = 22pF
Figure 29
Transimpedance Gain vs Frequency
CD = 47pF
Figure 30
Transimpedance Gain vs Frequency
CD = 100pF
Figure 31
Maximum/Minimum ±VOUT vs RLOAD
Figure 32
Slew Rate vs VOUT Step
Figure 33
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TYPICAL CHARACTERISTICS
At VS = ±6V, RF = 0Ω, G = +1V/V, and RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE
(VO = 200mVPP)
4
Normalized Signal Gain (dB)
G = +5V/V
-6
-8
G = +10V/V
-10
VS = ±6.0V
RL = 100W
VO = 200mVPP
-16
100k
1M
10M
100M
G = +5V/V
-4
-6
G = +10V/V
-8
-10
-12
VS = ±6.0V
RL = 100W
VO = 2VPP
-16
100k
1G
1M
10M
100M
1G
Frequency (Hz)
Figure 1.
Figure 2.
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE
(VO = 6VPP)
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
(VO = 200mVPP)
4
G = +1V/V
2
0
-2
G = +5V/V
-4
-6
G = +10V/V
-8
-10
-12
-14
VS = ±6.0V
RL = 100W
VO = 6VPP
-16
100k
10M
100M
G = -5V/V
-4
-6
G = -10V/V
-8
-10
-12
VS = ±6.0V
RL = 100W
VO = 200mVPP
-16
100k
1G
G = -1V/V
0
-2
-14
1M
G = -2V/V
2
G = +2V/V
Normalized Signal Gain (dB)
Normalized Signal Gain (dB)
-2
Frequency (Hz)
4
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
Figure 3.
Figure 4.
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
(VO = 2VPP)
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
(VO = 6VPP)
4
2
Normalized Signal Gain (dB)
G = +2V/V
0
-14
G = -2V/V
4
G = -1V/V
0
-2
G = -5V/V
-4
-6
G = -10V/V
-8
-10
-12
-14
VS = ±6.0V
RL = 100W
VO = 2VPP
-16
100k
0
-2
10M
100M
1G
G = -5V/V
-4
-6
G = -10V/V
-8
-10
-12
-14
1M
G = -2V/V G = -1V/V
2
Normalized Signal Gain (dB)
Normalized Signal Gain (dB)
-2
-4
G = +1V/V
2
G = +2V/V
0
-14
6
4
G = +1V/V
2
-12
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE
(VO = 2VPP)
VS = ±6.0V
RL = 100W
VO = 6VPP
-16
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 5.
Figure 6.
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100M
1G
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TYPICAL CHARACTERISTICS (continued)
At VS = ±6V, RF = 0Ω, G = +1V/V, and RL = 100Ω, unless otherwise noted.
NONINVERTING TRANSIENT RESPONSE (0.5V STEP)
0.3
VOUT
VIN
0.2
0.1
0
-0.1
-0.2
0.5
0
-0.5
-1.0
-0.3
-1.5
0
10
20
30
40
50
0
20
30
Time (ns)
Figure 7.
Figure 8.
NONINVERTING TRANSIENT RESPONSE (5V STEP)
40
50
INVERTING TRANSIENT RESPONSE (0.5V STEP)
0.3
VOUT
VIN
2.5
0.2
VIN/VOUT (V)
1.5
VIN/VOUT (V)
10
Time (ns)
3.5
0.5
-0.5
-1.5
VOUT
VIN
0.1
0
-0.1
-0.2
-2.5
-3.5
-0.3
0
10
20
30
40
50
0
10
20
30
Time (ns)
Time (ns)
Figure 9.
Figure 10.
INVERTING TRANSIENT RESPONSE (2V STEP)
1.5
40
50
INVERTING TRANSIENT RESPONSE (5V STEP)
3.5
VOUT
VIN
1.0
VOUT
VIN
2.5
1.5
0.5
VIN/VOUT (V)
VIN/VOUT (V)
VOUT
VIN
1.0
VIN/VOUT (V)
VIN/VOUT (V)
NONINVERTING TRANSIENT RESPONSE (2V STEP)
1.5
0
-0.5
0.5
-0.5
-1.5
-1.0
-2.5
-3.5
-1.5
0
10
20
30
40
50
0
10
20
30
Time (ns)
Time (ns)
Figure 11.
Figure 12.
40
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TYPICAL CHARACTERISTICS (continued)
At VS = ±6V, RF = 0Ω, G = +1V/V, and RL = 100Ω, unless otherwise noted.
HARMONIC DISTORTION vs NONINVERTING GAIN
AT 10MHz
HARMONIC DISTORTION vs FREQUENCY
-50
VS = ±6.0V
G = 1V/V
R F = 0W
RL = 100W
VOUT = 2VPP
-60
-70
-80
-90
Third
Harmonic
-100
Second
Harmonic
VS = ±6.0V
RL = 100W
VOUT = 2VPP
f = 10MHz
-55
Second
Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
-60
-65
-70
-75
Third
Harmonic
-80
-85
-90
-95
-110
-100
1
10
0
100
4
2
HARMONIC DISTORTION vs INVERTING GAIN
AT 10MHz
HARMONIC DISTORTION vs LOAD RESISTANCE
AT 10MHz
-50
VS = ±6.0V
RL = 100W
VOUT = 2VPP
f = 10MHz
-60
-65
Second
Harmonic
-70
-75
-80
Third
Harmonic
-85
-90
-60
-65
-70
-75
-85
-95
-100
4
6
8
Third
Harmonic
-90
-95
2
Second
Harmonic
-80
-100
0
VS = ±6.0V
Gain = 1V/V
RF = 0W
VOUT = 2VPP
f = 10MHz
-55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
10
Figure 14.
-55
0
10
100 200 300 400 500 600 700 800 900
Figure 15.
Figure 16.
HARMONIC DISTORTION vs OUTPUT VOLTAGE
HARMONIC DISTORTION
vs ±SUPPLY VOLTAGE
-70
VS = ±6.0V
Gain = 1V/V
RF = 0W
RL = 100W
f = 10MHz
-60
-70
Second
6
Harmonic
-80
Third
Harmonic
-90
-100
-80
-85
-90
-100
-110
-110
2
4
6
Third
Harmonic
-95
-105
0
Second
6
Harmonic
-75
Harmonic Distortion (dBc)
-50
1k
RLOAD (W)
Inverting Gain (V/V)
Harmonic Distortion (dBc)
8
Figure 13.
-50
f = 10MHz
Gain = +2V/V
RL = 100W
VOUT = 2VPP
4.0
VOUT (VPP)
4.5
5.0
5.5
6.0
±Supply Voltage (V)
Figure 17.
8
6
Noninverting Gain (V/V)
Frequency (MHz)
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
At VS = ±6V, RF = 0Ω, G = +1V/V, and RL = 100Ω, unless otherwise noted.
TWO-TONE, SECOND- AND THIRD-ORDER IMD
vs FREQUENCY
OVERDRIVE RECOVERY (GAIN = +2V/V)
3
-40
VIN
Left Scale
-50
2
-60
VIN(V)
VS = ±6.0V
RL = 100W
Gain = +2V/V
Two-Tone, 1MHz Spacing
1VPP Each Tone
-80
-90
-100
0
1
2
0
0
50
100
VOUT
Right Scale
-1
-4
-3
150
-6
0
20
40
120
INPUT-REFERRED VOLTAGE AND CURRENT NOISE
DENSITY
6
4
VOUT
Right Scale
2
0
-1
-2
VS = ±6.0V
RL = 100W
Gain = -2V/V
20
-4
Input-Referred Voltage Noise (nV/ÖHz)
Input-Referred Current Noise (fA/ÖHz)
OVERDRIVE RECOVERY (GAIN = –2V/V)
VOUT(V)
VIN(V)
100
Figure 20.
VIN
Left Scale
0
80
Time (ns)
0
-3
60
Figure 19.
1
-2
-2
-2
Frequency (MHz)
2
4
Third-Order
-70
3
6
VS = ±6.0V
RL = 100W
Gain = +2V/V
VOUT(V)
Intermodulation Distortion (dBc)
Second-Order
1000
100
10
Input-Referred
6
Current Noise
1
-6
40
60
80
100
Input-Referred
Voltage Noise
10
120
100
1k
10k
100k
1M
10M
Frequency (Hz)
Time (ns)
Figure 21.
Figure 22.
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION RATIO
vs FREQUENCY
RECOMMENDED RISO
vs CAPACITIVE LOAD (RLOAD = 1kΩ)
100
80
+PSRR
60
-PSRR
50
RISO (W)
CMRR, PSRR (dB)
70
CMRR
40
10
30
20
10
0
100k
1
10M
1M
100M
10
Frequency (Hz)
100
1000
Capacitive Load (pF)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
At VS = ±6V, RF = 0Ω, G = +1V/V, and RL = 100Ω, unless otherwise noted.
FREQUENCY RESPONSE
vs CAPACITIVE LOAD (RLOAD = 1kΩ)
5
OPEN-LOOP GAIN AND PHASE
60
CL = 10pF, RISO = 30.1W
50
CL = 100pF, RISO = 12.1W
Gain (dB)
-5
CL = 1000pF, RISO = 5W
-10
-15
-45
AOL Gain
30
AOL Phase
20
10
-135
0
-20
1M
10M
100M
-180
10k
1G
100k
Figure 26.
CLOSED-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
TRANSIMPEDANCE GAIN
vs FREQUENCY (CD = 10pF)
130
10
1
0.1
RF = 100kW, CF = Open
110
10M
100M
RF = 100kW,
CF = 0.25pF
90
80
RF = 10kW, CF = 1pF
70
RF = 1kW, CF = Open
60
RF = 1kW, CF = 3.3pF
40
100k
1G
Figure 28.
TRANSIMPEDANCE GAIN
vs FREQUENCY (CD = 22pF)
TRANSIMPEDANCE GAIN
vs FREQUENCY (CD = 47pF)
RF = 100kW, CF = Open
110
RF = 10kW,
CF = Open
100
RF = 100kW,
CF = 0.5pF
80
RF = 10kW, CF = 1.5pF
RF = 1kW, CF = Open
60
50
10M
110
RF = 1MW, CF = Open
RF = 1MW,
CF = 0.25pF
100M
90
RF = 10kW,
CF = Open
RF = 100kW,
CF = 0.5pF
80
70
RF = 10kW, CF = 1.5pF
RF = 1kW, CF = Open
60
40
100k
Frequency (Hz)
RF = 1kW, CF = 4.7pF
10M
1M
100M
Frequency (Hz)
Figure 29.
10
RF = 100kW, CF = Open
100
50
RF = 1kW, CF = 4.7pF
1M
120
Transimpedance Gain (dBW)
Transimpedance Gain (dBW)
130
RF = 1MW, CF = Open
120
100M
Frequency (Hz)
Figure 27.
130
40
100k
10M
1M
Frequency (Hz)
70
RF = 10kW,
CF = Open
100
50
1M
1G
RF = 1MW, CF = Open
120
Transimpedance Gain (dBW)
Closed Loop Output Impedance (W)
Figure 25.
100
90
100M
Frequency (Hz)
VS = ±6.0V
G = +1V/V
0.01
100k
10M
1M
Frequency (Hz)
1k
-90
-10
VS = ±6.0V
G = +1V/V
-25
100k
40
Open-Loop Phase (°)
Open-Loop Gain (dB)
0
-20
0
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
At VS = ±6V, RF = 0Ω, G = +1V/V, and RL = 100Ω, unless otherwise noted.
TRANSIMPEDANCE GAIN
vs FREQUENCY (CD = 100pF)
130
MAXIMUM/MINIMUM ±VOUT
vs RLOAD
5
RF = 1MW, CF = Open
4
110
RF = 100kW, CF = Open
RF = 1MW,
CF = 0.25pF
RF = 10kW, CF = Open
100
90
RF = 100kW,
CF = 0.5pF
70
2
RF = 1kW,
CF = Open
80
RF = 10kW, CF = 1.5pF
40
100k
1
VS = ±6.0V
G = +1V/V
RF = 249W
0
-1
-2
60
50
VOUT High
3
±VOUT (V)
Transimpedance Gain (dBW)
120
-3
RF = 1kW, CF = 4.7pF
VOUT Low
-4
-5
10M
1M
10
100M
100
1000
RLOAD (W)
Frequency (Hz)
Figure 31.
Figure 32.
SLEW RATE
vs VOUT STEP
Slew Rate (V/ms)
3000
Rising
6
Slew Rate
VS = ±6.0V
G = +2V/V
RLOAD = 100W
Falling
Slew Rate
2000
1000
0
0
1
2
3
4
5
VOUT / VSTEP (V)
Figure 33.
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APPLICATION INFORMATION
Wideband, Noninverting Operation
The OPA659 is a very broadband, unity-gain stable,
voltage-feedback amplifier with a high impedance
JFET-input stage. Its very high gain bandwidth
product (GBP) of 350MHz can be used to either
deliver high signal bandwidths for low-gain buffers, or
to deliver broadband, low-noise, transimpedance
bandwidth to photodiode-detector applications. The
OPA659 is designed to to provide very low distortion
and accurate pulse response with low overshoot and
ringing. To achieve the full performance of the
OPA659, careful attention to printed circuit board
(PCB) layout and component selection are required,
as discussed in the remaining sections of this data
sheet.
Figure 34 shows the noninverting gain of +1 circuit;
Figure 35 shows the more general circuit used for
other noninverting gains. These circuits are used as
the basis for most of the noninverting gain Typical
Characteristics graphs. Most of the graphs were
characterized using signal sources with 50Ω driving
impedance, and with measurement equipment
presenting a 50Ω load impedance. In Figure 34, the
shunt resistor RT at VIN should be set to 50Ω to
match the source impedance of the test generator
and cable, while the series output resistor, ROUT, at
VOUT should also be set to 50Ω to provide matching
impedance for the measurement equipment load and
cable. Generally, data sheet voltage swing
specifications are measured at the output pin, VOUT,
in Figure 34 and Figure 35.
+6V
0.1mF
50W Source
10mF
VIN
VOUT
ROUT
OPA659
50W Load
RT
RF
RG
0.1mF
10mF
-6V
Figure 35. General Noninverting Test Circuit
Table 1. Resistor Values for Noninverting Gains
with 50Ω Input/Output Match
+6V
0.1mF
50W Source
Voltage-feedback op amps can use a wide range of
resistor values to set the gain. To retain a controlled
frequency response for the noninverting voltage
amplifier of Figure 35, the parallel combination of RF
|| RG should always be less than 200Ω. In the
noninverting configuration, the parallel combination of
RF || RG forms a pole with the parasitic input and
board layout capacitance at the inverting input of the
OPA659. For best performance, this pole should be
at a frequency greater than the closed-loop
bandwidth for the OPA659. For this reason, a direct
short from the output to the inverting input is
recommended for the unity-gain follower application.
Table 1 lists several recommended resistor values for
noninverting gains with a 50Ω input/output match.
NONINVERTING
GAIN
10mF
VIN
VOUT
ROUT
OPA659
RG
RT
ROUT
+1
0
Open
49.9
49.9
+2
249
249
49.9
49.9
+5
249
61.9
49.9
49.9
+10
249
27.4
49.9
49.9
50W Load
RT
0.1mF
RF
10mF
-6V
Figure 34. Noninverting Gain of +1 Test Circuit
12
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Wideband, Inverting Gain Operation
The circuit of Figure 36 shows the inverting gain test
circuit used for most of the inverting Typical
Characteristics graphs. As with the noninverting
applications, most of the curves were characterized
using signal sources with 50Ω driving impedance,
and with measurement equipment that presents a
50Ω load impedance. In Figure 36, the shunt resistor
RT at VIN should be set so the parallel combination of
the shunt resistor and RG equals 50Ω to match the
source impedance of the test generator and cable,
while the series output resistor ROUT at VOUT should
also be set to 50Ω to provide matching impedance for
the measurement equipment load and cable.
Generally, data sheet voltage swing specifications are
measured at the output pin, VOUT, in Figure 36.
+6V
0.1mF
10mF
ROUT
VOUT
OPA659
50W Source
RF
RG
VIN
50W Load
RT
0.1mF
10mF
-6V
Figure 36. General Inverting Test Circuit
The inverting circuit can also use a wide range of
resistor values to set the gain; Table 2 lists several
recommended resistor values for inverting gains with
a 50Ω input/output match.
Figure 36 shows the noninverting input tied directly to
ground. Often, a bias current-cancelling resistor to
ground is included here to nullify the dc errors caused
by input bias current effects. For a JFET input op
amp such as the OPA659, the input bias currents are
so low that dc errors caused by input bias currents
are negligible. Thus, no bias current-cancelling
resistor is recommended at the noninverting input.
Wideband, High-Sensitivity, Transimpedance
Design
The high GBP and low input voltage and current
noise for the OPA659 make it an ideal wideband,
transimpedance amplifier for low to moderate
transimpedance gains. Higher transimpedance gains
(above 100kΩ) can benefit from the low input noise
current of a JFET input op amp such as the OPA659.
Designs that require high bandwidth from a large
area detector can benefit from the low input voltage
noise for the OPA659. This input voltage noise is
peaked up over frequency by the diode source
capacitance, and in many cases, may become the
limiting factor to input sensitivity. The key elements to
the design are the expected diode capacitance (CD)
with the reverse bias voltage (–VB) applied, the
desired transimpedance gain, RF, and the GBP for
the OPA659 (350MHz). Figure 37 shows a general
transimpedance amplifier circuit, or TIA, using the
OPA659. Given the source diode capacitance plus
parasitic input capacitance for the OPA659, the
transimpedance gain, and known GBP, the feedback
capacitor value, CF, may be calculated to avoid
excessive peaking in the frequency response.
+6V
0.1mF
Table 2. Resistor Values for Inverting Gains with
50Ω Input/Output Match
INVERTING
GAIN
RF
RG
RT
ROUT
–1
249
249
61.9
49.9
–2
249
124
84.5
49.9
–5
249
49.9
Open
49.9
–10
499
49.9
Open
49.9
VOUT
10mF
ROUT
OPA659
50W Load
RF
Photo
Diode
l
ID
CD
CF
0.1mF
-VB
10mF
-6V
Figure 37. Wideband, Low-Noise, Transimpedance
Amplifier (TIA)
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To achieve a maximally flat second-order Butterworth
frequency response, the feedback pole should be set
to:
1
=
2pRFCF
GBP
4pRFCD
(1)
For example, adding the common mode and
differential mode input capacitance (0.7 + 2.8 =
3.5)pF to the diode source with the 20pF
capacitance, and targeting a 100kΩ transimpedance
gain using the 350MHz GBP for the OPA659,
requires a feedback pole set to 3.44MHz. This pole in
turn requires a total feedback capacitance of 0.46pF.
Typical surface mount resistors have a parasitic
capacitance of 0.2pF, leaving the required 0.26pF
value to achieve the required feedback pole. This
calculation gives an approximate 4.9MHz, –3dB
bandwidth computed by:
GBP
2pRFCD
f-3dB =
(2)
Table 3 lists the calculated component values and
–3dB bandwidths for various TIA gains and diode
capacitance.
Table 3. OPA659 TIA Component Values and Bandwidth for Various Diode Capacitance and Gains
CDIODE = 10pF
CD
RF
CF
f–3dB
13.5 pF
1kΩ
3.50pF
64.24MHz
13.5 pF
10kΩ
1.11pF
20.31MHz
13.5 pF
100kΩ
0.35pF
6.42MHz
13.5 pF
1MΩ
0.11pF
2.03MHz
23.5 pF
1kΩ
4.62pF
48.69MHz
23.5 pF
10kΩ
1.46pF
15.40MHz
23.5 pF
100kΩ
0.46pF
4.87MHz
23.5 pF
1MΩ
0.15pF
1.54MHz
1kΩ
6.98pF
32.27MHz
53.5 pF
10kΩ
2.21pF
10.20MHz
53.5 pF
100kΩ
0.70pF
3.23MHz
53.5 pF
1MΩ
0.22pF
1.02MHz
103.5 pF
1kΩ
9.70pF
23.20MHz
103.5 pF
10kΩ
3.07pF
7.34MHz
103.5 pF
100kΩ
0.97pF
2.32MHz
103.5 pF
1MΩ
0.31pF
0.73MHz
CDIODE = 20pF
CDIODE = 50pF
53.5 pF
CDIODE = 100pF
14
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OPERATING SUGGESTIONS
Setting Resistor Values to Minimize Noise
The OPA659 provides a very low input noise voltage.
To take full advantage of this low input noise,
designers must pay careful attention to other possible
noise contributors. Figure 38 shows the op amp noise
analysis model with all the noise terms included. In
this model, all the noise terms are taken to be noise
voltage or current density terms in either nV/√Hz or
pA/√Hz.
Frequency Response Control
eN
RT
eO
OPA659
IBN
4kTRT
RF
IBI
4kTRF
4kT
RG
RG
Figure 38. Op Amp Noise Analysis Model
The total output spot noise voltage can be computed
as the square root of the squared contributing terms
to the output noise voltage. This computation adds all
the contributing noise powers at the output by
superposition, then takes the square root to arrive at
a spot noise voltage. Equation 3 shows the general
form for this output noise voltage using the terms
shown in Figure 38.
2
eO =
[4kTR
]
2
2
1+
T + (IBNRT) + eN
RF
RF
+ (IBIRF)2 + 4kTRF 1 +
RG
RG
(3)
Dividing this expression by the noise gain (GN = 1 +
RF/RG) gives the equivalent input-referred spot noise
voltage at the noninverting input, as Equation 4
shows.
2
eNI =
4kTRT + (IBNRT)2 + eN2 +
Putting high resistor values into Equation 4 can
quickly dominate the total equivalent input-referred
noise. A source impedance on the noninverting input
of 5kΩ adds a Johnson voltage noise term equal to
that of the amplifier alone (8.9nV/Hz). While the JFET
input of the OPA659 is ideal for high source
impedance
applications
in
the
noninverting
configuration of Figure 34 or Figure 35, both the
overall bandwidth and noise are limited by high
source impedances.
4kTRF
IBIRF
+
Noise Gain
Noise Gain
(4)
space
space
Voltage-feedback op amps such as the OPA659
exhibit decreasing signal bandwidth as the signal gain
increases. In theory, this relationship is described by
the gain bandwidth product (GBP) shown in the
Electrical Characteristics. Ideally, dividing the GBP by
the noninverting signal gain (also called the Noise
Gain, or NG) can predict the closed-loop bandwidth.
In practice, this guideline is valid only when the phase
margin approaches 90 degrees, as it does in high
gain configurations. At low gains (with increased
feedback factors), most high-speed amplifiers exhibit
a more complex response with lower phase margins.
The OPA659 is compensated to give a maximally-flat
frequency response at a noninverting gain of +1 (see
Figure 34). This compensation results in a typical
gain of +1 bandwidth of 650MHz, far exceeding that
predicted by dividing the 350MHz GBP by 1.
Increasing the gain causes the phase margin to
approach 90 degrees and the bandwidth to more
closely approach the predicted value of (GBP/NG). At
a gain of +10, the OPA659 shows the 35MHz
bandwidth predicted using the simple formula and the
typical GBP of 350MHz. Unity-gain stable op amps
such as the OPA659 can also be band-limited in
gains other than +1 by placing a capacitor across the
feedback resistor. For the noninverting configuration
of Figure 35, a capacitor across the feedback resistor
decreases the gain with frequency down to a gain of
+1. For instance, to band-limit a gain of +2 design to
20MHz, a 32pF capacitor can be placed in parallel
with the 249Ω feedback resistor. This configuration,
however, only decreases the gain from 2 to 1. Using
a feedback capacitor to limit the signal bandwidth is
more effective in the inverting configuration of
Figure 36. Adding that same capacitance to the
feedback of Figure 36 sets a pole in the signal
frequency response at 20MHz, but in this case it
continues to attenuate the signal gain to less than 1.
Note, however, that the noise gain of the circuit is
only reduced to a gain of 1 with the addition of the
feedback capacitor.
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Driving Capacitive Loads
Distortion Performance
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
The OPA659 is very robust, but care should be taken
with light loading scenarios so that output
capacitance does not decrease stability and increase
closed-loop frequency response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier open-loop output resistance is
considered, this capacitive load introduces an
additional pole in the signal path that can decrease
the phase margin. Several external solutions to this
problem have been suggested. When the primary
considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest
and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series
isolation resistor, RISO, between the amplifier output
and the capacitive load. In effect, this resistor isolates
the phase shift from the loop gain of the amplifier,
thus increasing the phase margin and improving
stability. The Typical Characteristics show the
recommended RISO versus capacitive load and the
resulting frequency response with a 1kΩ load (see
Figure 24). Note that larger RISO values are required
for lower capacitive loading. In this case, a design
target of a maximally-flat frequency response was
used. Lower values of RISO may be used if some
peaking can be tolerated. Also, operating at higher
gains (instead of the +1 gain used in the Typical
Characteristics) requires lower values of RISO for a
minimally-peaked frequency response. Parasitic
capacitive loads greater than 2pF can begin to
degrade the performance of the OPA659. Moreover,
long PCB traces, unmatched cables, and connections
to multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and
add the recommended series resistor as close as
possible to the OPA659 output pin (see the Board
Layout section).
The OPA659 is capable of delivering a low distortion
signal at high frequencies over a wide range of gains.
The distortion plots in the Typical Characteristics
show the typical distortion under a wide variety of
conditions. Generally, until the fundamental signal
reaches very high frequencies or powers, the second
harmonic dominates the distortion with a negligible
third harmonic component. Focusing then on the
second harmonic, increasing the load impedance
improves distortion directly. Remember that the total
load includes the feedback network: in the
noninverting configuration, this network is the sum of
RF + RG, while in the inverting configuration the
network is only RF (see Figure 35). Increasing the
output voltage swing directly increases harmonic
distortion. A 6dB increase in output swing generally
increases the second harmonic by 12dB and the third
harmonic by 18dB. Increasing the signal gain also
increases the second-harmonic distortion. Again, a
6dB increase in gain increases the second and third
harmonics by about 6dB, even with a constant output
power and frequency. Finally, the distortion increases
as the fundamental frequency increases because of
the rolloff in the loop gain with frequency. Conversely,
the distortion improves going to lower frequencies,
down to the dominant open-loop pole at
approximately 300kHz.
With heavier loads (for example, the 100Ω load
presented in the test circuits and used for testing
typical characteristic performance), the OPA659 is
very robust; RISO can be as low as 10Ω with
capacitive loads less than 5pF and continue to show
a flat frequency response.
space
space
16
Note that power-supply decoupling is critical for
harmonic distortion performance. In particular, for
optimal
second-harmonic
performance,
the
power-supply high-frequency 0.1µF decoupling
capacitors to the positive and negative supply pins
should be brought to a single point ground located
away from the input pins.
The OPA659 has an extremely low third-order
harmonic distortion. This characteristic also shows up
in the two-tone, third-order intermodulation spurious
(IMD3) response curves (see Figure 19). The
third-order spurious levels are extremely low (less
than –100dBc) at low output power levels and
frequencies below 10MHz. The output stage
continues to hold these levels low even as the
fundamental power reaches higher levels. As with
most op amps, the spurious intermodulation powers
do not increase as predicted by a traditional intercept
model. As the fundamental power level increases, the
dynamic range does not decrease significantly. For
two tones centered at 10MHz, with –2dBm/tone into a
matched 50Ω load (that is, 0.5VPP for each tone at
the load, which requires 2VPP for the overall two-tone
envelope at the output pin), the Typical
Characteristics show a 96dBc difference between the
test tones and the third-order intermodulation
spurious levels. This exceptional performance
improves further when operating at lower frequencies
and/or higher load impedances.
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Board Layout
Achieving
optimum
performance
with
a
high-frequency amplifier such as the OPA659
requires careful attention to PCB layout parasitics and
external component types. Recommendations that
can optimize device performance include the
following.
a) Minimize parasitic capacitance to any ac ground
for all of the signal input/output (I/O) pins. Parasitic
capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it can
react with the source impedance to cause
unintentional band-limiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.
b) Minimize the distance (less than 0.25in, or
6,35mm) from the power-supply pins to the
high-frequency, 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins.
Use a single point ground, located away from the
input pins, for the positive and negative supply
high-frequency, 0.1µF decoupling capacitors. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power-supply connections should
always be decoupled with these capacitors. Larger
(2.2µF to 10µF) decoupling capacitors, effective at
lower frequencies, should also be used on the supply
pins. These larger capacitors may be placed
somewhat farther from the device and may be shared
among several devices in the same area of the PCB.
c) Careful selection and placement of external
components
preserves
the
high-frequency
performance of the OPA659. Resistors should be a
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal film
and carbon composition, axially-leaded resistors can
also provide good high-frequency performance.
Again, keep the leads and PCB trace length as short
as possible. Never use wirewound-type resistors in a
high-frequency application. The inverting input pin is
the most sensitive to parasitic capacitance;
consequently, always position the feedback resistor
as close to the negative input as possible. The output
is also sensitive to parasitic capacitance; therefore,
position a series output resistor (in this case, RISO) as
close to the output pin as possible.
Other network components, such as noninverting
input termination resistors, should also be placed
close to the package. Even with a low parasitic
capacitance, excessively high resistor values can
create significant time constants that can degrade
device performance. Good axial metal film or
surface-mount resistors have approximately 0.2pF in
shunt with the resistor. For resistor values greater
than 1.5kΩ, this parasitic capacitance can add a pole
and/or zero below 500MHz that can affect circuit
operation. Keep resistor values as low as possible,
consistent with load driving considerations. It is
recommended to keep RF || RG less than 250Ω. This
low value ensures that the resistor noise terms
remain low, and minimizes the effects of the parasitic
capacitance. Transimpedance applications (for
example, see Figure 37) can use the feedback
resistor required by the application as long as the
feedback compensation capacitor is set given
consideration to all parasitic capacitance terms on the
inverting node.
d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils, or 1,27cm to 2,54cm)
should be used. Estimate the total capacitive load
and set RISO from the plot of Recommended RISO vs
Capacitive Load (Figure 24). Low parasitic capacitive
loads (less than 5pF) may not need an RISO because
the OPA659 is nominally compensated to operate
with a 2pF parasitic load.
Higher parasitic capacitive loads without an RISO are
allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required,
and the 6dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line
using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally
not necessary onboard, and in fact a higher
impedance environment improves distortion as shown
in the distortion versus load plots. With a
characteristic board trace impedance defined based
on board material and trace dimensions, a matching
series resistor into the trace from the output of the
OPA659 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is the
parallel combination of the shunt resistor and the
input impedance of the destination device: this total
effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a
doubly-terminated transmission line is unacceptable,
a long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in this
case, and set the series resistor value as shown in
the plot of RISO vs Capacitive Load (Figure 24). This
configuration does not preserve signal integrity as
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17
OPA659
SBOS342 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com
well as a doubly-terminated line. If the input
impedance of the destination device is low, there will
be some signal attenuation as a result of the voltage
divider formed by the series output into the
terminating impedance.
e) Socketing a high-speed part such as the
OPA659 is not recommended. The additional lead
length and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome parasitic
network that can make it almost impossible to
achieve a smooth, stable frequency response. Best
results are obtained by soldering the OPA659 directly
onto the board.
Input and ESD Protection
The OPA659 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins are protected with internal ESD protection
diodes to the power supplies, as Figure 39 shows.
18
+VCC
External
Pin
Internal
Circuitry
-VCC
Figure 39. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±12V supply
parts driving into the OPA659), current limiting series
resistors should be added into the two inputs. Keep
these resistor values as low as possible because high
values degrade both noise performance and
frequency response.
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EVALUATION MODULE
Schematic and PCB Layout
Figure 40 is the OPA659EVM schematic. Layers 1 through 4 of the PCB are shown in Figure 41. It is
recommended to follow the layout of the external components near to the amplifier, ground plane construction,
and power routing as closely as possible.
2
3
+
7
6
4
+
+
Figure 40. OPA659EVM Schematic
Figure 41. OPA659EVM Layers 1 through 4
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OPA659
SBOS342 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com
Bill of Materials
Table 4 lists the bill of material for the OPA659EVM as supplied from TI.
Table 4. OPA659EVM Parts List
ITEM
20
DESCRIPTION
SMD SIZE
REFERENCE
DESIGNATOR
QUANTITY
MANUFACTURER
PART NUMBER
1
Cap, 10.0µF, Tantalum, 10%, 35V
D
C1, C2
2
(AVX) TAJ106K035R
2
Cap, 0.1µF, Ceramic, X7R, 16V
0603
C3, C4
2
(AVX) 0603YC104KAT2A
3
Open
0603
R1, R2
2
4
Resistor, 0Ω
0603
R4
1
(ROHM) MCR03EZPJ000
5
Resistor, 49.9Ω, 1/10W, 1%
0603
R3, R5
2
(ROHM) MCR03EZPFX49R9
6
Jack, Banana Receptance, 0.25in
diameter hole
J4, J5, J8
3
(SPC) 813
7
Connector, Edge, SMA PCB Jack
J1, J2, J3
3
(JOHNSON) 142-0701-801
8
Test Point, Black
TP1
1
(KEYSTONE) 5001
9
IC, OPA659
U1
1
(TI) OPA659DRB
10
Standoff, 4-40 HEX, 0.625in length
4
(KEYSTONE) 1808
11
Screw, Phillips, 4-40, .250in
4
SHR-0440-016-SN
12
Board, Printed Circuit
1
(TI) EDGE# 6506173
13
Bead, Ferrite, 3A, 80Ω
2
(STEWARD)
HI1206N800R-00
1206
FB1, FB2
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EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does
not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling
(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER
AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY
INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or
services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or
safety programs, please contact the TI application engineer or visit www.ti.com/esh.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio
frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are
designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may
be required to correct this interference.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of ±3.5V to ±6.5V split-supply and the output voltage range of ±3.5V to
±6.5V power-supply voltage; do not exceed ±6.5V power-supply voltage.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than +85°C. The EVM is designed to operate
properly with certain components above +85°C as long as the input and output ranges are maintained. These components include but are
not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified
using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated
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21
PACKAGE OPTION ADDENDUM
www.ti.com
22-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
OPA659IDBVR
PREVIEW
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
OPA659IDBVT
PREVIEW
SOT-23
DBV
5
250
TBD
Call TI
Call TI
OPA659IDRBR
ACTIVE
SON
DRB
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA659IDRBT
ACTIVE
SON
DRB
8
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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