Holtek HT48R54A I/o type 8-bit otp mcu with 16x16 high current led driver Datasheet

HT48R54A
I/O Type 8-Bit OTP MCU with 16´16 High Current LED Driver
Technical Document
· Tools Information
· FAQs
· Application Note
-
HA0002E
HA0007E
HA0019E
HA0020E
HA0075E
Reading Larger than Usual MCU Tables
Using the MCU Look Up Table Instructions
Using the Watchdog Timer in the HT48 MCU Series
Using the Timer/Event Counter in the HT48 MCU Series
MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage:
· RC/XTAL and 32768Hz crystal oscillator
fSYS=32768Hz: 2.2V~5.5V
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Dual clock system offers three operating modes
- Normal mode: Both RC/XTAL and 32768Hz clock
active
· 4k´15 program memory ROM
- Slow mode: 32768Hz clock only
- Idle mode: Periodical wake-up by watchdog timer
· 192´8 data memory RAM
overflow
· 16 bidirectional I/O lines
· HALT function and wake-up feature reduce power
· 24 output lines
consumption
· One external interrupt input
· 15-bit table read instructions
· Two internal interrupt
· 63 powerful instructions
· Two 8 bit programmable timer/event counter
· One instruction cycle: 4 system clock periods
· 32768 Real Time Clock function
· All instructions in 1 or 2 instruction cycles
· 6-level subroutine nesting
· Bit manipulation instructions
· Watchdog Timer (WDT)
· Up to 0.5ms instruction cycle with 8MHz system clock
· Low voltage reset (LVR)
· 44/52-pin QFP package
· PFD/Buzzer driver output
General Description
timer, as well as low cost, enhance the versatility of
these devices to suit a wide range of application possibilities such as industrial control, consumer products,
subsystem controllers, etc.
This device is an 8-bit high performance, RISC architecture microcontroller specifically designed for multiple
I/O control product applications. The advantages of low
power consumption, I/O flexibility, timer functions, oscillator options, HALT and wake-up functions, watchdog
Rev. 1.00
1
July 27, 2007
HT48R54A
Block Diagram
T 1 S
M
In te rru p t
C ir c u it
S ta c k
T M R 1
M e m o ry
L o o k u p T a b le
R e g is te r
T M R 0
T M R 0 C
In s tr u c tio n
R e g is te r
R T C O S C
fS
X
X
Y S
P A 3 /T M R 1
M
U
M
X
U
P r e s c a le r
X
fS
Y S
M
fS
U
X
Y S /4
R T C O S C
W D T O S C
/4
A C C
M U X
P A C
P O R T A
A L U
P A 0 /B Z
P A 1 /B Z
S h ifte r
In s tr u c tio n
D e c o d e r
U
U
W D T
C o u n te r
L o o k u p T a b le
P o in te r
A d d re s s D e c o d e r
P ro g ra m
T M R 1 C
IN T C
S ta c k P o in te r
P ro g ra m
C o u n te r
M
P A 2 /T M R 0
P A
P A 3 /T M R 1
M e m o ry
P o in te r
P A 4 ~ P A 6
P A 7 /P F D
M U X
T im in g
G e n e ra to r
P B C
A d d re s s D e c o d e r
P ro g ra m
P B
O S C 1
Rev. 1.00
O S C 2
R T C
O s c illa to r
O S C 3
O S C 4
P B 0 ~ P B 7
M e m o ry
P C
W D T
O s c illa to r
R C o r C ry s ta l
O s c illa to r
P O R T B
R e s e t &
L V R
R E
V D D
V S S
V
S , V
B , V
, V
S S
P O R T C
P D 0 /IN T
P D
P O R T D
P E
D D
D D C
S S D
E
2
P C 0 ~ P C 7
P O R T E
P D 1 ~ P D 7
P E 0 ~ P E 7
July 27, 2007
HT48R54A
Pin Assignment
P A
P A
P A 2 /T
P A 3 /T
O
O
O
O
S C
S C
V D
S C
S C
R E
0 /B
1 /B
M R
M R
P A
P A
P A
O
O
O
O
P A
P A
P A 2 /T
P A 3 /T
D
S C
S C
V D
S C
S C
R E
0 /B
1 /B
M R
M R
P A
S
Z
Z
6
5
4
1
0
3
4
2
1
D
S
Z
Z
3
4
2
1
0
4
1
P A
P A
P A 7 /P F
P E
P E
P E
V S S
P E
P E
P E
P E
6
D
2
E
6
5
4
1
4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
5
1
3 3
3 2
3
3 1
0
2
4
3 0
5
2 9
H T 4 8 R 5 4 A
4 4 Q F P -A
6
7
3
2 8
2 7
8
2 6
9
2 5
1 0
2 4
1 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 3
V S
P B
P B
P B
P B
V D
V D
P B
P B
P B
P B
0
4
1
2
3
5
6
7
P A 7 /P F
P E
P E
P E
V S S
P E
P E
P E
P E
P E
P D 0 /IN
P D
P D
S
D B
D B
D
1
2
E
6
T
7
5
4
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
1
0
3 7
3
3 6
4
5
3 5
3
6
H T 4 8 R 5 4 A
5 2 Q F P -A
7
8
9
1 0
1 1
1
2
3 9
3 8
2
1 2
1 3
P C
P C
P C
P C
V D
P C
P C
P C
P C
V S
P D
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
V S
P B
P B
P B
P B
V D
V D
P B
P B
P B
P B
P C
P C
0
4
1
2
5
6
7
S
D B
D B
3
7
6
P C 5
P C 4
V D D C
P C 3
P C 2
P C 1
P C 0
P D 7
P D 6
P D 5
V S S D
P D 4
P D 3
7
6
5
4
D C
3
2
1
0
S D
0 /IN T
Pin Description
Pin Name
I/O
Options
Description
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected via configuration option. Each pin can be setup to be a wake-up input
via configuration options.
The PA0 and PA1 are pin-shared with the BZ and BZ, respectively.
The timer input TMR0 is pin-shared with PA2.
The timer input TMR1 is pin-shared with PA3.
The PFD function is pin-shared with PA7 which is determined by configuration
option.
PA0/BZ
PA1/BZ
PA2/TMR0
PA3/TMR1
PA4~PA6
PA7/PFD
I/O
Pull-high
Wake-up
Buzzer
PFD
PB0~PB7
I/O
¾
Bidirectional 8-bit input/output port. When used as output port, they are configured as PMOS output pins.
PC0~PC7
O
¾
PC0~PC7 are PMOS output pins.
PD0/INT
I/O
¾
External interrupt input. Pin-shared with PD0 and activated on a high to low or
low to high transition. PD0 is NMOS type output pin.
PD1~PD7
O
¾
PD1~PD7 are NMOS output pins.
PE0~PE7
O
¾
PE0~PE7 are NMOS output pins.
RES
I
¾
Schmitt trigger reset input. Active low.
OSC1
OSC2
I
O
RC or Crystal
OSC1 and OSC2 are connected to an RC network or a crystal (by options) for
the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.
OSC3
OSC4
I
O
¾
Real time clock oscillator. OSC3 and OSC4 are connected to a 32768Hz crystal oscillator for system clock timing purposes.
VDD
¾
¾
Positive power supply
VDDB
¾
¾
PB port positive power supply
VDDC
¾
¾
PC port positive power supply
VSS
¾
¾
Negative Power supply, ground
VSSD,
VSSE
¾
¾
PD & PE port negative power supply, ground
Rev. 1.00
3
July 27, 2007
HT48R54A
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................300mA
IOH Total............................................................-200mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
VDD
IDD1
Parameter
Operating Voltage
Operating Current
(Crystal OSC, RC OSC)
IDD2
Operating Current
(Crystal OSC, RC OSC)
IDD3
Operating Current
(*RTC OSC Enabled, Crystal OSC
Disabled, RC OSC Disabled)
ISTB1
ISTB2
ISTB3
Standby Current
(WDT OSC, *RTC OSC Enabled)
Standby Current (WDT OSC Disabled,
*RTC OSC Enabled)
Standby Current (WDT OSC Enabled,
RTC OSC Disabled)
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
¾
fSYS=4MHz
2.2
¾
5.5
¾
fSYS=8MHz
3.3
¾
5.5
¾
fSYS=32768Hz
2.2
¾
5.5
¾
1.2
2
¾
2.5
5
¾
4
8
¾
20
40
¾
50
100
¾
3
5
¾
6
10
¾
1
2
¾
2
4
¾
2
4
¾
4
8
¾
¾
1
¾
¾
2
3V
No load, fSYS=4MHz
5V
5V
No load, fSYS=8MHz
3V
No load,
fSYS=32768Hz
5V
3V
5V
3V
5V
3V
5V
3V
No load,
system HALT
No load,
system HALT
No load,
system HALT
V
mA
mA
mA
mA
mA
mA
Standby Current
(WDT OSC, RTC OSC Disabled)
5V
VIL1
Input Low Voltage for I/O Ports
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
2.1V option
1.98
2.1
2.22
V
3.15V option
2.98
3.15
3.32
V
4.2V option
3.98
4.2
4.42
V
4
8
¾
10
20
¾
8
16
¾
20
40
¾
ISTB4
VLVR
IOL1
Low Voltage Reset
¾
3V
I/O Port Sink Current for PA
No load,
system HALT
Unit
VOL=0.1VDD
5V
IOL2
3V
I/O Port Sink Current for PD, PE
VOL=0.1VDD
5V
Rev. 1.00
4
mA
mA
mA
July 27, 2007
HT48R54A
Symbol
Parameter
Test Conditions
3V
IOH1
Conditions
VDD
I/O Port Source Current for PA
VOH=0.9VDD
5V
3V
IOH2
I/O Port Source Current for PB, PC
VOH=0.9VDD
5V
3V
RPH
¾
Pull-high Resistance
5V
Min.
Typ.
Max.
-2
-4
¾
-5
-10
¾
-4
-8
¾
-10
-20
¾
20
60
100
10
30
50
Unit
mA
mA
kW
Note: * RTC OSC in slow start oscillating
A.C. Characteristics
Symbol
Parameter
System Clock
(Crystal OSC, RC OSC)
fSYS
fTIMER
Timer I/P Frequency
tWDTOSC Watchdog Oscillator Period
Ta=25°C
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
¾
2.2V~5.5V
400
¾
4000
¾
3.3V~5.5V
400
¾
8000
¾
2.2V~5.5V
0
¾
4000
¾
3.3V~5.5V
0
¾
8000
Unit
kHz
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
tFSP1
fSP Time-out Period Clock Source
from WDT
¾
With prescaler
(fS/4096)
¾
221
¾
tWDTOSC
tFSP2
fSP Time-out Period Clock Source
from RTC Oscillator
¾
With prescaler
(fS/4096)
¾
221
¾
*tRTC
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Power-up or wake-up
from HALT
¾
1024
¾
tSYS
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Note:
tSYS=1/fSYS
*[email protected]
Rev. 1.00
5
July 27, 2007
HT48R54A
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
a crystal oscillator or an RC oscillator or a RTC oscillator. The system clock is internally divided into four
non-overlapping clocks. One instruction cycle consists
of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call or return
from subroutine, initial reset, internal interrupt, external
interrupt or return from interrupt, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
Skip
Program Counter+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
Rev. 1.00
@7~@0: PCL bits
6
July 27, 2007
HT48R54A
Program Memory - ROM
TBLH is read only and cannot be restored. If the main
routine and the ISR (Interrupt Service Routine) both
employ the table read instruction, the contents of the
TBLH in the main routine are likely to be changed by
the table read instruction used in the ISR, therefore
errors may occur. In other words, using the table read
instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read
instruction has to be applied in both the main routine
and the ISR, the interrupt should be disabled prior to
using the table read instruction. It should not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the
operation. These areas may function as normal program memory depending upon the requirements.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
Certain locations in the program memory are reserved
for special usage:
· Location 000H
This area is reserved for program initialisation. After a
chip reset, the program always begins execution at location 000H.
· Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
· Location 008H
This area is reserved for the timer/event counter 0 interrupt service program. If a timer interrupt results from a
timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
0 0 C H
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
n F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
· Location 00CH
This area is reserved for the timer/event counter 1 interrupt service program. If a timer interrupt results from a
timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
F 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
Program Memory
· Table location
Stack Register - STACK
Any location in the program memory space can be
used as look-up tables. The instructions ²TABRDC
[m]² (the current page, one page=256 words) and
²TABRDL [m]² (the last page) transfer the contents of
the lower-order byte to the specified data memory,
and the higher-order byte to TBLH (08H). Only the
destination of the lower-order byte in the table is
well-defined, the other bits of the table word are transferred to the lower portion of the TBLH, and the remaining 2-bit words are read as ²0². The Table
Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H),
which indicates the table location. Before accessing
the table, the location must be placed in the TBLP. The
Instruction
0 to 7
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 6 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the program counter is restored to its previous value from the
stack. After a chip reset, the stack pointer will point to
the top of the stack.
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
Rev. 1.00
7
July 27, 2007
HT48R54A
0 0 H
If the stack is full and a non-masked interrupt takes place,
the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented, by RET or RET, the interrupt will
be serviced. This feature prevents stack overflow
allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is
subsequently executed, a stack overflow occurs and the
first entry will be lost. Only the most recent 6 return
addresses are stored.
IA R 0
0 1 H
M P 0
0 2 H
IA R 1
0 3 H
M P 1
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
Data Memory - RAM
0 A H
S T A T U S
0 B H
IN T C
0 C H
The data memory is divided into two functional groups,
namely, function registers and general purpose data
memory (192´8). Most are read/write, but some are
read only.
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
1 0 H
T M R 1
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
the memory pointer registers.
1 1 H
T M R 1 C
Indirect Addressing Register
1 8 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P D
1 9 H
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] ([02H]) will access the data memory
pointed to by MP0 (MP1). Reading location 00H (02H)
itself indirectly will return the result ²00H². Writing indirectly results in no operation.
1 A H
P E
1 B H
1 C H
1 D H
1 E H
1 F H
The memory pointer registers, MP0 and MP1, are 8-bit
registers.
2 0 H
Accumulator
4 0 H
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
F F H
M O D E
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
Arithmetic and Logic Unit - ALU
(TO). It also records the status information and controls
the operation sequence.
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition, operations related to the status register may
give different results from those intended. The TO
flag can be affected only by a system power-up, a
WDT time-out or executing the ²CLR WDT² or
²HALT² instruction. The PDF flag can be affected
only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
Rev. 1.00
S p e c ia l P u r p o s e
D a ta M e m o ry
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
8
July 27, 2007
HT48R54A
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a
rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow
from the high nibble into the low nibble in subtraction, otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
4
PDF
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
STATUS (0AH) Register
All interrupts have a wake-up capability. When an interrupt is serviced, a control transfer occurs by pushing the
program counter onto the stack, followed by a branch to
a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack.
If the contents of the register or status register are altered by the interrupt service program, an action which
may corrupt the desired control sequence, the contents
should be saved in advance.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status register are important and if the subroutine
can corrupt the status register, precautions must be
taken to save it properly.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupt. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set
the enable or disable bits and the interrupt request flags.
An external interrupt is triggered either on a high to low
or low to high transition on the INT pin. The related interrupt request flag, EIF; bit 4 of the INTC register will then
be set. When the interrupt is enabled, the stack is not full
and the external interrupt is active, a subroutine call to
location 04H will occur. The interrupt request flag (EIF)
and EMI bits will be cleared to disable other interrupts.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be set
to allow interrupt nesting. If the stack is full, the interrupt
request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from
becoming full.
Bit No.
Label
0
EMI
The internal timer/event counter 0 interrupt is initialised
by setting the timer/event counter 0 interrupt request
flag, T0F; bit 5 of the INTC register. This will be caused
by a timer 0 overflow. When the interrupt is enabled, the
stack is not full and the T0F bit is set, a subroutine call to
location 08H will occur. The related interrupt request
flag, T0F, will then be reset and the EMI bit cleared to
disable further interrupts.
Function
Controls the master (global) interrupt (1=enable; 0=disable)
1
EEI
Controls the external interrupt (1=enable; 0=disable)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
3
ET1I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
4
EIF
External interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
INTC (0BH) Register
Rev. 1.00
9
July 27, 2007
HT48R54A
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged if a
²CALL² is executed in the interrupt subroutine.
The internal timer/event counter 1 interrupt is initialised
by setting the timer/event counter 1 interrupt request
flag, T1F; bit 6 of the INTC register. This will be caused
by a timer 1 overflow. When the interrupt is enabled, the
stack is not full and the T1F bit is set, a subroutine call to
location 0CH will occur. The related interrupt request
flag, T1F, will then be reset and the EMI bit cleared to
disable further interrupts.
Oscillator Configuration
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1, if the stack is not full. To
return from the interrupt subroutine, a ²RET² or ²RETI²
instruction may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
These devices provide three types of system oscillator
circuits, an crystal oscillator, an RC oscillator and a
32768Hz crystal oscillator, the choice crystal or RC oscillator is determined by configuration option.
If an RC oscillator is used, an external resistor, whose
resistance must range from 130kW to 2.5MW, should be
connected between OSC1 and VSS. The RC oscillator
provides the most cost effective solution, however, the
frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is,
therefore, not suitable for timing sensitive operations
where an accurate oscillator frequency is desired.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
The other oscillator circuit is designed for the real time
clock. For this device, only a 32768Hz crystal oscillator
can be used. The crystal should be connected between
OSC3 and OSC4.
The RTC oscillator circuit can be controlled to start up
quickly by setting the ²QOSC² bit (bit 4 of mode). It is
recommended to turn on the quick oscillating function at
power on until the RTC oscillator is stable, and then turn
it off after 2 seconds to reduce power consumption.
The timer/event counter 0 interrupt request flag (T0F),
The timer/event counter 1 interrupt request flag (T1F),
external interrupt request flag (EIF); enable timer/event
counter 0 interrupt bit (ET0I), enable timer/event counter 1 interrupt bit (ET1I), enable external interrupt bit
(EEI), enable master interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in
the data memory. EMI, EEI, ET0I, ET1I are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once
the interrupt request flags, T0F, T1F and EIF, are set,
they will remain in the INTC register until the interrupts
are serviced or cleared by a software instruction.
V
The WDT oscillator is a free running on-chip RC oscillator, and requires no external components. Although
when the system enters the power down mode, the system clock stops, the WDT oscillator will keep running
with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by a configuration option to conserve power.
D D
4 7 0 p F
O S C 1
R
O S C
fS
Y S
O S C 2
/4
R C
O s c illa to r
1 0 p F
O S C 3
O S C 1
O S C 4
O S C 2
3 2 7 6 8 H z
C r y s ta l O s c illa to r
C r y s ta l O s c illa to r
System Oscillator
Rev. 1.00
10
July 27, 2007
HT48R54A
Watchdog Timer - WDT
The WDT time-out under normal mode or slow mode will
initialize a ²chip reset² and set the status bit ²TO². But in
the idle mode, that is after a HALT instruction is executed, the time-out will initialize a ²warm reset² and only
the program counter and stack pointer are reset to 0.
The WDT clock source is implemented by a internal WDT
OSC, the external 32768Hz (fRTC) or the instruction clock
(system clock divided by 4), the choice of which is determined by configuration option. This timer is designed to
prevent software malfunctions or sequences jumping to
an unknown location with unpredictable results. The
Watchdog can be disabled by a configuration option. If
the Watchdog Timer is disabled, all the executions related to WDT will result in no operation.
To clear the WDT contents (not including the 4-bit divider and the 8-stage prescaler), three methods are
adopted; an external reset (a low level to RES pin), software instruction and a ²HALT² instruction.
The software instruction includes a ²CLR WDT² instruction, and the instruction pair ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one can
be active depending on the configuration option ²WDT²
instruction. If the ²CLR WDT² is selected (i.e. One clear
instruction), any execution of the CLR WDT instruction
will clear the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. two clear instructions),
these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip as a result
of a time-out.
If the device operates in a noisy environment, using the
on-chip WDT OSC or 32768Hz crystal oscillator is
strongly recommended.
When the WDT clock source is selected, it will be first divided by 16 (4-stage), and then divided by the TMR0C
prescaler (8-stage), after that, divided by 512 (9-stage)
to get the nominal time-out period. By using the TMR0C
prescaler, longer time-out periods can be realized. Writing data to PSC2, PSC1, PSC0 can give different
time-out periods. The WDT OSC period is 65ms. This
time-out period may vary with temperature, VDD and
process variations. The WDT OSC keep running in any
operation mode.
Operation Mode
The device support two system clocks and three operation modes. The system clock can be either an RC/XTAL
oscillator or a 32768Hz RTC. The three operational
modes are, Normal, Slow, or Idle mode. These are all
selected by software.
If the instruction clock (system clock/4) is selected as
the WDT clock source, the WDT operates in the same
manner.
If the WDT clock source is the 32768Hz, the WDT also
operates in the same manner.
S y s te m
C lo c k /4
3 2 7 6 8 H z
O p tio n
S e le c t
fS
4 - B it D iv id e r
8 - S ta g e P r e s c a le r
W D T O S C
8 -to -1 M U X
P S C 2 ~ P S C 0
9 - B it C o u n te r
W D T T im e - o u t
Watchdog Timer
Bit No.
Label
Function
0
MODS
System clock high/low mode select bit
0= RC/XTAL system clock select
1= 32768Hz system clock select and RC/XTAL system clock stop
Note that if the 32768Hz system clock is selected, then the WDT clock source configuration option must also select the 32768Hz oscillator as its clock source, otherwise unpredictable system operation may occur.
1, 2, 3
¾
4
QOSC
5, 6, 7
¾
Unused bit, read as ²0²
32768Hz OSC quick start-up
0=quick start; 1=slow start
Unused bit, read as ²0²
MODE (20H) Register
Rev. 1.00
11
July 27, 2007
HT48R54A
Mode
System Clock
HALT Instruction
MODS
RC Oscillator
32768Hz
Normal
RC/XTAL oscillator
No Executed
0
On
On
Slow
32768Hz
No Executed
1
Off
On
Idle
HALT
Be executed
x
Off
On
Operation Mode
Power Down Operation - HALT
The RTC oscillator will keep running when the device is
in the HALT mode, if the RTC oscillator is enabled.
The HALT mode is entered using the ²HALT² instruction
and results in the following:
Reset
· The system oscillator will be turned off but the WDT
There are three ways in which a reset can occur:
remains operational if its clock source is the internal
WDT oscillator.
· The contents of the on chip RAM and registers remain
unchanged.
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
· The WDT will be cleared. The WDT will resume count-
A the time-out during a HALT is different from the other
chip reset conditions, since it can perform a ²warm re set² that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions.
Most registers are reset to their ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
ing, if the WDT clock souce is the internal WDT oscillator.
· All of the I/O ports will maintain their original status.
· The PDF flag will be set and the TO flag will be cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the reason behind the reset can be determined. The PDF flag is cleared by a system power-up or
executing the ²CLR WDT² instruction and is set when
executing the ²HALT² instruction. The TO flag is set if
the WDT time-out occurs, and causes a wake-up that
only resets the program counter and stack pointer, the
other circuits remain in their original status.
TO PDF
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each port
A pin can be independently selected to wake up the device via configuration options. If awakened by an I/O
port stimulus, the program will resume execution at the
next instruction. If awakened by an interrupt, two sequences may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is
set to ²1² before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 system clock periods to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² stands for ²unchanged²
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
H A L T
W a rm
R e s e t
W D T
R E S
O S C 1
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Rev. 1.00
RESET Conditions
C o ld
R e s e t
R e s e t
Reset Configuration
12
July 27, 2007
HT48R54A
V
To guarantee that the system oscillator is running and
stable, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system
reset (power-up, WDT time-out or RES reset) or when
the system awakes from the HALT state.
R E S
B a s ic
R e s e t
C ir c u it
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
R E S
1 0 k W
0 .1 m F
H i-n o is e
R e s e t
C ir c u it
Reset Circuit
Note: Most applications can use the Basic Reset Circuit
as shown, however for applications with extensive noise,
it is recommended to use the Hi-noise Reset Circuit.
The functional unit chip reset status are shown below.
Interrupt
1 0 0 k W
0 .1 m F
An extra option load time delay is added during a system
reset (power-up, WDT time-out at normal mode or RES
reset).
000H
D D
0 .0 1 m F
1 0 0 k W
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
Program Counter
V
D D
Timer/Event Counter Off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
The states of the registers are summarised in the table.
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
--00 -000
--00 -000
--00 -000
--00 -000
--uu -uuu
Register
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1000
0000 1000
0000 1000
0000 1000
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
MODE
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Rev. 1.00
13
July 27, 2007
HT48R54A
Timer/Event Counter 0
occurs, the counter is reloaded from the timer/event
counter 0 preload register and at the same time generates the interrupt request flag, T0F; bit 5 of the INTC.
Two Timer/event counters are implemented in the
microcontroller. The timer/event counter 0 contains an
8-bit programmable count-up counter whose clock may
be sourced from an external source or from the system
clock/4 or fSP.
In the pulse width measurement mode with the T0ON
and T0E bits equal to one, once it goes from low to high
(or high to low if the T0E bits is ²0²) it will start counting
until the TMR0 returns to the original level and resets the
T0ON. The measured result will remain in the
timer/event counter 0 even if the activated transient occurs again. In other words, only one cycle measurement
can be done. Until setting the T0ON, the cycle measurement will function again as long as it receives further
transient pulse. Note that, in this operating mode, the
timer/event counter 0 starts counting not according to
the logic level but according to the transient edges. In
the case of counter overflows, the counter is reloaded
from the timer/event counter 0 preload register and issues the interrupt request just like the other two modes.
To enable the counting operation, the timer 0 ON bit
(T0ON; bit 4 of the TMR0C) should be set to ²1². In the
pulse width measurement mode, the T0ON will be
cleared automatically after the measurement cycle is
completed. But in the other two modes the T0ON can
only be reset by instructions. The overflow of the
timer/event counter 0 is one of the wake-up sources. No
matter what the operation mode is, writing a ²0² to ET0I
can disable the corresponding interrupt services.
The fSP clock source is implemented by the WDT OSC,
an external 32768Hz (fRTC) or an instruction clock (system clock divided by 4), determined by configuration option. If one of these three source is selected, it will be
first divided by 16 (4-stage), and then divided by the
TMR0C prescaler (8-stage) to get an fSP output period.
By using the TMR0C prescaler, longer time-out periods
can be realized. Writing data to P0SC2, P0SC1, P0SC0
can give different fSP output periods.
Using internal clock sources, there are 2 reference
time-bases for the timer/event counter 0. The internal
clock source can be sourced from fSYS/4 or fSP via a configuration options. Using an external clock input allows
the user to count external events, measure time
intervals or pulse widths, or generate an accurate time
base, while using the internal clock allows the user to
generate an accurate time base.
There are two registers related to the timer/event counter 0; TMR0 ([0DH]) and TMR0C ([0EH]). Writing to
TMR0 places the start value in the timer/event counter 0
preload register while reading the TMR0 register retrieves the contents of the timer/event counter 0. The
TMR0C register is a timer/event counter 0 control register which defines some options.
In the case of timer/event counter 0 OFF condition, writing data to the timer/event counter 0 preload register will
also reload that data to the timer/event counter 0. But if
the timer/event counter 0 is turned on, data written to it
will only be kept in the timer/event counter 0 preload register. The timer/event counter 0 will still operate until
overflow occurs (a timer/event counter 0 reloading will
occur at the same time). When the timer/event counter 0
(reading TMR0) is read, the clock will be blocked to
avoid errors. As clock blocking may result in a counting
error, this must be taken into consideration by the programmer. The bit2~bit0 of the TMR0C can be used to
define the pre-scaling stages of the internal clock
sources of the timer/event counter 0. The definitions are
as shown.
The T0M0, T0M1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source must comes from the external timer pin, TMR0. The timer mode functions as a
normal timer with the clock source coming from the fINT
clock. The pulse width measurement mode can be used
to count the duration of a high or low-level signal on the
external timer pin, TMR0. The counting is based on the
fINT clock.
In the event count or timer mode, once the timer/event
counter 0 is enabled, it begins counting form the value
placed in the timer/event counter 0. From this initial
value it will count up to a value of FFH. Once an overflow
fS Y S /4
R T C O S C
W D T O S C
M
U
X
fS
4 - b it D iv id e r
fS /1 6
(1 /2 ~ 1 /2 5 6 )
8 - s ta g e P r e s c a le r
fS
fS
8 -1 M U X
C o n fig u r a tio n O p tio n
P 0 S C 2 ~ P 0 S C 0
9 - B it C o u n te r
/4
Y S
P
M
U
f IN
W D T T im e - o u t
T
D a ta B u s
X
T 0 M 1
T 0 M 0
C o n fig u r a tio n
O p tio n
T M R 0
8 - B it T im e r /E v e n t C o u n te r 0
P r e lo a d R e g is te r
R e lo a d
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
8 - B it T im e r /E v e n t
C o u n te r 0 (T M R 0 )
O v e r flo w
to In te rru p t
Timer/Event Counter 0
Rev. 1.00
14
July 27, 2007
HT48R54A
Bit No.
0
1
2
Label
P0SC0
P0SC1
P0SC2
3
T0E
4
T0ON
5
¾
6
7
T0M0
T0M1
Function
Define the prescaler stages, P0SC2, P0SC1, P0SC0=
000: fSP=fS/32
001: fSP=fS/64
010: fSP=fS/128
011: fSP=fS/256
100: fSP=fS/512
101: fSP=fS/1024
110: fSP=fS/2048
111: fSP=fS/4096
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
To enable or disable timer 0 counting
(0=disable; 1=enable)
Unused bit, read as ²0²
Define the operating mode, T0M1, T0M0=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
Timer/Event Counter 1
flow occurs, the counter is reloaded from the timer/event
counter 1 preload register and generates the corresponding interrupt request flag (T1F; bit 6 of INTC) at
the same time.
Using the internal clock sources, there are 2 reference
time-bases for timer/event counter 1. The internal clock
source can be selected as coming from fSYS or fRTC (selected by T1S bit). The external clock input allows the
user to count external events, measure time intervals or
pulse widths, or to generate an accurate time base and
PFD signals.
In pulse width measurement mode with the T1ON and
T1E bits are equal to one, once the TMR1 has received
a transition from low to high (or high to low if the T1E bit
is 0) it will start counting until the TMR1 returns to the
original level and reset the T1ON. The measured result
will remain in the timer/event counter 1 even if the activated transition occurs again. In other words, only one
cycle measurement can be done. Until setting the
T1ON, the cycle measurement will function again as
long as it receives further transition pulse. Note that, in
this operating mode, the timer/event counter 1 starts
counting not according to the logic level but according to
the transition edges. In the case of counter overflows,
the counter 1 is reloaded from the timer/event counter 1
pre-load register and issues the interrupt request just
like the other two modes.
There are 2 registers related to timer/event counter 1;
TMR1(10H), TMR1C(11H). In timer/event counter 1
counting mode (T1ON=1), writing TMR1 will only put the
written data to pre-load register (8 bits). The timer/event
counter 1 pre-load register is changed by each writing
TMR1 operations. Reading TMR1 will also latch the
TMR1 to the destination. The TMR1C is the timer/event
counter 1 control register, which defines the operating
mode, counting enable or disable and active edge.
The T1M0, T1M1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR1) pin. The timer mode functions as a normal timer
with the clock source coming from the fINT1 clock. The
pulse width measurement mode can be used to count
the high or low level duration of the external signal
(TMR1). The counting is based on the fINT1 clock.
To enable the counting operation, the timer ON
bit(T1ON; bit 4 of TMR1C) should be set to 1. In the
pulse width measurement mode, the T1ON will be
cleared automatically after the measurement cycle is
complete. But in the other two modes the T1ON can only
be reset by instructions. The overflow of the timer/event
counter 1 is one of the wake-up sources. No matter what
the operation mode is, writing a 0 to ET1I can disabled
the corresponding interrupt service.
In the event count or timer mode, once the timer/event
counter 1 starts counting, it will count from the current
contents in the timer/event counter 1 to FFH. Once over-
Rev. 1.00
15
July 27, 2007
HT48R54A
When the timer/event counter 1 (reading TMR1) is read,
the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration by the programmer.
In the case of timer/event counter 1 OFF condition, writing data to the timer/event counter 1 pre-load register
will also load the data to timer/event counter 1. But if the
timer/event counter 1 is turned on, data written to the
timer/event counter 1 will only be kept in the timer/event
counter 1 pre-load register. The timer/event counter 1
will still operate until the overflow occurs (a timer/event
counter 1 reloading will occur at the same time).
fS
Y S
fR
T C
M
U
fS 1
The bit 0~2 of the TMR1C can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter 1. The definitions are as shown.
8 - s ta g e P r e s c a le r
X
f IN
8 -1 M U X
D a ta B u s
T 1
T 1 M 1
T 1 M 0
T 1 S
P S 1 C 2 ~ P S 1 C 0
T M R 1
T im e r /E v e n t C o u n te r 1
P r e lo a d R e g is te r
R e lo a d
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
T im e r /E v e n t C o u n te r
(T M R 1 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
¸ 2
P F D
Timer/Event Counter 1
Bit No.
0
1
2
Label
P1SC0
P1SC1
P1SC2
Function
Define the prescaler stages, P1SC2, P1SC1, P1SC0=
000: fINT1=fS1/2
001: fINT1=fS1/4
010: fINT1=fS1/8
011: fINT1=fS1/16
100: fINT1=fS1/32
101: fINT1=fS1/64
110: fINT1=fS1/128
111: fINT1=fS1/256
3
T1E
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T1ON
To enable or disable timer 1 counting (0=disable; 1=enable)
5
T1S
6
7
T1M0
T1M1
Select clock source of TMR1 (0=fSYS; 1=fRTC)
Define the operating mode, T1M1, T1M0=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
Rev. 1.00
16
July 27, 2007
HT48R54A
Input/Output Ports
The PD and PE can be used for output operation only.
Setting its output register high which effectively places
its NMOS output transistor in high impedance state. Resetting output register to low will force to output low
state.
There are 16 bidirectional input/output (PA, PB) lines
and 8 PMOS (PC), 16 NMOS (PD, PE) output lines in
the microcontroller, labeled from PA to PE, which are
mapped to the data memory of [12H], [14H], [16H],
[18H] and [1AH] respectively. All pins on PA~PB can be
used for both input and output operations.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high options). Each bit of these input/output latches can be set
or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H, 18H or 1AH) instructions.
For the input operation, these ports are non-latching,
that is, the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]² (m=12H, 14H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²LR [m].i²,
²CPL [m]², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or the accumulator.
The PA and PB have their own control registers (PAC,
PBC) to control the input/output configuration. These
two control registers are mapped to locations 13H and
15H. CMOS/PMOS output or Schmitt trigger input with
structures can be reconfigured dynamically under software control. The control registers specifies which pin
are set as input and which are set as outputs. To setup a
pin as an input the corresponding bit of the control register must be set high, for an output it must be set low.
Each line of port A has the capability of waking-up the
device.
There is a pull-high option available for PA0~PA7 lines
(port option). Once the pull-high option of an I/O line is
selected, the I/O line have pull-high resistor. Otherwise,
the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
The PC can be used for output operation only. Resetting
its output register to low will effectively places its PMOS
output transistor in high impedance state. Setting output
register to high will force PC to output high state.
The external interrupt pin INT is pin-shard with output
pin PD0.
V
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
Q
D
C K
D D
P u ll- H ig h
O p tio n
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P A
P A
P A
P A
P A
P A
D a ta B it
Q
D
C K
S
Q
M
P A 7 o r P A 0
P F D o r B Z /B Z
M
R e a d D a ta R e g is te r
S y s te m
U
U
0 /B
1 /B
2 /T
3 /T
4 ~
7 /P
Z
Z
M R 0
M R 1
P A 6
F D
X
B Z o r P F D
O p tio n
X
W a k e -u p
W a k e - u p O p tio n
T M R 0 fo r P A 2 o n ly
T M R 1 fo r P A 3 o n ly
PA Input/Output Ports
Rev. 1.00
17
July 27, 2007
HT48R54A
V
C o n tr o l B it
Q
D
D a ta B u s
W r ite C o n tr o l R e g is te r
C K
D D
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
P B 0 ~ P B 7
Q
M
R e a d D a ta R e g is te r
U
X
PB Input/Output Ports
V
D D
D a ta B it
Q
D
D a ta B u s
W r ite D a ta R e g is te r
C K
Q
R
C h ip R e s e t
P C 0 ~ P C 7
R e a d D a ta R e g is te r
PC Output Ports
P D 0 /IN T
D a ta B it
D a ta B u s
W r ite D a ta R e g is te r
Q
D
C K
S
Q
C h ip R e s e t
R e a d D a ta R e g is te r
IN T In p u t
PD0 Input/Output Port
P D 1 ~ P D 7
P E 0 ~ P E 7
D a ta B it
D a ta B u s
W r ite D a ta R e g is te r
Q
D
C K
S
Q
C h ip R e s e t
R e a d D a ta R e g is te r
PD1~PD7, PE Output Ports
Rev. 1.00
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July 27, 2007
HT48R54A
Buzzer Output
The PA0 and PA1 are pin-shared with BZ and BZ signal, respectively. If the BZ/BZ option is selected, the output signal
in output mode of PA0/PA1 will be the buzzer signal generated by Multi-function timer. The input mode is always remained in its original functions. Once the BZ/BZ option is selected, the buzzer output signals are controlled by the PA0
data register only.
The I/O functions of PA0/PA1 are shown below.
PAC Register
PAC0
PAC Register
PAC1
PA Data Register
PA0
PA Data Register
PA1
0
0
1
x
PA0=BZ, PA1=BZ
0
0
0
x
PA0=0, PA1=0
0
1
1
x
PA0=BZ, PA1=input
0
1
0
x
PA0=0, PA1=input
1
0
x
D
PA0=input, PA1=0
1
1
x
x
PA0=input, PA1=input
Note:
Output Function
²x² stands for don¢t care
²D² stands for Data ²0² or ²1²
PFD Output
The PA7 is pin-shared with the PFD signal. If the PFD option is selected, the output signal in output mode of PA7 will be
the PFD signal generated by timer/event counter 1 overflow signal. The input mode is always remaining its original
functions. Once the PFD option is selected, the PFD output signal is controlled by PA7 data register only. The I/O functions of PA7 are shown below.
Note:
I/O Mode
I/P (Normal)
O/P (Normal)
I/P (PFD)
O/P (PFD)
PA7
Logical Input
Logical Output
Logical Input
PFD (Timer on)
The PFD frequency is the timer/event counter 1 overflow frequency divided by 2.
The definitions of the PFD control signal and PFD output frequency are listed in the following table.
Note:
Timer
Timer Preload Value
PA7 Data Register
PA7 Pad State
PFD Frequency
OFF
X
0
0
X
OFF
X
1
U
X
ON
N
0
0
X
ON
N
1
PFD
fTMR1/[2´(M-N)]
²X² stands for unused
²U² stands for unknown
²M² is ²65536² for PFD
²N² is the preload value for the timer/event counter 1
²fTMR1² is input clock frequency for timer/event counter 1
Rev. 1.00
19
July 27, 2007
HT48R54A
Low Voltage Reset - LVR
The LVR includes the following specifications:
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally.
· The low voltage (0.9V~VLVR) has to remain in their
original state for more than 1ms. If the low voltage
state does not exceed 1ms, the LVR will ignore it and
do not perform a reset function.
· The LVR uses the ²OR² function with the external
RES signal to perform a chip reset.
The relationship between VDD and VLVR is shown below.
V D D
5 .5 V
V O P R
5 .5 V
2 .1 V
2 .2 V
V D D
5 .5 V
V
V O P R
5 .5 V
V D D
5 .5 V
V
L V R
V
L V R
3 .1 5 V
L V R
4 .2 V
2 .2 V
0 .9 V
Note:
V O P R
5 .5 V
2 .2 V
0 .9 V
0 .9 V
VOPR is the voltage range for proper chip operation at 4MHz system clock.
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of
1024 system clock pulses before entering the normal operation.
*2: Since a low voltage has to be maintained for more than 1ms, therefore a 1ms delay is provided before
entering the reset mode.
Rev. 1.00
20
July 27, 2007
HT48R54A
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure having
a proper functioning system.
Items
Options
1
OSC type selection: RC or crystal
2
PA0~PA7 bit wake-up enable or disable (by bit)
3
PA pull-high enable or disable (by port)
4
WDT clock source: WDT oscillator or fSYS/4 or 32768Hz oscillator
5
WDT enable or disable
6
CLRWDT instructions: 1 or 2 instructions
7
Timer/event counter 0 clock sources: fSYS/4 or fSP
8
LVR enable or disable
9
LVR voltage: 2.1V or 3.15V or 4.2V
10
Buzzer function: single BZ enable or both BZ and BZ or both disable
11
Buzzer frequency: fS/2, fS/4, fS/8, fS/16
12
PA7: Normal I/O or PFD output
Rev. 1.00
21
July 27, 2007
HT48R54A
Application Circuits
V
D D
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
R E S
0 .1 m F
P
/B
/B
R
R
Z
Z
A 6
F D
1
0
P B 0 ~ P B 7
V
O S C 1
4 7 0 p F
P D 0 /IN T
P D 1 ~ P D 7
R
P E 0 ~ P E 7
O S C
C 1
O S C 2
3 2 7 6 8 H z
D D
P C 0 ~ P C 7
V S S
O S C
C ir c u it
P A
P A
P
P A 0
P A 1
2 /T M
3 /T M
A 4 ~ P
A 7 /P
O S C 1
fS
Y S
/4
C 2
1 0 p F
O s c illa to r
< 2 .4 M W
O S C 1
C r y s ta l/R e s o n a to r
S y s te m O s c illa to r
O S C 2
F o r R 1 , C 1 , C 2 s e e n o te
O S C
O S C 4
S C
O S C 2
R 1
O S C 3
R C S y s te m
1 3 0 k W < R O
C ir c u it
H T 4 8 R 5 4 A
Note:
1. Crystal/resonator system oscillators
For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For
resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is
not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator
when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2
should be selected in consultation with the crystal/resonator manufacturer specifications.
2. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
3. For applications where noise may interfere with the reset circuit and for details on the oscillator external
components, refer to Application Note HA0075E for more information.
Rev. 1.00
22
July 27, 2007
HT48R54A
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.00
23
July 27, 2007
HT48R54A
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.00
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
24
July 27, 2007
HT48R54A
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
25
July 27, 2007
HT48R54A
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
26
July 27, 2007
HT48R54A
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
27
July 27, 2007
HT48R54A
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
28
July 27, 2007
HT48R54A
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
29
July 27, 2007
HT48R54A
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
30
July 27, 2007
HT48R54A
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
31
July 27, 2007
HT48R54A
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
32
July 27, 2007
HT48R54A
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
July 27, 2007
HT48R54A
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
July 27, 2007
HT48R54A
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
July 27, 2007
HT48R54A
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
36
July 27, 2007
HT48R54A
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
37
July 27, 2007
HT48R54A
Package Information
44-pin QFP (10´10) Outline Dimensions
H
C
D
G
2 3
3 3
I
3 4
2 2
L
F
A
B
E
1 2
4 4
K
a
J
1
Symbol
Rev. 1.00
1 1
Dimensions in mm
Min.
Nom.
Max.
A
13
¾
13.4
B
9.9
¾
10.1
C
13
¾
13.4
D
9.9
¾
10.1
E
¾
0.8
¾
F
¾
0.3
¾
G
1.9
¾
2.2
H
¾
¾
2.7
I
0.25
¾
0.5
J
0.73
¾
0.93
K
0.1
¾
0.2
L
¾
0.1
¾
a
0°
¾
7°
38
July 27, 2007
HT48R54A
52-pin QFP (14´14) Outline Dimensions
C
H
D
3 9
G
2 7
I
2 6
4 0
F
A
B
E
1 4
5 2
K
J
1
Symbol
Rev. 1.00
1 3
Dimensions in mm
Min.
Nom.
Max.
A
17.3
¾
17.5
B
13.9
¾
14.1
C
17.3
¾
17.5
D
13.9
¾
14.1
E
¾
1
¾
F
¾
0.4
¾
G
2.5
¾
3.1
H
¾
¾
3.4
I
¾
0.1
¾
J
0.73
¾
1.03
K
0.1
¾
0.2
a
0°
¾
7°
39
July 27, 2007
HT48R54A
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
40
July 27, 2007