Hitachi HM62256ALSP-15 32,768-word x 8-bit high speed cmos static ram Datasheet

HM62256A Series
Maintenance only
32,768-word × 8-bit High Speed CMOS Static RAM
The Hitachi HM62256A is a CMOS static RAM
organized 32-kword × 8-bit. It realizes higher
performance and low power consumption by
employing 0.8 µm Hi-CMOS process technology.
The device, packaged in a 8 × 14 mm TSOP with
thickness of 1.2 mm, 450-mil SOP (foot print pitch
width), 600-mil plastic DIP, or 300-mil plastic DIP,
is available for high density mounting. TSOP
package is suitable for cards, and reverse type
TSOP is also provided. It offers low power
standby power dissipation; therefore, it is suitable
for battery back up system.
Features
• High speed: Fast Access time 85/100/120/150 ns
(max)
• Low Power
Standby: 5 µW (typ) (L/L-SL version)
Operation: 40 mW (typ) (f = 1 MHz)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output: Three state
output
• Directly TTL compatible: All inputs and outputs
• Capability of battery back up operation
Ordering Information
Type No.
Access time Package
——————————————————————–
HM62256AP-8
85 ns
600-mil
HM62256AP-10
100 ns
28-pin
HM62256AP-12
120 ns
plastic DIP
HM62256AP-15
150 ns
(DP-28)
————————————————–
HM62256ALP-8
85 ns
HM62256ALP-10
100 ns
HM62256ALP-12
120 ns
HM62256ALP-15
150 ns
————————————————–
HM62256ALP-8SL
85 ns
HM62256ALP-10SL
100 ns
HM62256ALP-12SL
120 ns
HM62256ALP-15SL
150 ns
——————————————————————–
HM62256ASP-8
85 ns
300-mil
HM62256ASP-10
100 ns
28-pin
HM62256ASP-12
120 ns
plastic DIP
HM62256ASP-15
150 ns
(DP-28NA)
————————————————–
HM62256ALSP-8
85 ns
HM62256ALSP-10
100 ns
HM62256ALSP-12
120 ns
HM62256ALSP-15
150 ns
————————————————–
HM62256ALSP-8SL 85 ns
HM62256ALSP-10SL 100 ns
HM62256ALSP-12SL 120 ns
HM62256ALSP-15SL 150 ns
——————————————————————–
HM62256AFP-8T
85 ns
450-mil
HM62256AFP-10T
100 ns
28-pin
HM62256AFP-12T
120 ns
plastic SOP
HM62256AFP-15T
150 ns
(FP-28DA)
————————————————–
HM62256ALFP-8T
85 ns
HM62256ALFP-10T
100 ns
HM62256ALFP-12T
120 ns
HM62256ALFP-15T
150 ns
————————————————–
HM62256ALFP-8SLT 85 ns
HM62256ALFP-10SLT 100 ns
HM62256ALFP-12SLT 120 ns
HM62256ALFP-15SLT 150 ns
——————————————————————–
Note: This device is not available for new application.
1
HM62256A Series
HM62256A Series
TSOP Series
Type No.
Access time Package
——————————————————————–
HM62256ALT-8
85 ns
8 mm × 14 mm
HM62256ALT-10
100 ns
32-pin TSOP
HM62256ALT-12
120 ns
(normal type)
HM62256ALT-15
150 ns
(TFP-32DA)
———————————————–
HM62256ALT-8SL 85 ns
HM62256ALT-10SL 100 ns
HM62256ALT-12SL 120 ns
HM62256ALT-15SL 150 ns
——————————————————————–
Type No.
Access time Package
——————————————————————–
HM62256ALR-8
85 ns
8 mm × 14 mm
HM62256ALR-10
100 ns
32-pin TSOP
HM62256ALR-12
120 ns
(reverse type)
HM62256ALR-15
150 ns
(TFP-32DAR)
———————————————–
HM62256ALR-8SL 85 ns
HM62256ALR-10SL 100 ns
HM62256ALR-12SL 120 ns
HM62256ALR-15SL 150 ns
——————————————————————–
Pin Arrangement
HM62256AP/AFP/ASP Series
A14
1
28
VCC
A12
2
27
WE
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CS
A0
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
VSS
14
15
I/O3
(Top view)
HM62256AR Series
HM62256AT Series
OE
A11
NC
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
NC
A4
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
2
A10
CS
NC
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
NC
A1
A2
A3
A4
NC
A5
A6
A7
A12
A14
VCC
WE
A13
A8
A9
NC
A11
OE
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Top view)
A2
A1
NC
A0
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
NC
CS
A10
HM62256A Series
HM62256A Series
Pin Description
Symbol
Function
——————————————————————–
A0 – A14
Address
——————————————————————–
I/O0 – I/O7
Input/output
——————————————————————–
CS
Chip select
——————————————————————–
WE
Write enable
——————————————————————–
Symbol
Function
——————————————————————–
OE
Output enable
——————————————————————–
NC
No connection
——————————————————————–
VCC
Power supply
——————————————————————–
VSS
Ground
——————————————————————–
Block Diagram
A5
V CC
A4
V SS
A3
A11
A9
•
•
•
•
•
•
A8
•
A12
•
Row
Decoder
Memory Matrix
512 × 512
•
•
A7
A6
I/O0
•
•
•
•
•
Column I/O
•
•
•
•
•
•
•
•
Input
Data
Control
Column Decoder
•
•
I/O7
•
•
A0 A1 A2 A10 A13 A14
•
•
•
•
CS
WE
Timing Pulse Generator
Read/Write Control
OE
3
HM62256A Series
HM62256A Series
Function Table
WE
CS
OE
Mode
VCC current
I/O pin
Ref. cycle
———————————————————————————————————————————————–
X
H
X
Not selected
ISB, ISB1
High-Z
—
———————————————————————————————————————————————–
H
L
H
Output disable
ICC
High-Z
—
———————————————————————————————————————————————–
H
L
L
Read
ICC
Dout
Read cycle (1)–(3)
———————————————————————————————————————————————–
L
L
H
Write
ICC
Din
Write cycle (1)
———————————————————————————————————————————————–
L
L
L
Write
ICC
Din
Write cycle (2)
———————————————————————————————————————————————–
Note: X: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
———————————————————————————————————————————————–
Voltage on any pin relative to VSS
VT
–0.5*1 to +7.0
V
———————————————————————————————————————————————–
Power dissipation
PT
1.0
W
———————————————————————————————————————————————–
Operating temperature
Topr
0 to +70
°C
———————————————————————————————————————————————–
Storage temperature
Tstg
–55 to +125
°C
———————————————————————————————————————————————–
Storage temperature under bias
Tbias
–10 to +85
°C
———————————————————————————————————————————————–
Note: 1. VT min = –3.0 V for pulse half-width ≤ 50 ns
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
———————————————————————————————————————————————–
Supply voltage
VCC
4.5
5.0
5.5
V
———————————————————————————————–
VSS
0
0
0
V
———————————————————————————————————————————————–
Input high (logic 1) voltage
VIH
2.2
—
6.0
V
———————————————————————————————————————————————–
Input low (logic 0) voltage
VIL
–0.5*1
—
0.8
V
———————————————————————————————————————————————–
Note: 1. VIL min = –3.0 V for pulse half-width ≤ 50 ns
4
HM62256A Series
HM62256A Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
Parameter
Symbol Min
Typ*1 Max
Unit Test conditions
———————————————————————————————————————————————–
Input leakage current
|ILI|
—
—
1
µA
Vin = VSS to VCC
———————————————————————————————————————————————–
Output leakage current
|ILO|
—
—
1
µA
CS = VIH or OE = VIH or WE = VIL,
VI/O = VSS to VCC
———————————————————————————————————————————————–
Operating VCC current
ICC
—
6
15
mA
CS = VIL, others = VIH/VIL
Iout = 0 mA
——————————————————————————————————————————
HM62256A-8 ICC1
—
33
50
mA
min cycle, duty = 100%, II/O = 0 mA
HM62256A-10
—
30
50
CS = VIL, others = VIH/VIL
HM62256A-12
—
27
45
HM62256A-15
—
24
40
——————————————————————————————————————————
ICC2
—
5
15
mA
Cycle time = 1µs, II/O = 0 mA
CS = VIL, VIH = VCC, VIL = 0
———————————————————————————————————————————————–
Standby VCC current
ISB
—
0.3
2
mA
CS = VIH
———————————————————————————————————
ISB1
—
0.01
1
mA
Vin ≥ 0 V
—————————————— CS ≥ VCC – 0.2 V
—
0.3*2
100*2 µA
——————————————
—
0.3*3
50*3
µA
———————————————————————————————————————————————–
Output low voltage
VOL
—
—
0.4
V
IOL = 2.1 mA
———————————————————————————————————————————————–
Output high voltage
VOH
2.4
—
—
V
IOH = –1.0 mA
———————————————————————————————————————————————–
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
3. This characteristics is guaranteed only for L-SL version.
Capacitance (Ta = 25°C, f = 1 MHz)*1
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
———————————————————————————————————————————————–
Input capacitance
Cin
—
—
6
pF
Vin = 0 V
———————————————————————————————————————————————–
Input/output capacitance
CI/O
—
—
8
pF
VI/O= 0 V
———————————————————————————————————————————————–
Note: 1. This parameter is sampled and not 100% tested.
5
HM62256A Series
HM62256A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: 0.8 V to 2.4 V
• Input and output timing refernce levels: 1.5 V
• Input rise and fall times: 5 ns
• Output load: 1 TTL Gate + CL (100 pF)
(Including scope & jig)
Read Cycle
HM62256A-8 HM62256A-10 HM62256A-12 HM62256A-15
—————– —————– —————– —————–
Parameter
Symbol Min Max Min Max Min Max Min Max
Unit
Note
———————————————————————————————————————————————–
Read cycle time
tRC
85
—
100 —
120 —
150 —
ns
———————————————————————————————————————————————–
Address access time
tAA
—
85
—
100 —
120 —
150
ns
———————————————————————————————————————————————–
Chip select
tACS
—
85
—
100 —
120 —
150
ns
access time
———————————————————————————————————————————————–
Output enable to
tOE
—
45
—
50
—
60
—
70
ns
output valid
———————————————————————————————————————————————–
Chip selection to
tCLZ
10
—
10
—
10
—
10
—
ns
2
output in low-Z
———————————————————————————————————————————————–
Output enable to
tOLZ
5
—
5
—
5
—
5
—
ns
2
output in low-Z
———————————————————————————————————————————————–
Chip deselection to
tCHZ
0
30
0
35
0
40
0
50
ns
1, 2
output in high-Z
———————————————————————————————————————————————–
Output disable to
tOHZ
0
30
0
35
0
40
0
50
ns
1, 2
output in high-Z
———————————————————————————————————————————————–
Output hold from
tOH
5
—
10
—
10
—
10
—
ns
address change
———————————————————————————————————————————————–
6
HM62256A Series
HM62256A Series
Read Timing Waveform (1) *3
t RC
Address
t AA
t ACS
CS
t CLZ *2
t OH
t OE
t OLZ
*2
OE
t OHZ*1 *2
t CHZ *1 *2
Dout
Valid Data
Read Timing Waveform (2) *3 *4 *6
t RC
Address
t OH
Dout
t OH
t AA
Valid Data
7
HM62256A Series
HM62256A Series
Read Timing Waveform (3) *3 *5 *6
CS
t ACS
t CHZ
t CLZ *2
Dout
*1,*2
Valid Data
Notes: 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit
conditions and are not referenced to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. WE is high for read cycle.
4. Device is continuously selected, CS = VIL.
5. Address Valid prior to or coincident with CS transition Low.
6. OE = VIL.
Write Cycle
HM62256A-8 HM62256A-10 HM62256A-12 HM62256A-15
—————– —————– —————– —————–
Parameter
Symbol Min Max Min Max Min Max Min Max
Unit
Note
———————————————————————————————————————————————–
85
—
100 —
120 —
150 —
ns
Write cycle time
tWC
———————————————————————————————————————————————–
75
—
80
—
85
—
100 —
ns
2
Chip selection to
tCW
end of write
———————————————————————————————————————————————–
0
—
0
—
0
—
0
—
ns
3
Address setup time
tAS
———————————————————————————————————————————————–
75
—
80
—
85
—
100 —
ns
Address valid to
tAW
end of write
———————————————————————————————————————————————–
55
—
60
—
70
—
90
—
ns
1
Write pulse width
tWP
———————————————————————————————————————————————–
0
—
0
—
0
—
0
—
ns
4
Write recovery time
tWR
———————————————————————————————————————————————–
0
30
0
35
0
40
0
50
ns
10
WE to output in high-Z tWHZ
———————————————————————————————————————————————–
40
—
40
—
50
—
60
—
ns
Data to write time
tDW
overlap
———————————————————————————————————————————————–
0
—
0
—
0
—
0
—
ns
Data hold from
tDH
write time
———————————————————————————————————————————————–
5
—
5
—
5
—
5
—
ns
10
Output active from
tOW
end of write
———————————————————————————————————————————————–
0
30
0
35
0
40
0
50
ns
10, 11
Output disable to
tOHZ
output in high-Z
———————————————————————————————————————————————–
8
HM62256A Series
HM62256A Series
Write Timing Waveform (1) (OE Clock)
t WC
Address
t WR *4
t AW
OE
t CW *2
CS
*6
t AS *3
t WP *1
WE
t OHZ *5 *10
Dout
t DW
Din
t DH
Valid Data
9
HM62256A Series
HM62256A Series
Write Timing Waveform (2) (OE Low Fixed)
t WC
Address
t WR*4
t CW *2
CS
*6
t AW
t WP *1
WE
t OH
*3
t AS
t OW *10
t WHZ*5 *10
*7
*8
Dout
t DW
t DH
*9
Din
Valid Data
Notes: 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the later
transition of CS going low or WE going low. A write ends at the earlier transition of CS
going high or WE going high. tWP is measured from the beginning of write to the end of
write.
2. tCW is measured from CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the earlier of WE or CS going high to the end of write cycle.
5. During this period, I/O pins are in the output state so that the input signals of the opposite
phase to the outputs must not be applied.
6. If the CS low transition occurs simultaneously with the WE low transition or after the WE
transition, the output remain in a high impedance state.
7. Dout is the same phase of the write data of this write cycle.
8. Dout is the read data of next address.
9. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals
of the opposite phase to the output must not be applied to them.
10. This parameter is sampled and not 100% tested.
11. tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit
conditions and are not referenced to output voltage levels.
10
HM62256A Series
HM62256A Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L/L-SL version.
Parameter
Symbol Min
Typ*1 Max
Unit Test conditions
———————————————————————————————————————————————–
VCC for data retention
VDR
2
—
—
V
CS ≥ VCC – 0.2 V, Vin ≥ 0 V
———————————————————————————————————————————————–
Data retention current
ICCDR
—
0.2
30*2
µA
VCC = 3.0 V, Vin ≥ 0 V
——————————————–
—
0.2
10*3
µA
CS ≥ VCC – 0.2 V
———————————————————————————————————————————————–
Chip deselect to data retention time tCDR
0
—
—
ns
See retention waveform
——————————————————————————————————––
Operation recovery time
tR
tRC*4 —
—
ns
———————————————————————————————————————————————–
Low VCC Data Retention Timing Waveform
Data retention mode
V CC
4.5 V
tR
t CDR
2.2 V
V DR
CS
0V
Notes: 1
2.
3.
4.
5.
CS ≥ VCC – 0.2 V
Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed.
20 µA max at Ta = 0 to +40°C. (only for L-version)
3 µA max at Ta = 0 to +40°C. (only for L-SL version)
tRC = read cycle time.
CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data
retention mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state.
11
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