ATMEL ATF1502AS-10AC44 High performance e2prom cpld Datasheet

Features
• High Density, High Performance Electrically Erasable Complex Programmable Logic
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Device
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44 pin
– 7.5 ns Maximum Pin-to-Pin Delay
– Registered Operation Up To 125 MHz
– Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
– D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic utilization by burying a register with a COM output
Advanced Power Management Features
– Automatic 3 mA Stand-By for “L” Version
– Pin-Controlled 4 mA Stand-By Mode (Typical)
– Programmable Pin-Keeper Inputs and I/Os
– Reduced-Power Feature Per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-pin PLCC; TQFP; and PQFP
Advanced EEPROM Technology
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-Up Immunity
JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
3.3 or 5.0V I/O pins
Security Fuse Feature
High
Performance
E2PROM CPLD
ATF1502AS
Preliminary
Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D - Latch Mode
Combinatorial Output with Registered Feedback within any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-Keeper” Option
VCC Power-Up Reset Option
Pull-Up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge Controlled Power Down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 0995A–04/98
1
44-Lead PLCC
Top View
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
6
5
4
3
2
1
44
43
42
41
40
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O/TDI
I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
VCC
I/O
I/O
18
19
20
21
22
23
24
25
26
27
28
44
43
42
41
40
39
38
37
36
35
34
I/O
I/O
I/O/PD1
VCC/PD2
GCK2/OE2/I
GCLR/I
OE1/I
GCK1/I
GND
I/O/GCLK3
I/O
I/O
I/O
I/O/PD1
VCC/PD2
I/OE2/GCK2
GCLR/I
I/OE1
GCK1/I
GND
GCK3
I/O
44-Lead TQFP/PQFP
Top View
Description
The ATF1502AS is a high performance, high density Complex Programmable Logic Device (CPLD) which utilizes
Atmel’s proven electrically erasable technology. With 32
logic macrocells and up to 36 inputs, it easily integrates
logic from several TTL, SSI,MSI, LSI and classic PLDs.
The ATF1502AS’s enhanced routing switch matrices
increase usable gate count, and the odds of successful pinlocked design modifications.
The ATF1502AS has up to 32 bi-directional I/O pins and 4
dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal; register clock, register reset or output
enable. Each of these control signals can be selected for
use individually within each macrocell.
Block Diagram
B
32
Each of the 32 macrocells generates a buried feedback,
which goes to the global bus. Each input and I/O pin also
2
ATF1502AS
feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus.
ATF1502AS
Each macrocell also generates a foldback logic term, which
goes to a regional bus. Cascade logic between macrocells
in the ATF1502AS allows fast, efficient generation of complex logic functions. The ATF1502AS contains four such
logic chains, each capable of creating sum term logic with a
fan in of up to 40 product terms.
The ATF1502AS macrocell shown in Figure 1, is flexible
enough to support highly complex logic functions operating
at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer;
OR/XOR/CASCADE logic; a flip-flop; output select and
enable; and logic array inputs.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A Security Fuse,
when programmed, protects the contents of the
ATF1502AS. Two bytes (16-bits) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is
accessible regardless of the state of the Security Fuse.
The ATF1502AS device is an In-System Programmable
(ISP) device. It uses the industry standard 4-pin JTAG
interface (IEEE Std. 1149.1), and is fully compliant with
JTAG’s Boundary Scan Description Language (BSDL). ISP
allows the device to be programmed without removing it
from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to
be made in the field via software.
Figure 1. ATF1502AS Macrocell
Product Terms and Select MUX
Each ATF1502AS macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum
macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1502AS’s logic structure is designed to efficiently
support all types of logic. Within a single macrocell, all the
product terms can be routed to the OR gate, creating a 5input AND/OR sum term. With the addition of the CASIN
from neighboring macrocells, this can be expanded to as
many as 40 product terms with a very small additional
delay.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection.
For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used
to emulate T- and JK-type flip-flops.
Flip Flop
The ATF1502AS’s flip flop has very flexible data and control functions. The data input can come from either the XOR
gate, from a separate product term or directly from the I/O
pin. Selecting the separate product term allows creation of
a buried registered feedback within a combinatorial output
3
macrocell. (This feature is automatically implemented by
the fitter software). In addition to D, T, JK and SR operation, the flip flop can also be configured as a flow-through
latch. In this mode, data passes through when the clock is
high and is latched when the clock is low.
The clock itself can either be one of the Global CLK Signal
GCK[0 : 2] or an individual product term. The flip flop
changes state on the clock’s rising edge. When the GCK
signal is used as the clock, one of the macrocell product
terms can be selected as a clock enable. When the clock
enable function is active and the enable signal (product
term) is low, all clock edges are ignored. The flip flop’s
asynchronous reset signal (AR) can be either the Global
Clear (GCLEAR), a product term, or always off. AR can
also be a logic OR of GCLEAR with a product term. The
asynchronous preset (AP) can be a product term or always
off.
Output Select and Enable
The ATF1502AS macrocell output can be selected as registered or combinatorial. The buried feedback signal can be
either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configuration all the macrocell resources are still available, including the buried feedback, expander and CASCADE logic.
The output enable for each macrocell can be selected as
either of the two dedicated OE input pins as an I/O pin configured as an input, or as an individual product term.
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well
as the buried feedback signal from all 32 macrocells. The
Switch Matrix in each Logic Block receives as its inputs all
signals from the global bus. Under software control, up to
40 of these signals can be selected as inputs to the Logic
Block.
Foldback Bus
Each macrocell also generates a foldback product term.
This signal goes to the regional bus and is available to 4
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 4 foldback terms in each
region allows generation of high fan-in sum terms (up to 9
product terms) with a small additional delay.
Programmable Pin-Keeper Option for
Inputs and I/Os
The ATF1502AS offers the option of programming all input
and I/O pins so that pin keeper circuits can be utilized.
When any pin is driven high or low and then subsequently
left floating, it will stay at that previous high or low level.
4
ATF1502AS
This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which cause unnecessary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
Input Diagram
I/O Diagram
Speed/Power Management
The ATF1502AS has several built-in speed and power
management features. The ATF1502AS contains circuitry
that automatically puts the device into a low power standby mode when no logic transitions are occurring. This not
only reduces power consumption during inactive periods,
but also provides a proportional power savings for most
applications running at system speeds below 50 MHz. This
feature may be selected as a design option.
To further reduce power, each ATF1502AS macrocell has
a Reduced Power bit feature. This feature allows individual
macrocells to be configured for maximum power savings.
This feature may be selected as a design option.
The ATF1502ASs also has an optional power down mode.
In this mode, current drops to below 10 mA. When the
power down option is selected, either PD1 or PD2 pins (or
both) can be used to power down the part. The power down
ATF1502AS
option is selected in the design source file. When enabled,
the device goes into power down when either PD1 or PD2
is high. In the power down mode, all internal logic signals
are latched and held, as are any enabled outputs.
All pin transitions are ignored until the PD pin is brought
low. When the power down feature is enabled, the PD1 or
PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals.
All Power-Down AC Characteristic parameters are computed from external input or I/O pins, with Reduced Power
Bit turned on. For macrocells in reduced-power mode
(Reduced power bit turned on), the reduced power adder,
tRPA, must be added to the AC parameters, which include
the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.
The ATF1502AS macrocell also has an option whereby the
power can be reduced on a per macrocell basis. By
enabling this power down option, macrocells that are not
used in an application can be turned down thereby reducing the overall power consumption of the device.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
Design Software Support
ATF1502AS designs are supported by several third party
tools. Automated fitters allow logic synthesis using a variety
of high level description languages and formats.
Power Up Reset
The ATF1502AS has a power-up reset option at two different voltage trip levels when the device is being powered
down. Within the fitter, or during a conversion, if the
“power-reset” option is turned “on” (which is the default
option), the trip levels during power up or power down is at
2.8V. The user can change this default option from “on” to
“off” (within the fitter or specify it as a switch during conversion). When this is done, the voltage trip level during
power-down changes from 2.8V to 0.7V. This is to ensure a
robust operating environment.
The registers in the ATF1502AS are designed to reset during power up. At a point delayed slightly from VCC crossing
Vrst, all registers will be reset to the low state. The output
state will depend on the polarity of the buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pinhigh, and,
3. The clock must remain stable during TD.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF1502AS fuse patterns. Once programmed, fuse
verify is inhibited. However, the 16-bit User Signature
remains accessible.
Programming
ATF1502AS devices are In-System Programmable (ISP)
devices utilizing the 4-pin JTAG protocol. This capability
eliminates package handling normally required for program
and facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1502AS via the PC. ISP is performed
by using either a download cable, or a comparable board
tester or a simple microprocessor interface.
When using the ISP hardware or S/W to program the
ATF1502AS devices, four I/0 pins must be reserved for the
JTAG interface. However, the logic features the macrocells
associated with these I/0 pins are still available to the
design for burned logic functions.
To facilitate ISP programming by the Automated Test
Equipment (ATE) vendors. Serial Vector Format (SVF) files
can be created by Atmel provided Software utilities.
ATF1502AS devices can also be programmed using standard 3rd party programmers. With 3rd party programmer
the JTAG ISP port can be disabled thereby allowing 4 additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD
applications for details.
ISP Programming Protection
The ATF1502AS has a special feature which locks the
device and prevents the inputs and I/O from driving if the
programming process is interrupted due to any reason. The
inputs and I/O default to high-Z state during such a condition. In addition, the pin keeper option preserves the previous state of the input and I/0 PMS during programming.
All ATF1502AS devices are initially shipped in the erased
state thereby making them ready to use for ISP.
Note:
For more information refer to the “Designing for In-System Programmability with Atmel CPLDs” application
note.
5
JTAG-BST/ISP Overview
The JTAG boundary-scan testing is controlled by the Test
Access Port (TAP) controller in the ATF1502AS. The
boundary-scan technique involves the inclusion of a shiftregister stage (contained in a boundary-scan cell) adjacent
to each component so that signals at component boundaries can be controlled and observed using scan testing
methods. Each input pin and I/O pin has its own boundary
scan cell (BSC) to support boundary scan testing. The
ATF1502AS does not include a Test Reset (TRST) input
pin because the TAP controller is automatically reset at
power up. The five JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ.
The ATF1502AS’s ISP can be fully described using JTAG’s
BSDL as described in IEEE Standard 1149.1b. This allows
ATF1502AS programming to be described and implemented using any one of the 3rd party development tools
supporting this standard.
The ATF1502AS has the option of using four JTAG-standard I/O pins for boundary scan testing (BST) and in-system programming (ISP) purposes. The ATF1502AS is
programmable through the four JTAG pins using the IEEE
standard JTAG programming protocol established by IEEE
Standard 1149.1 using 5V TTL-level programming signals
from the ISP interface for in-system programming. The
JTAG feature is a programmable option. If JTAG (BST or
ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
JTAG Boundary Scan Cell (BSC)
Testing
The ATF1502AS contains up to 32 I/O pins and 4 input
pins, depending on the and package type selected. Each
input pin and I/O pin has its own boundary scan cell (BSC)
in order to support boundary scan testing as described in
detail by IEEE Standard 1149.1. Typical BSC consists of
three capture registers or scan registers and up to two
update registers. There are two types of BSCs, one for
input or I/O pin, and one for the macrocells. The BSCs in
the device are chained together through the capture registers. Input to the capture register chain is fed in from the
TDI pin while the output is directed to the TDO pin. Capture
registers are used to capture active device data signals, to
shift data in and out of the device and to load data into the
update registers. Control signals are generated internally
by the JTAG TAP controller. The BSC configuration for the
input and I/O pins and macrocells are shown below.
6
ATF1502AS
BSC Configuration for Input and I/O
Pins (except JTAG TAP Pins)
Note:
The ATF1502AS has pull-up option on TMS and TDI
pins. This feature is selected as a design option.
DC and AC Operating Conditions
Commercial
Industrial
0°C - 70°C
-40°C - 85°C
VCCINT or VCCIO (5V) Power
Supply
5V ± 5%
5V ± 10%
VCCIO (3.3V) Power Supply
3.0V - 3.6V
3.0V - 3.6V
Operating Temperature (Case)
ATF1502AS
DC Characteristics
Symbol
Parameter
Condition
IIL
Input or I/O Low
Leakage Current
VIN = VCC
IIH
Input or I/O High
Leakage Current
IOZ
Tri-State Output
Off-State Current
Min
VO = VCC or GND
Typ
Max
Units
-2
-10
µA
2
10
-40
40
µA
Com.
60
mA
Ind.
75
mA
Com.
40
µA
Ind.
40
µA
Std Mode
ICC1
Power Supply Current,
Stand-by
VCC = Max
VIN = 0, VCC
“Z” Mode
ICC2
Power Supply Current,
Power Down Mode
VCC = Max
VIN = 0, VCC
“PD” Mode
1
mA
ICC3
Clocked Power Supply
Current
VCC = Max
VIN = 0, VCC
“Z” Mode
2
mA/
MHz
IOS
Output Short Circuit
Current
VOUT = 0.5V
VCCIO
Supply Voltage
5.0V Device Output
VCCIO
Supply Voltage
VIL
-150
mA
Com.
4.75
5.25
V
Ind.
4.5
5.5
V
3.0
3.6
V
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VCCINT +
0.3
V
0.45
V
VOL
Output Low Voltage
VOH
Output High Voltage
Note:
3.3V Device Output
Com.
VIN = VIH or VIL
VCCIO = MIN, IOL = 12 mA
Ind.
VIN = VIH or VIL
VCCIO = MIN, IOH = -4.0 mA
2.4
V
Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Pin Capacitance
CIN
CI/O
Note:
Typ
Max
Units
Conditions
8
10
pF
VIN = 0V; f = 1.0 MHz
8
10
pF
VOUT = 0V; f = 1.0 MHz
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pf.
7
Absolute Maximum Ratings*
Temperature Under Bias .................................. -40°C to +85°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
1.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
AC Characteristics
-7
8
Min
-10
Max
Min
-15
-20
Max
Min
Max
7.5
10
3
15
7
9
3
12
Symbol
Parameter
tPD1
Input or Feedback to
Non-Registered Output
tPD2
I/O Input or Feedback to
Non-Registered Feedback
tSU
Global Clock Setup Time
6
7
11
16
20
ns
tH
Global Clock Hold Time
0
0
0
0
0
ns
tFSU
Global Clock Setup Time of
Fast Input
3
3
3
3
5
ns
tFH
Global Clock Hold Time of
Fast Input
0.5
0.5
1
1.5
2
MHz
tCOP
Global Clock to Output Delay
tCH
Global Clock High Time
3
4
5
6
7
ns
tCL
Global Clock Low Time
3
4
5
6
7
ns
tASU
Array Clock Setup Time
3
3
4
4
5
ns
tAH
Array Clock Hold Time
2
3
4
5
6
ns
tACOP
Array Clock Output Delay
tACH
Array Clock High Time
3
4
6
8
10
ns
tACL
Array Clock Low Time
3
4
6
8
10
ns
tCNT
Minimum Clock Global Period
fCNT
Maximum Internal Global
Clock Frequency
tACNT
Minimum Array Clock Period
fACNT
Maximum Internal Array
Clock Frequency
4.5
5
7.5
125
100
ATF1502AS
10
100
Max
Units
20
25
ns
16
25
ns
13
25
17
66
13
76.9
Min
20
13
76.9
Max
10
15
10
8
125
8
10
8
Min
-25
22
50
17
66
ns
ns
MHz
22
50
ns
ns
MHz
ATF1502AS
AC Characteristics (Continued)
-7
Max
Maximum Clock Frequency
tIN
Input Pad and Buffer Delay
0.5
0.5
2
2
2
ns
tIO
I/O Input Pad and Buffer Delay
0.5
0.5
2
2
2
ns
tFIN
Fast Input Delay
1
1
2
2
2
ns
tSEXP
Foldback Term Delay
4
5
8
10
12
ns
tPEXP
Cascade Logic Delay
0.8
0.8
1
1
1.2
ns
tLAD
Logic Array Delay
3
5
6
7
8
ns
tLAC
Logic Control Delay
3
5
6
7
8
ns
tIOE
Internal Output Enable Delay
2
2
3
3
4
ns
tOD1
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCCIO = 5V; CL = 35 pF)
2
1.5
4
5
6
ns
tOD2
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
2.5
2.0
5
6
7
ns
125
Min
Max
100
Min
-25
FMAX
See ordering information for valid part numbers.
Max
-20
Parameter
166.7
Min
-15
Symbol
Note:
Min
-10
Max
83.3
Min
Max
60
Units
MHz
(continued)
Timing Model
9
AC Characteristics (Continued)
-7
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 5.0V; CL = 35 pF)
4.0
5.0
7
tZX2
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
4.5
5.5
tZX3
Output Buffer Enable Delay
(Slow slew rate = ON;
VCCIO = 5.0V/3.3V; CL = 35 pF)
9
tXZ
Output Buffer Disable Delay
(CL = 5 pF)
4
tSU
Register Setup Time
3
3
4
5
6
ns
tH
Register Hold Time
2
3
4
5
6
ns
tFSU
Register Setup Time of Fast Input
3
3
2
2
3
ns
tFH
Register Hold Time of Fast Input
0.5
0.5
2
2
2.5
ns
tRD
Register Delay
1
2
1
2
2
ns
tCOMB
Combinatorial Delay
1
2
1
2
2
ns
tIC
Array Clock Delay
3
5
6
7
8
ns
tEN
Register Enable Time
3
5
6
7
8
ns
tGLOB
Global Control Delay
1
1
1
1
1
ns
tPRE
Register Preset Time
2
3
4
5
6
ns
tCLR
Register Clear Time
2
3
4
5
6
ns
tUIM
Switch Matrix Delay
1
1
2
2
2
ns
10
11
13
14
15
ns
Notes:
Max
Min
Max
Min
-25
tZX1
Reduced-Power Adder
Min
-20
Parameter
(2)
Max
-15
Symbol
tRPA
Min
-10
Max
Min
Max
Units
9
10
ns
7
9
10
ns
9
10
11
12
ns
5
6
7
8
ns
1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reducedpower mode.
Input Test Waveforms and
Measurement Levels
Output AC Test Loads
(3.0V)*
(703 )*
(8060 )*
tR, tF = 1.5 ns typical
Note:
10
ATF1502AS
*Numbers in parenthesis refer to 3.0V operating conditions (preliminary)
ATF1502AS
Power Down Mode
The ATF1502AS includes an optional pin controlled power
down feature.When this mode is enabled, the PD pin acts
as the power down pin. When the PD pin is high, the device
supply current is reduced to less than 3 mA. During power
down, all output data and internal logic states are latched
and held. Therefore, all registered and combinatorial output
data remain valid. Any outputs which were in a Hi-Z state at
the onset will remain at Hi-Z. During power down, all input
signals except the power down pin are blocked. Input and
I/O hold latches remain active to insure that pins do not
float to indeterminate levels, further reducing system
power. The power down pin feature is enabled in the logic
design file. Designs using the power down pin may not use
the PD pin logic array input. However, all other PD pin macrocell resources may still be used, including the buried
feedback and foldback product term array inputs.
Power Down AC Characteristics(1)(2)
-7
Min
-10
Max
Min
Max
Min
-25
Parameter
tIVDH
Valid I, I/O Before PD High
7
10
15
20
25
ns
tGVDH
Valid OE(2) Before PD High
7
10
15
20
25
ns
7
10
15
20
25
ns
Max
Min
Max
Units
tCVDH
Valid Clock
tDHIX
I, I/O Don’t Care After PD High
12
15
25
30
35
ns
tDHGX
OE(2) Don’t Care After PD High
12
15
25
30
35
ns
tDHCX
Clock(2) Don’t Care After PD High
12
15
25
30
35
ns
tDLIV
PD Low to Valid I, I/O
1
1
1
1
1
µs
tDLGV
PD Low to Valid OE (Pin or Term)
1
1
1
1
1
µs
tDLCV
PD Low to Valid Clock (Pin or Term)
1
1
1
1
1
µs
tDLOV
PD Low to Valid Output
1
1
1
1
1
µs
Notes:
Before PD High
Min
-20
Symbol
(2)
Max
-15
1. For slow slew outputs, add tSSO.
2. Pin or Product Term.
11
BSC Configuration for Mac
BSC for Dedicated Input
TDO
0
Pin
D Q
1
Capture
DR
Clock
TDI
TDO
Shift
0
Q D
1
TDI
CLOCK
TDO
OEJ
0
1
0
D Q
D Q
1
OUTJ
0
Pin
1
0
D Q
D Q
Capture
DR
Update
DR
1
Mode
TDI
Clock
Shift
BSC for I/O Pins and Macrocells
12
ATF1502AS
ATF1502AS
PCI Compliance
high current load required by the PCI interface. The
ATF1502AS allows this without contributing to system
noise while delivering low output to output skew. Having a
programmable high drive option is also possible without
increasing output delay or pin capacitance. The PCI electrical characteristics appear on the next page.
The ATF1502AS also supports the growing need in the
industry to support the new Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and
specifications. The PCI interface calls for high current drivers which are much larger than the traditional TTL drivers.
In general, PLDs and FPGAs parallel outputs to support the
PCI Voltage-to-Current Curves for +5V Signaling in Pull-Up Mode
Pull Up
VCC
Voltage
Test Point
2.4
DC
drive point
1.4
AC drive
point
-44 Current (mA) -178
-2
PCI Voltage-to-Current Curves for +5V Signaling in Pull-Down Mode
Pull Down
VCC
Voltage
AC drive
point
2.2
DC
drive point
0.55
Test Point
3.6
95 Current (mA) 380
13
PCI DC Characteristics (Preliminary)
Symbol
Parameter
VCC
Conditions
Min
Max
Units
Supply Voltage
4.75
5.25
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VIL
Input Low Voltage
-0.5
0.8
V
IIH
Input High Leakage Current
VIN = 2.7V
70
µA
IIL
Input Low Leakage Current
VIN = 0.5V
-70
µA
VOH
Output High Voltage
IOUT = -2 mA
VOL
Output Low Voltage
IOUT = 3 mA, 6 mA
CIN
2.4
V
0.55
V
Input Pin Capacitance
10
pF
CCLK
CLK Pin Capacitance
12
pF
CIDSEL
IDSEL Pin Capacitance
8
pF
LPIN
Pin Inductance
20
nH
Note:
Leakage Current is with Pin-Keeper off.
PCI AC Characteristics (Preliminary)
Symbol
Parameter
Conditions
Min
IOH(AC)
Switching
0 < VOUT ≤ 1.4
-44
mA
Current High
1.4 < VOUT < 2.4
-44+(VOUT - 1.4)
/0.024
mA
3.1 < VOUT < VCC
IOL(AC)
(Test High)
VOUT = 3.1V
Switching
VOUT > 2.2V
Current Low
2.2 > VOUT > 0
Max
Units
Equation A
mA
-142
µA
95
mA
VOUT/0.023
mA
0.1 > VOUT > 0
Equation B
mA
206
mA
(Test Point)
VOUT = 0.71
ICL
Low Clamp Current
-5 < VIN ≤ -1
SLEWR
Output Rise Slew Rate
0.4V to 2.4V load
1
5
V/ns
Output Fall Slew Rate
2.4V to 0.4V load
1
5
V/ns
SLEWF
Notes:
-25+(VIN + 1)
/0.015
1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.
14
ATF1502AS
mA
ATF1502AS
ATF1502AS Dedicated Pinouts
44-Pin
TQFP
44-Pin
J-Lead
44-Pin
PQFP
INPUT/OE2/GCLK2
40
2
40
INPUT/GCLR
39
1
39
INPUT/OE1
38
44
38
INPUT/GCLK1
37
43
37
I/O /GCLK3
35
41
35
5, 19
11, 25
5, 19
I/O / TDI (JTAG)
1
7
1
I/O / TMS (JTAG)
7
13
7
I/O / TCK (JTAG)
26
32
26
I/O / TDO (JTAG)
32
38
32
GND
4, 16, 24, 36
10, 22, 30, 42
4, 16, 24, 36
VCCINT
9, 17, 29, 41
3, 15, 23, 35
9, 17, 29, 41
VCCIO
-
-
-
N/C
-
-
-
# of Signal Pins
36
36
36
# User I/O Pins
32
32
32
Dedicated Pin
I/O / PD (1,2)
OE (1, 2)
GCLR
GCLK (1, 2, 3)
PD (1, 2)
TDI, TMS, TCK, TDO
GND
VCCINT
VCCIO
Global OE Pins
Global Clear Pin
Global Clock Pins
Power down pins
JTAG pins used for Boundary Scan Testing or In-System Programming
Ground Pins
VCC pins for the device (+5V - Internal)
VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os)
15
ATF1502AS I/O Pinouts
16
MC
PLC
44-Pin PLCC
44-Pin TQFP
44-Pin PQFP
1
A
4
42
42
2
A
5
43
43
3
A/PD1
6
41
41
4
A
7
1
1
5
A
8
2
2
6
A
9
3
3
7
A
11
5
5
8/TDI
A
12
6
6
9
A
13
7
7
10
A
14
8
8
11
A
16
10
10
12
A
17
11
11
13
A
18
12
12
14
A
19
13
13
15
A
20
14
14
16
A
21
15
15
17
B
41
35
35
18
B
40
34
34
19
B
39
33
33
20
B
38
32
32
21
B
37
31
31
22
B
36
30
30
23
B
34
28
28
24
B
33
27
27
25
B
32
26
26
26
B
31
25
25
27
B
29
23
23
28
B
28
22
22
29
B
27
21
21
30
B
26
20
20
31
B
25
19
19
32/TMS
B
24
18
18
ATF1502AS
ATF1502AS
Ordering Information
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
7.5
4.5
10
Ordering Code
Package
Operation Range
166.7
ATF1502AS-7 AC44
ATF1502AS-7 JC44
ATF1502AS-7 QC44
44A
44J
44Q
Commercial
(0°C to 70°C)
5
125
ATF1502AS-10 AC44
ATF1502AS-10 JC44
ATF1502AS-10 QC44
44A
44J
44Q
Commercial
(0°C to 70°C)
10
5
125
ATF1502AS-10 AI44
ATF1502AS-10 JI44
ATF1502AS-10 QI44
44A
44J
44Q
Industrial
(-40°C to +85°C)
15
8
100
ATF1502AS-15 AC44
ATF1502AS-15 JC44
ATF1502AS-15 QC44
44A
44J
44Q
Commercial
(0°C to 70°C)
15
8
100
ATF1502AS-15 AI44
ATF1502AS-15 JI44
ATF1502AS-15 QI44
44A
44J
44Q
Industrial
(-40°C to +85°C)
20
12
83.3
ATF1502ASL-20 AC44
ATF1502ASL-20 JC44
ATF1502ASL-20 QC44
44A
44J
44Q
Commercial
(0°C to 70°C)
20
12
83.3
ATF1502ASL-20 AI44
ATF1502ASL-20 JI44
ATF1502ASL-20 QI44
44A
44J
44Q
Industrial
(-40°C to +85°C)
25
15
70
ATF1502ASL-25 AC44
ATF1502ASL-25 JC84
ATF1502ASL-25 QC44
44A
44J
44Q
Commercial
(0°C to 70°C)
25
15
70
ATF1502ASL-25 AI44
ATF1502ASL-25 JI84
ATF1502ASL-25 QI44
44A
44J
44Q
Industrial
(-40°C to +85°C)
Package Type
44A
44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J
44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC)
44Q
44-Lead, Plastic Gull Wing Quad Flatpack (PQFP)
17
Packaging Information
44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing
Quad Flat Package (TQFP)
Dimensions in Millimeters and (Inches)*
44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.045(1.14) X 30° - 45°
.012(.305)
.008(.203)
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
.032(.813)
.026(.660)
.695(17.7)
SQ
.685(17.4)
.050(1.27) TYP
.500(12.7) REF SQ
.021(.533)
.013(.330)
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
.165(4.19)
.022(.559) X 45° MAX (3X)
* Controlling dimension: millimeters
44Q, 44 Lead, Plastic Gull Wing Quad Flat
Package (PQFP)
Dimensions in Inches and (Millimeters)
* Controlling dimension: millimeters
18
ATF1502AS
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