Cypress CY14B108L 8 mbit (1024k x 8/512k x 16) nvsram Datasheet

CY14B108L, CY14B108N
8 Mbit (1024K x 8/512K x 16) nvSRAM
Features
Functional Description
■
20 ns, 25 ns, and 45 ns Access Times
■
Internally Organized as 1024K x 8 (CY14B108L) or 512K x 16
(CY14B108N)
■
Hands off Automatic STORE on Power Down with only a Small
Capacitor
■
STORE to QuantumTrap Nonvolatile Elements Initiated by
Software, Device Pin, or AutoStore on Power Down
■
RECALL to SRAM Initiated by Software or Power Up
■
Infinite Read, Write, and RECALL Cycles
■
200,000 STORE Cycles to QuantumTrap
■
20 year Data Retention
■
Single 3V +20%, -10% Operation
■
Commercial and Industrial Temperatures
■
48-Ball FBGA and 44/54-Pin TSOP-II Packages
■
Pb-free and RoHS Compliant
The Cypress CY14B108L/CY14B108N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 1024 Kbytes of 8 bits each or 512K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
Logic Block Diagram[1, 2, 3]
Quatrum Trap
2048 X 2048 X 2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A17
A18
A19
R
O
W
D
E
C
O
D
E
R
STORE
VCC
VCAP
POWER
CONTROL
RECALL
STORE/RECALL
CONTROL
STATIC RAM
ARRAY
2048 X 2048 X 2
SOFTWARE
DETECT
HSB
A14 - A2
DQ0
DQ1
DQ2
DQ3
I
N
P
U
T
B
U
F
F
E
R
S
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
COLUMN I/O
OE
COLUMN DEC
WE
DQ12
DQ13
CE
DQ14
BLE
A9 A10 A11 A12 A13 A14 A15 A16
DQ15
BHE
Notes
1. Address A0 - A19 for x8 configuration and Address A0 - A18 for x16 configuration.
2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-45523 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 30, 2009
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CY14B108L, CY14B108N
Pinouts
Figure 1. Pin Diagram - 48 FBGA
48-FBGA
48-FBGA
Top View
(not to scale)
Top View
(not to scale)
(x8)
(x16)
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
NC
A
NC
B
DQ8
BHE
A3
A4
CE
DQ0
B
NC
DQ4
C
DQ9 DQ10
A5
A6
DQ1
DQ2
C
A7
DQ5
VCC
D
VSS
A17
A7
DQ3
VCC
D
2
3
4
5
6
NC
OE
A0
A1
A2
NC
NC
NC
A3
A4
CE
DQ0
NC
A5
A6
VSS
DQ1
A17
1
DQ11
VCC
DQ2
VCAP
A16
DQ6
VSS
E
VCC DQ12
VCAP
A16
DQ4
VSS
E
DQ3
NC
A14
A15
NC
DQ7
F
DQ14 DQ13
A14
A15
DQ5
DQ6
F
A12
A13
WE
NC
G
DQ15 HSB
A12
A13
WE
DQ7
G
A9
A10
A11
A19
H
A9
A10
A11
[4]
NC
H
[4]
HSB
NC
A18
A8
A18
A8
Figure 2. Pin Diagram - 44/54-Pin TSOP II
44-TSOP II
54-TSOP II
(x8)
NC
[4]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Top View
(not to scale)
(x16)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
HSB
NC
A19
A18
A17
A16
A15
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
30
29
28
27
26
25
24
23
VCAP
A14
A13
A12
A11
A10
NC
NC
NC
[4]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
Top View
(not to scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
A18
A17
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
NC
NC
NC
Notes
4. Address expansion for 16 Mbit. NC pin not connected to die.
Document #: 001-45523 Rev. *D
Page 2 of 24
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CY14B108L, CY14B108N
Table 1. Pin Definitions
Pin Name
I/O Type
Description
A0 – A19
Input
Address Inputs Used to Select one of the 1,048,576 bytes of the nvSRAM for x8 Configuration.
A0 – A18
DQ0 – DQ7
Address Inputs Used to Select one of the 524,288 words of the nvSRAM for x16 Configuration.
Input/Output Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE
Input
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
VSS
Ground
VCC
Ground for the Device. Must be connected to the ground of the system.
Power Supply Power Supply Inputs to the Device.
HSB
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in
progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak
internal pull up resistor keeps this pin HIGH if not connected (connection optional). After each STORE
operation HSB is driven HIGH for short time with standard output high current.
VCAP
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC
No Connect
No Connect. This pin is not connected to the die.
Document #: 001-45523 Rev. *D
Page 3 of 24
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CY14B108L, CY14B108N
The CY14B108L/CY14B108N nvSRAM is made up of two
functional components paired in the same physical cell. They are
a SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B108L/CY14B108N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations. See the “Truth Table For SRAM Operations” on
page 16 for a complete description of read and write modes.
SRAM Read
The CY14B108L/CY14B108N performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0-19 or A0-18 determines which of the
1,048,576 data bytes or 524,288 words of 16 bits each are
accessed. Byte enables (BHE, BLE) determine which bytes are
enabled to the output, in the case of 16-bit words. When the read
is initiated by an address transition, the outputs are valid after a
delay of tAA (read cycle 1). If the read is initiated by CE or OE,
the outputs are valid at tACE or at tDOE, whichever is later (read
cycle 2). The data output repeatedly responds to address
changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
may corrupt the data stored in nvSRAM.
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 8 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull
up should be placed on WE to hold it inactive during power up.
This pull up is effective only if the WE signal is tristate during
power up. Many MPUs tristate their controls on power up. This
should be verified when using the pull up. When the nvSRAM
comes out of power-on-recall, the MPU must be active or the WE
held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 3. AutoStore Mode
Vcc
0.1uF
10kOhm
Device Operation
Vcc
WE
VCAP
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memory if the data is valid tSD before the end
of a WE controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B108L/CY14B108N stores data to the nvSRAM using
one of the following three storage operations: Hardware STORE
activated by HSB; Software STORE activated by an address
sequence; AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B108L/CY14B108N.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 7. In case AutoStore is enabled without a
Document #: 001-45523 Rev. *D
VSS
VCAP
Hardware STORE Operation
The CY14B108L/CY14B108N provides the HSB pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B108L/CY14B108N conditionally initiates a
STORE operation after tDELAY. An actual STORE cycle only
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B108L/CY14B108N. But any SRAM read and
write cycles are inhibited until HSB is returned HIGH by MPU or
other external source.
During any STORE operation, regardless of how it is initiated,
the CY14B108L/CY14B108N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. After the
STORE operation is completed, the CY14B108L/CY14B108N
Page 4 of 24
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CY14B108L, CY14B108N
remains disabled until the HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
Hardware RECALL (Power Up)
During power up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven LOW by the HSB driver.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14B108L/CY14B108N
Software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Document #: 001-45523 Rev. *D
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared; then, the nonvolatile information is transferred
into the SRAM cells. After the tRECALL cycle time, the SRAM is
again ready for read and write operations. The RECALL
operation does not alter the data in the nonvolatile elements.
Page 5 of 24
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CY14B108L, CY14B108N
Table 2. Mode Selection
CE
WE
OE, BHE, BLE[3]
A15 - A0[5]
Mode
I/O
Power
H
X
X
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[6]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[6]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[6]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[6]
Notes
5. While there are 20 address lines on the CY14B108L (19 address lines on the CY14B108N), only the 13 address lines (A14 - A2) are used to control software modes.
Rest of the address lines are don’t care.
6. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document #: 001-45523 Rev. *D
Page 6 of 24
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CY14B108L, CY14B108N
Preventing AutoStore
Noise Considerations
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
Refer to CY application note AN1064.
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled.
Data Protection
The CY14B108L/CY14B108N protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY14B108L/CY14B108N
is in a write mode (both CE and WE are LOW) at power up, after
a RECALL or STORE, the write is inhibited until the SRAM is
enabled after tLZHSB (HSB to output active). This protects against
inadvertent writes during power up or brown out conditions.
Document #: 001-45523 Rev. *D
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in this nvSRAM product are delivered from
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, autostore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this max VCAP value. Customers that
want to use a larger VCAP value to make sure there is extra store
charge and store time should discuss their VCAP size selection
with Cypress to understand any impact on the VCAP voltage level
at the end of a tRECALL period.
Page 7 of 24
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CY14B108L, CY14B108N
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Package Power Dissipation
Capability (TA = 25°C) ....................................................1.0W
Storage Temperature ..................................–65°C to +150°C
Surface Mount Pb Soldering
Temperature (3 Seconds)...........................................+260°C
Maximum Accumulated Storage Time
At 150°C Ambient Temperature..........................1000h
At 85°C Ambient Temperature.................... ..20 Years
Ambient Temperature with
Power Applied .............................................–55°C to +150°C
DC Output Current (1 output at a time, 1s duration) ....15 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch Up Current................................................... > 200 mA
Supply Voltage on VCC Relative to GND.......... –0.5V to 4.1V
Operating Range
Voltage Applied to Outputs
in High Z State....................................... –0.5V to VCC + 0.5V
Commercial
Input Voltage .......................................... –0.5V to Vcc + 0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential.................. –2.0V to VCC + 2.0V
Range
Ambient Temperature
VCC
0°C to +70°C
2.7V to 3.6V
Industrial
–40°C to +85°C
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V)
Parameter
Description
Test Conditions
Power Supply
VCC
Average VCC Current tRC = 20 ns
ICC1
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads
(IOUT = 0 mA)
ICC2
ICC3
ICC4
ISB
IIX[8]
IOZ
VIH
VIL
VOH
VOL
VCAP
Average VCC Current
during STORE
Average VCC Current
at tRC= 200 ns,
VCC (Typ), 25°C
Average VCAP
Current during
AutoStore Cycle
VCC Standby Current
Input Leakage
Current (except HSB)
Input Leakage
Current (for HSB)
Off-State Output
Leakage Current
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Storage Capacitor
Min
2.7
Typ[7]
3.0
Commercial
Industrial
All Inputs Don’t Care, VCC = Max
Average current for duration tSTORE
All I/P cycling at CMOS levels.
Values obtained without output loads (IOUT = 0 mA).
Max
3.6
70
70
55
75
75
57
20
Unit
V
mA
mA
mA
mA
mA
mA
mA
40
mA
All Inputs Don’t Care. Average current for duration
tSTORE
10
mA
CE > (VCC – 0.2V). VIN < 0.2V or > (VCC – 0.2V). Standby
current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
VCC = Max, VSS < VIN < VCC
10
mA
–2
+2
μA
–200
+2
μA
–2
+2
μA
2.0
Vss – 0.5
2.4
VCC + 0.5
0.8
V
V
V
V
μF
VCC = Max, VSS < VIN < VCC
VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or
BHE/BLE > VIH or WE < VIL
IOUT = –2 mA
IOUT = 4 mA
Between VCAP pin and VSS, 5V Rated
122
150
0.4
360
Notes
7. Typical values are at 25°C, VCC= VCC (Typ). Not 100% tested.
8. The HSB pin has IOUT = -2 uA for VOH of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
Document #: 001-45523 Rev. *D
Page 8 of 24
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CY14B108L, CY14B108N
Data Retention and Endurance
Parameter
Description
Min
Unit
DATAR
Data Retention
20
Years
NVC
Nonvolatile STORE Operations
200
K
Max
Unit
14
pF
14
pF
Capacitance
In the following table, the capacitance parameters are listed.[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC (Typ)
Thermal Resistance
In the following table, the thermal resistance parameters are listed. [9]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
48-FBGA 44-TSOP II 54-TSOP II
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, in accordance with
EIA/JESD51.
Unit
28.82
31.11
30.73
°C/W
7.84
5.56
6.08
°C/W
Figure 4. AC Test Loads
577 Ω
3.0V
577 Ω
3.0V
R1
for tristate specs
R1
OUTPUT
OUTPUT
30 pF
R2
789 Ω
5 pF
R2
789 Ω
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times (10% - 90%) ........................ <3 ns
Input and Output Timing Reference Levels .................... 1.5V
Note
9. These parameters are guaranteed by design but not tested.
Document #: 001-45523 Rev. *D
Page 9 of 24
[+] Feedback
CY14B108L, CY14B108N
AC Switching Characteristics
Parameters
Cypress
Parameters
20 ns
Description
Alt
Parameters
Min
25 ns
Max
Min
45 ns
Max
Min
Max
Unit
SRAM Read Cycle
tACE
tACS
Chip Enable Access Time
tRC[10]
tRC
Read Cycle Time
tAA[11]
tAA
Address Access Time
20
25
45
ns
tDOE
tOE
Output Enable to Data Valid
10
12
20
ns
tOHA[11]
tOH
Output Hold After Address Change
3
3
3
ns
tLZCE[9, 12]
tLZ
Chip Enable to Output Active
3
3
3
ns
tHZCE[9, 12]
tLZOE[9, 12]
tHZOE[9, 12]
tPU[9]
tPD[9]
tHZ
Chip Disable to Output Inactive
tOLZ
Output Enable to Output Active
tOHZ
Output Disable to Output Inactive
tPA
Chip Enable to Power Active
tPS
Chip Disable to Power Standby
20
25
45
ns
tDBE
-
Byte Enable to Data Valid
10
12
20
ns
tLZBE[9]
tHZBE[9]
-
Byte Enable to Output Active
-
Byte Disable to Output Inactive
20
20
25
25
8
0
10
0
0
15
10
0
0
15
ns
ns
0
10
ns
ns
0
8
ns
ns
0
8
0
45
45
ns
15
ns
SRAM Write Cycle
tWC
tWC
Write Cycle Time
tPWE
tWP
Write Pulse Width
15
20
30
ns
tSCE
tCW
Chip Enable To End of Write
15
20
30
ns
tSD
tDW
Data Setup to End of Write
8
10
15
ns
tHD
tDH
Data Hold After End of Write
0
0
0
ns
tAW
tAW
Address Setup to End of Write
15
20
30
ns
tSA
tAS
Address Setup to Start of Write
0
0
0
ns
tHA
tWR
Address Hold After End of Write
0
tHZWE[9, 12,13]
tWZ
Write Enable to Output Disable
tLZWE[9, 12]
tOW
Output Active after End of Write
3
3
3
ns
tBW
-
Byte Enable to End of Write
15
20
30
ns
Switching Waveforms
20
25
45
0
ns
0
8
10
ns
15
ns
Figure 5. SRAM Read Cycle #1: Address Controlled[10, 11, 14]
tRC
Address
Address Valid
tAA
Data Output
Previous Data Valid
Output Data Valid
tOHA
Notes
10. WE must be HIGH during SRAM read cycles.
11. Device is continuously selected with CE, OE and BHE / BLE LOW.
12. Measured ±200 mV from steady state output voltage.
13. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
14. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-45523 Rev. *D
Page 10 of 24
[+] Feedback
CY14B108L, CY14B108N
Figure 6. SRAM Read Cycle #2: CE and OE Controlled[3, 10, 14]
Address
Address Valid
tRC
tACE
CE
tHZCE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
Data Output
High Impedance
ICC
Output Data Valid
tPU
tPD
Active
Standby
Figure 7. SRAM Write Cycle #1: WE Controlled[3, 13, 14, 15]
W:&
$GGUHVV
$GGUHVV9DOLG
W6&(
W+$
&(
W%:
%+(%/(
W$:
W3:(
:(
W6$
W6'
'DWD,QSXW
,QSXW'DWD9DOLG
W+=:(
'DWD2XWSXW
W+'
3UHYLRXV'DWD
W/=:(
+LJK,PSHGDQFH
Note
15. CE or WE must be >VIH during address transitions.
Document #: 001-45523 Rev. *D
Page 11 of 24
[+] Feedback
CY14B108L, CY14B108N
Figure 8. SRAM Write Cycle #2: CE Controlled[3, 13, 14, 15]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Figure 9. SRAM Write Cycle #3: BHE and BLE Controlled[3, 13, 14, 15]
tWC
Address
Address Valid
tSCE
CE
tSA
tHA
tBW
BHE, BLE
tAW
tPWE
WE
tSD
Data Input
tHD
Input Data Valid
High Impedance
Data Output
Document #: 001-45523 Rev. *D
Page 12 of 24
[+] Feedback
CY14B108L, CY14B108N
AutoStore/Power Up RECALL
Parameters
20 ns
Description
Min
Max
tHRECALL [16] Power Up RECALL Duration
tSTORE
[17]
25 ns
Min
45 ns
Max
20
Min
Max
20
Unit
20
ms
STORE Cycle Duration
8
8
8
ms
tDELAY [18]
Time Allowed to Complete SRAM Write Cycle
20
25
25
ns
VSWITCH
Low Voltage Trigger Level
tVCCRISE[9]
VCC Rise Time
VHDIS[9]
HSB Output Disable Voltage
1.9
1.9
1.9
V
tLZHSB[9]
HSB To Output Active Time
5
5
5
μs
tHHHD[9]
HSB High Active Time
500
500
500
ns
2.65
150
Switching Waveforms
2.65
2.65
150
V
μs
150
Figure 10. AutoStore or Power Up RECALL[19]
VCC
VSWITCH
VHDIS
Note 17
VVCCRISE
tSTORE
tHHHD
Note
tSTORE
Note
tHHHD
HSB OUT
17
20
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
Read & Write
Inhibited
(RWI)
tHRECALL
POWER-UP
RECALL
Read & Write
tHRECALL
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
16. tHRECALL starts from the time VCC rises above VSWITCH.
17. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.
18. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
19. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
20. HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.
Document #: 001-45523 Rev. *D
Page 13 of 24
[+] Feedback
CY14B108L, CY14B108N
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed.[21, 22]
Parameters
tRC
tSA
tCW
tHA
tRECALL
20 ns
Min
Max
20
0
15
0
200
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
25 ns
Min
Max
25
0
20
0
200
45 ns
Min
Max
45
0
30
0
200
Unit
ns
ns
ns
ns
μs
Switching Waveforms
Figure 11. CE and OE Controlled Software STORE/RECALL Cycle[22]
tRC
Address
tRC
Address #1
tSA
Address #6
tCW
tCW
CE
tHA
tSA
tHA
tHA
tHA
OE
tHHHD
HSB (STORE only)
tHZCE
tLZCE
t DELAY
23
Note
tLZHSB
High Impedance
tSTORE/tRECALL
DQ (DATA)
RWI
Figure 12. Autostore Enable/Disable Cycle
Address
tSA
CE
tRC
tRC
Address #1
Address #6
tCW
tCW
tHA
tSA
tHA
tHA
tHA
OE
tLZCE
tHZCE
tSS
23
Note
t DELAY
DQ (DATA)
Notes
21. The software sequence is clocked with CE controlled or OE controlled reads.
22. The six consecutive addresses must be read in the order listed in Table 2 on page 6. WE must be HIGH during all six consecutive cycles.
23. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
Document #: 001-45523 Rev. *D
Page 14 of 24
[+] Feedback
CY14B108L, CY14B108N
Hardware STORE Cycle
Parameters
20 ns
Description
Min
tDHSB
HSB To Output Active Time when write latch not set
tPHSB
Hardware STORE Pulse Width
tSS [24, 25]
Soft Sequence Processing Time
Switching Waveforms
25 ns
Max
Min
45 ns
Max
20
Min
25
15
15
Max
25
ns
100
μs
15
100
100
Unit
ns
Figure 13. Hardware STORE Cycle[17]
Write latch set
tPHSB
HSB (IN)
tSTORE
tDELAY
tHHHD
HSB (OUT)
tLZHSB
DQ (Data Out)
RWI
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100kOhm resistor,
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
HSB (IN)
HSB (OUT)
tDELAY
tDHSB
tDHSB
RWI
Figure 14. Soft Sequence Processing[24, 25]
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
tSS
Soft Sequence
Command
Address #1
tSS
Address #6
tCW
CE
VCC
Notes
24. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
25. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document #: 001-45523 Rev. *D
Page 15 of 24
[+] Feedback
CY14B108L, CY14B108N
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
For x8 Configuration
Inputs/Outputs[2]
CE
WE
OE
H
X
X
High Z
Deselect/Power down
Mode
Standby
Power
L
H
L
Data Out (DQ0–DQ7);
Read
Active
L
H
H
High Z
Output Disabled
Active
L
L
X
Data in (DQ0–DQ7);
Write
Active
For x16 Configuration
CE
WE
OE
BHE[3]
BLE[3]
H
X
X
X
X
L
X
X
H
L
H
L
L
L
H
L
L
H
L
L
H
L
H
L
Inputs/Outputs[2]
Mode
Power
High Z
Deselect/Power down
Standby
H
High Z
Output Disabled
Active
L
Data Out (DQ0–DQ15)
Read
Active
H
L
Data Out (DQ0–DQ7);
DQ8–DQ15 in High Z
Read
Active
L
H
Data Out (DQ8–DQ15);
DQ0–DQ7 in High Z
Read
Active
H
L
L
High Z
Output Disabled
Active
H
H
L
High Z
Output Disabled
Active
H
H
L
H
High Z
Output Disabled
Active
L
L
X
L
L
Data In (DQ0–DQ15)
Write
Active
L
L
X
H
L
Data In (DQ0–DQ7);
DQ8–DQ15 in High Z
Write
Active
L
L
X
L
H
Data In (DQ8–DQ15);
DQ0–DQ7 in High Z
Write
Active
Document #: 001-45523 Rev. *D
Page 16 of 24
[+] Feedback
CY14B108L, CY14B108N
Ordering Information
Speed
(ns)
20
25
Ordering Code
Package
Diagram
Package Type
CY14B108L-ZS20XCT
51-85087
44-pin TSOP II
CY14B108L-ZS20XC
51-85087
44-pin TSOP II
CY14B108L-ZS20XIT
51-85087
44-pin TSOP II
CY14B108L-ZS20XI
51-85087
44-pin TSOP II
CY14B108L-BA20XCT
51-85128
48-ball FBGA
CY14B108L-BA20XC
51-85128
48-ball FBGA
CY14B108L-BA20XIT
51-85128
48-ball FBGA
CY14B108L-BA20XI
51-85128
48-ball FBGA
CY14B108N-BA20XCT
51-85128
48-ball FBGA
CY14B108N-BA20XC
51-85128
48-ball FBGA
CY14B108N-BA20XIT
51-85128
48-ball FBGA
CY14B108N-BA20XI
51-85128
48-ball FBGA
CY14B108N-ZSP20XCT
51-85160
54-pin TSOP II
CY14B108N-ZSP20XC
51-85160
54-pin TSOP II
CY14B108N-ZSP20XIT
51-85160
54-pin TSOP II
CY14B108N-ZSP20XI
51-85160
54-pin TSOP II
CY14B108L-ZS25XCT
51-85087
44-pin TSOP II
CY14B108L-ZS25XC
51-85087
44-pin TSOP II
CY14B108L-ZS25XIT
51-85087
44-pin TSOP II
CY14B108L-ZS25XI
51-85087
44-pin TSOP II
CY14B108L-BA25XCT
51-85128
48-ball FBGA
CY14B108L-BA25XC
51-85128
48-ball FBGA
CY14B108L-BA25XIT
51-85128
48-ball FBGA
CY14B108L-BA25XI
51-85128
48-ball FBGA
CY14B108N-BA25XCT
51-85128
48-ball FBGA
CY14B108N-BA25XC
51-85128
48-ball FBGA
CY14B108N-BA25XIT
51-85128
48-ball FBGA
CY14B108N-BA25XI
51-85128
48-ball FBGA
CY14B108N-ZSP25XCT
51-85160
54-pin TSOP II
CY14B108N-ZSP25XC
51-85160
54-pin TSOP II
CY14B108N-ZSP25XIT
51-85160
54-pin TSOP II
CY14B108N-ZSP25XI
51-85160
54-pin TSOP II
Document #: 001-45523 Rev. *D
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 17 of 24
[+] Feedback
CY14B108L, CY14B108N
Ordering Information (continued)
Speed
(ns)
45
Ordering Code
Package
Diagram
Package Type
CY14B108L-ZS45XCT
51-85087
44-pin TSOP II
CY14B108L-ZS45XC
51-85087
44-pin TSOP II
CY14B108L-ZS45XIT
51-85087
44-pin TSOP II
CY14B108L-ZS45XI
51-85087
44-pin TSOP II
CY14B108L-BA45XCT
51-85128
48-ball FBGA
CY14B108L-BA45XC
51-85128
48-ball FBGA
CY14B108L-BA45XIT
51-85128
48-ball FBGA
CY14B108L-BA45XI
51-85128
48-ball FBGA
CY14B108N-BA45XCT
51-85128
48-ball FBGA
CY14B108N-BA45XC
51-85128
48-ball FBGA
CY14B108N-BA45XIT
51-85128
48-ball FBGA
CY14B108N-BA45XI
51-85128
48-ball FBGA
CY14B108N-ZSP45XCT
51-85160
54-pin TSOP II
CY14B108N-ZSP45XC
51-85160
54-pin TSOP II
CY14B108N-ZSP45XIT
51-85160
54-pin TSOP II
CY14B108N-ZSP45XI
51-85160
54-pin TSOP II
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
All the above parts are Pb-free.
Document #: 001-45523 Rev. *D
Page 18 of 24
[+] Feedback
CY14B108L, CY14B108N
Part Numbering Nomenclature
CY 14 B 108L-ZS P 20 X C T
Option:
T - Tape & Reel
Blank - Std.
Pb-Free
P - 54 Pin
Blank - 44 Pin/48 Ball
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Package:
BA - 48 FBGA
ZS - TSOP II
Voltage:
B - 3.0V
Data Bus:
L - x8
N - x16
Speed:
20 - 20 ns
25 - 25 ns
45 - 45 ns
Density:
108 - 8 Mb
NVSRAM
14 - Auto Store + Software STORE + Hardware STORE
Cypress
Document #: 001-45523 Rev. *D
Page 19 of 24
[+] Feedback
CY14B108L, CY14B108N
Package Diagrams
Figure 15. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH)
MAX
MIN.
PIN 1 I.D.
1
23
10.262 (0.404)
10.058 (0.396)
11.938 (0.470)
11.735 (0.462)
22
EJECTOR PIN
44
TOP VIEW
0.800 BSC
(0.0315)
OR E
K X A
SG
BOTTOM VIEW
0.400(0.016)
0.300 (0.012)
10.262 (0.404)
10.058 (0.396)
BASE PLANE
0.210 (0.0083)
0.120 (0.0047)
0°-5°
0.10 (.004)
Document #: 001-45523 Rev. *D
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
18.517 (0.729)
18.313 (0.721)
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
51-85087-*A
Page 20 of 24
[+] Feedback
CY14B108L, CY14B108N
Package Diagrams
(continued)
Figure 16. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
10.00±0.10
10.00±0.10
1
F
G
H
H
1.875
A
A
B
0.75
6.00±0.10
0.53±0.05
B
0.15 C
0.21±0.05
0.25 C
3.75
6.00±0.10
0.15(4X)
Document #: 001-45523 Rev. *D
1.20 MAX
0.36
SEATING PLANE
C
51-85128-*D
Page 21 of 24
[+] Feedback
CY14B108L, CY14B108N
Package Diagrams
(continued)
Figure 17. 54-Pin TSOP II (51-85160)
51-85160-**
Document #: 001-45523 Rev. *D
Page 22 of 24
[+] Feedback
CY14B108L, CY14B108N
Document History Page
Document Title: CY14B108L, CY14B108N 8 Mbit (1024K x 8/512K x 16) nvSRAM
Document Number: 001-45523
Rev.
ECN No.
Orig. of Change
Submission
Date
**
2428826
GVCH
See ECN
New Data Sheet
*A
2520023
GVCH/PYRS
06/23/08
Updated ICC1 for tRC=20ns, 25ns and 45ns access speed for both industrial
and Commercial temperature Grade
Updated Thermal resistance values for 48-FBGA,44-TSOP II and 54-TSOP II
packages
Changed tCW value from 16ns to 15ns
*B
2676670
GVCH/PYRS
03/20/2009
Added maximum accumulated storage time for 150°C and 85°C Temperature
Added best practices
Changed ICC2 from 12mA to 20mA
Changed ICC3 from 38mA to 40mA
Changed ICC4 from 12mA to 10mA
Changed ISB from 6mA to 10mA
Changed VCAP from 164uF to 360uF
Changed Input Rise and Fall Times from 5ns to 3ns
Updated ICC1, ICC3, ISBand IOZ Test conditions
Changed tDELAY to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively
Changed tSTORE from 15ms to 8ms
Added VHDIS, tHHHD and tLZHSB parameters
Software controlled STORE/RECALL cycle table: Changed tAS to tSA
Changed tGHAX to tHA
Added tDHSB parameter
Changed tHLHX to tPHSB
Updated tSS from 70us to 100us
Added Truth table for SRAM operations
Updated ordering information
*C
2712462
GVCH/PYRS
05/29/2009
Moved data sheet status from Preliminary to Final
Updated AutoStore operation
Updated ISB test condition
Updated footnote 7
Referenced footnote 9 to VCCRISE, tHHHD and tLZHSB parameters
Updated VHDIS parameter description
*D
2746310
GVCH
07/29/2009
Page 4: Updated Hardware STORE (HSB) operation description
page 5: Updated Software STORE description
Updated tDELAY parameter description
Updated footnote 18 and added footnote 23
Referenced footnote 23 to Figure 11 and Figure 12
Document #: 001-45523 Rev. *D
Description of Change
Page 23 of 24
[+] Feedback
CY14B108L, CY14B108N
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
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critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-45523 Rev. *D
Revised July 30, 2009
Page 24 of 24
All products and company names mentioned in this document are the trademarks of their respective holders.
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