Renesas M38K01M3 Renesas 8-bit single-chip microcomputer 740 family / 38000 sery Datasheet

REJ09B0337-0200
38K0 Group
8
User's Manual
RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev. 2.00
Revision date: Oct 05, 2006
www.renesas.com
Keep safety first in your circuit designs!
1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
2.
3.
4.
5.
6.
7.
8.
These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corp. product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Renesas Technology Corp. or a third party.
Renesas Technology Corp. assumes no responsibility for any damage, or infringement of
any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corp. without notice due to
product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://
www.renesas.com).
When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information
and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Renesas Technology Corp. semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at
stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology
Corp. product distributor when considering the use of a product contained herein for any
specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions,
they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/
or the country of destination is prohibited.
Please contact Renesas Technology Corp. for further details on these materials or the
products contained therein.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the
products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General
Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description
in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register settings and pins
are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins are
not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
 When the clock signal is generated with an external resonator (or from an external oscillator) during
a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover,
when switching to a clock signal produced with an external resonator (or by an external oscillator)
while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm that the
change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different type numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different type numbers, implement a system-evaluation test for each of the products.
BEFORE USING THIS MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. Chapter 3 also includes necessary information for
systems development. You must refer to that chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the list of registers.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B 16]
B
Name
0
Processor mode bits
1
Function
At reset
R W
b1 b0
0 0 : Single-chip mode
01:
10:
Not available
11:
0 : 0 page
1 : 1 page
0
0
2
Stack page selection bit
3
0
✕
4
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
0
✕
5
Fix this bit to “0.”
1
6
Main clock (X IN-XOUT) stop bit
7
Internal system clock selection bit
: Bit in which nothing is arranged
0 : Operating
1 : Stopped
0 : XIN -XOUT selected
1 : XCIN -XCOUT selected
0
✽
✽
: Bit that is not used for control of the corresponding function
Note 1:. Contents immediately after reset release
0....... “0” at reset release
1....... “1” at reset release
?....... Undefined at reset release
✽.......Contents determined by option at reset release
Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows :
R....... Read
...... Read enabled
✕.......Read disabled
W......Write
..... Write enabled
✕...... Write disabled
✽.......“0” write
3. Supplementation
For details of software, refer to the “740 FAMILY SOFTWARE MANUAL.”
For details of development support tools, refer to the “Renesas Technology” Homepage (http://www.renesas.com).
Table of contents
38K0 Group
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................... 2
FEATURES ......................................................................................................................................... 2
PIN CONFIGURATION ..................................................................................................................... 2
FUNCTIONAL BLOCK ..................................................................................................................... 3
PIN DESCRIPTION ........................................................................................................................... 4
PART NUMBERING .......................................................................................................................... 5
GROUP EXPANSION ....................................................................................................................... 6
Memory Type ............................................................................................................................... 6
Memory Size ................................................................................................................................ 6
Packages ...................................................................................................................................... 6
FUNCTIONAL DESCRIPTION ......................................................................................................... 7
Central Processing Unit (CPU) ................................................................................................. 7
Memory ....................................................................................................................................... 11
I/O Ports ..................................................................................................................................... 13
Interrupts .................................................................................................................................... 17
Timers ......................................................................................................................................... 20
Serial Interface .......................................................................................................................... 22
USB Function ............................................................................................................................. 26
External Bus Interface (EXB) .................................................................................................. 52
Multichannel RAM ..................................................................................................................... 71
A/D Converter ............................................................................................................................ 73
Watchdog Timer ........................................................................................................................ 75
Reset Circuit .............................................................................................................................. 76
PLL Circuit (Frequency Synthesizer) ...................................................................................... 77
Clock Generating Circuit .......................................................................................................... 79
Flash Memory Mode ................................................................................................................. 82
NOTES ON PROGRAMMING ...................................................................................................... 108
NOTES ON USAGE ...................................................................................................................... 110
DATA REQUIRED FOR MASK ORDERS ................................................................................. 110
FUNCTIONAL DESCRIPTION SUPPLEMENT .......................................................................... 111
CHAPTER 2 APPLICATION
2.1 I/O port ........................................................................................................................................ 2
2.1.1 Memory map ...................................................................................................................... 2
2.1.2 Related registers ............................................................................................................... 3
2.1.3 Handling of unused pins .................................................................................................. 5
2.1.4 Notes on input and output pins ...................................................................................... 6
2.1.5 Termination of unused pins ............................................................................................. 7
2.2 Interrupt ...................................................................................................................................... 8
2.2.1 Memory map ...................................................................................................................... 8
2.2.2 Related registers ............................................................................................................... 8
2.2.3 Interrupt source ............................................................................................................... 11
2.2.4 Interrupt operation ........................................................................................................... 12
2.2.5 Interrupt control ............................................................................................................... 15
2.2.6 INT interrupt ..................................................................................................................... 18
2.2.7 Key input interrupt .......................................................................................................... 19
2.2.8 Notes on interrupts ......................................................................................................... 21
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 1 of 13
Table of contents
38K0 Group
2.3 Timer .......................................................................................................................................... 23
2.3.1 Memory map .................................................................................................................... 23
2.3.2 Related registers ............................................................................................................. 23
2.3.3 Timer application examples ........................................................................................... 28
2.3.4 Notes on timer ................................................................................................................. 39
2.4 Serial I/O ................................................................................................................................... 40
2.4.1 Memory map .................................................................................................................... 40
2.4.2 Related registers ............................................................................................................. 41
2.4.3 Serial I/O connection examples .................................................................................... 45
2.4.4 Setting of serial I/O transfer data format .................................................................... 47
2.4.5 Serial I/O application examples .................................................................................... 48
2.4.6 Notes on serial I/O ......................................................................................................... 66
2.5 USB function ........................................................................................................................... 69
2.6 External bus interface(EXB) ................................................................................................. 70
2.7 A/D converter .......................................................................................................................... 71
2.7.1 Memory map .................................................................................................................... 71
2.7.2 Related registers ............................................................................................................. 71
2.7.3 A/D converter application examples ............................................................................. 74
2.7.4 Notes on A/D converter ................................................................................................. 76
2.8 Watchdog timer ....................................................................................................................... 77
2.8.1 Memory map .................................................................................................................... 77
2.8.2 Related registers ............................................................................................................. 77
2.8.3 Watchdog timer application examples ........................................................................ 79
2.8.4 Notes on watchdog timer ............................................................................................... 80
2.9 Reset .......................................................................................................................................... 81
2.9.1 Connection____________
example of reset IC ................................................................................... 81
2.9.2 Notes on RESET pin ...................................................................................................... 82
2.10 Frequency synthesizer (PLL) ............................................................................................. 83
2.10.1 Memory map .................................................................................................................. 83
2.10.2 Related registers ........................................................................................................... 83
2.10.3 Functional description ................................................................................................... 85
2.10.4 Notes on PLL ................................................................................................................ 88
2.11 Clock generating circuit ..................................................................................................... 89
2.11.1 Memory map .................................................................................................................. 89
2.11.2 Related registers ........................................................................................................... 89
2.11.3 Oscillation control .......................................................................................................... 91
2.12 Standby function .................................................................................................................. 94
2.12.1 Memory map .................................................................................................................. 94
2.12.2 Related registers ........................................................................................................... 94
2.12.3 Stop mode ...................................................................................................................... 95
2.12.4 Wait mode ...................................................................................................................... 99
2.12.5 Notes on stand-by function ........................................................................................ 101
2.13 Flash memory ...................................................................................................................... 102
2.13.1 Overview ....................................................................................................................... 102
2.13.2 Memory map ................................................................................................................ 102
2.13.3 Related registers ......................................................................................................... 103
2.13.4 Parallel I/O mode ........................................................................................................ 104
2.13.5 Standard serial I/O mode ........................................................................................... 104
2.13.6 CPU rewrite mode ...................................................................................................... 105
2.13.7 Flash memory mode application examples ............................................................. 106
2.13.8 Notes on CPU rewrite mode ..................................................................................... 111
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 2 of 13
Table of contents
38K0 Group
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ........................................................................................................ 2
3.1.1 Absolute maximum ratings ............................................................................................... 2
3.1.2 Recommended operating conditions ............................................................................... 3
3.1.3 Electrical characteristics ................................................................................................... 5
3.1.4 A/D converter characteristics ........................................................................................... 7
3.1.5 Timing requirements ......................................................................................................... 8
3.1.6 Switching characteristics ................................................................................................ 11
3.2 Notes on use ........................................................................................................................... 20
3.2.1 Notes on input and output ports ................................................................................... 20
3.2.2 Termination of unused pins ........................................................................................... 21
3.2.3 Notes on interrupts ......................................................................................................... 22
3.2.4 Notes on timer ................................................................................................................. 23
3.2.5 Notes on serial I/O ......................................................................................................... 24
3.2.6 Notes on USB function ................................................................................................... 26
3.2.7 Notes on A/ºD converter ................................................................................................ 27
3.2.8 Notes on _____________
watchdog timer ............................................................................................... 27
3.2.9 Notes on RESET pin ...................................................................................................... 27
3.2.10 Notes onPLL .................................................................................................................. 27
3.2.11 Notes on stand-by function .......................................................................................... 28
3.2.12 Notes on CPU rewrite mode ....................................................................................... 28
3.2.13 Notes on programming ................................................................................................. 29
3.2.14 Notes on flash memory version .................................................................................. 31
3.2.15 Electric Characteristic Differences Between Mask ROM and Flash Memory Version
MCUs .............................................................................................................................. 31
3.3 Countermeasures against noise ......................................................................................... 32
3.3.1 Shortest wiring length ..................................................................................................... 32
3.3.2 Connection of bypass capacitor across V SS line and V CC line .................................. 34
3.3.3 Wiring to analog input pins ........................................................................................... 35
3.3.4 Oscillator concerns .......................................................................................................... 36
3.3.5 Setup for I/O ports .......................................................................................................... 37
3.3.6 Providing of watchdog timer function by software ..................................................... 38
3.4 List of registers ...................................................................................................................... 39
3.5 Package outline ...................................................................................................................... 73
3.6 Machine instructions ............................................................................................................. 75
3.7 List of instruction code ........................................................................................................ 87
3.8 SFR memory map ................................................................................................................... 88
3.9 Pin configurations .................................................................................................................. 89
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 3 of 13
List of figures
38K0 Group
List of figures
CHAPTER 1 HARDWARE
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
1 Pin configuration of 38K0 group ........................................................................................ 2
2 Functional block diagram .................................................................................................... 3
3 Part numbering ..................................................................................................................... 5
4 Memory expansion plan ...................................................................................................... 6
5 740 Family CPU register structure .................................................................................... 7
6 Register push and pop at interrupt generation and subroutine call ............................. 8
7 Structure of CPU mode register ...................................................................................... 10
8 Memory map diagram ........................................................................................................ 11
9 Memory map of special function register (SFR) ............................................................ 12
10 Port block diagram (1) .................................................................................................... 14
11 Port block diagram (2) .................................................................................................... 15
12 Structure of port I/O-related registers ........................................................................... 16
13 Interrupt control ................................................................................................................ 18
14 Structure of interrupt-related registers .......................................................................... 18
15 Connection example when using key input interrupt and port P0 block diagram .. 19
16 Structure of timer X mode register ............................................................................... 20
17 Timer block diagram ........................................................................................................ 21
18 Block diagram of clock synchronous serial I/O ........................................................... 22
19 Operation of clock synchronous serial I/O function .................................................... 22
20 Block diagram of UART serial I/O ................................................................................. 23
21 Operation of UART serial I/O function .......................................................................... 23
22 Structure of serial I/O control registers ........................................................................ 25
23 USB function overview .................................................................................................... 26
24 USB Function Control Circuit (USBFCC) block diagram ............................................ 27
25 USB port external circuit (D0+, D0-, USBV REF, TrON) block diagram (4.0V ≤ V CC
≤ 5.25V) ........................................................................................................................... 28
26 USB port external circuit (D0+, D0-, USBV REF, TrON) block diagram (3.0V ≤ V CC
≤ 4.0V) ............................................................................................................................. 28
27 Example setting of buffer area beginning address ..................................................... 29
28 Examples of interrupt source dependant buffer area offset address ....................... 29
29 USB device interrupt control .......................................................................................... 31
30 USB related registers ...................................................................................................... 32
31 Structure of USB control register .................................................................................. 33
32 Structure of USB function enable register ................................................................... 33
33 Structure of USB function address register ................................................................. 34
34 Structure of Frame number register Low ..................................................................... 34
35 Structure of Frame number register High .................................................................... 34
36 Structure of USB interrupt source enable register ...................................................... 35
37 Structure of USB interrupt source register ................................................................... 36
38 Structure of Endpoint index register ............................................................................. 36
39 Structure of EP00 stage register ................................................................................... 37
40 Structure of EP00 control register 1 ............................................................................. 37
41 Structure of EP00 control register 2 ............................................................................. 37
42 Structure of EP00 control register 3 ............................................................................. 38
43 Structure of EP00 interrupt source register ................................................................. 38
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 4 of 13
List of figures
38K0 Group
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Structure of EP00 byte number register ....................................................................... 39
Structure of EP00 buffer area set register ................................................................... 39
Structure of EP01 set register ....................................................................................... 40
Structure of EP01 control register 1 ............................................................................. 40
Structure of EP01 control register 2 ............................................................................. 41
Structure of EP01 control register 3 ............................................................................. 41
Structure of EP01 interrupt source register ................................................................. 41
Structure of EP01 byte number register 0 ................................................................... 42
Structure of EP01 byte number register 1 ................................................................... 42
Structure of EP01 MAX. packet size register .............................................................. 42
Structure of EP01 buffer area set register ................................................................... 43
Structure of EP02 set register ....................................................................................... 44
Structure of EP02 control register 1 ............................................................................. 44
Structure of EP02 control register 2 ............................................................................. 45
Structure of EP02 control register 3 ............................................................................. 45
Structure of EP02 interrupt source register ................................................................. 45
Structure of EP02 byte number register 0 ................................................................... 46
Structure of EP02 byte number register 1 ................................................................... 46
Structure of EP02 MAX. packet size register .............................................................. 46
Structure of EP02 buffer area set register ................................................................... 47
Structure of EP03 set register ....................................................................................... 48
Structure of EP03 control register 1 ............................................................................. 48
Structure of EP03 control register 2 ............................................................................. 49
Structure of EP03 control register 3 ............................................................................. 49
Structure of EP03 interrupt source register ................................................................. 49
Structure of EP03 byte number register 0 ................................................................... 50
Structure of EP03 byte number register 1 ................................................................... 50
Structure of EP03 MAX. packet size register .............................................................. 50
Structure of EP03 buffer area set register ................................................................... 51
External bus interface ..................................................................................................... 52
Data transfer timing of memory channel ...................................................................... 52
External bus interface (EXB) pin assignment .............................................................. 53
Block diagram of external bus interface (EXB) ........................................................... 54
EXB related registers (1) ................................................................................................ 58
EXB related registers (2) ................................................................................................ 58
Structure of EXB interrupt source enable register ...................................................... 59
Structure of EXB interrupt source register ................................................................... 59
Structure of EXB index register ..................................................................................... 60
Structure of Register window 1 ..................................................................................... 60
Structure of Register window 2 ..................................................................................... 60
Index00[low]; Structure of External I/O configuration register ................................... 61
Index00[high]; Structure of External I/O configuration register ................................ 61
Index01[low]; Structure of Transmit/Receive buffer register ...................................... 62
Index02[low]; Structure of Memory channel operation mode register ...................... 62
Index03[low]; Structure of Memory address counter .................................................. 62
Index03[high]; Structure of Memory address counter ................................................. 63
Index04[low]; Structure of End address register ......................................................... 63
Index04[high]; Structure of End address register ........................................................ 63
CPU channel receiving operation .................................................................................. 64
CPU channel tranmitting operation ................................................................................ 65
Memory channel receiving operation (1) ...................................................................... 66
Memory channel receiving operation (2) ...................................................................... 67
page 5 of 13
List of figures
38K0 Group
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
96 Memory channel receiving operation (3) ...................................................................... 68
97 Memory channel tranmitting operation (1) .................................................................... 69
98 Memory channel tranmitting operation (2) .................................................................... 70
99 Multichannel RAM timing diagram (no wait) ................................................................ 71
100 Multichannel RAM timing diagram (one wait) ............................................................ 71
101 Multichannel RAM operation example ......................................................................... 72
102 Structure of AD control register ................................................................................... 73
103 10-bit A/D mode reading .............................................................................................. 73
104 A/D converter block diagram ........................................................................................ 74
105 Block diagram of Watchdog timer ............................................................................... 75
106 Structure of Watchdog timer control register ............................................................. 75
108 Reset sequence ............................................................................................................. 76
107 Example of reset circuit ................................................................................................ 76
109 Block diagram of PLL circuit ........................................................................................ 77
110 Structure of PLL control register ................................................................................. 78
111 Ceramic resonator or quartz-crystal oscilltor circuit ................................................. 80
112 External clock input circuit ........................................................................................... 80
114 System clock generating circuit block diagram (single-chip mode) ........................ 80
113 Structure of MISRG ....................................................................................................... 80
115 State transitions of clock .............................................................................................. 81
116 Block diagram of built-in flash memory ...................................................................... 83
117 Structure of flash memory control register ................................................................. 84
118 CPU rewrite mode set/release flowchart .................................................................... 85
119 Program flowchart .......................................................................................................... 87
120 Erase flowchart .............................................................................................................. 88
121 Full status check flowchart and remedial procedure for errors .............................. 90
122 Structure of ROM code protect control register ........................................................ 91
123 ID code store addresses .............................................................................................. 92
124 Pin connection diagram in standard serial I/O mode (1) ......................................... 96
125 Timing for page read ..................................................................................................... 98
126 Timing for reading status register ............................................................................... 98
127 Timing for clear status register .................................................................................... 99
128 Timing for page program .............................................................................................. 99
129 Timing for erase all blocks ......................................................................................... 100
130 Timing for download .................................................................................................... 101
131 Timing for version information output ....................................................................... 102
132 Timing for Boot ROM area output ............................................................................. 102
133 Timing for ID check ..................................................................................................... 103
134 ID code storage addresses ........................................................................................ 103
135 Full status check flowchart and remedial procedure for errors ............................ 106
136 Example circuit application for standard serial I/O mode ...................................... 107
137 Definition of A/D conversion accuracy ...................................................................... 109
138 A/D conversion equivalent circuit .............................................................................. 112
139 A/D conversion timing chart ....................................................................................... 112
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 6 of 13
List of figures
38K0 Group
CHAPTER 2 APPLICATION
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
2.1.1 Memory map of registers related to I/O port .............................................................. 2
2.1.2 Structure of Port Pi (i = 0 to 6) .................................................................................... 3
2.1.3 Structure of Port Pi direction register (i = 0 to 6) ..................................................... 3
2.1.4 Structure of Port P0 pull-up control register ............................................................... 4
2.1.5 Structure of Port P5 pull-up control register ............................................................... 4
2.2.1 Memory map of registers related to interrupt ............................................................. 8
2.2.2 Structure of Interrupt request register 1 ...................................................................... 8
2.2.3 Structure of Interrupt request register 2 ...................................................................... 9
2.2.4 Structure of Interrupt control register 1 ....................................................................... 9
2.2.5 Structure of Interrupt control register 2 ..................................................................... 10
2.2.6 Structure of Interrupt edge selection register ........................................................... 10
2.2.7 Interrupt operation diagram .......................................................................................... 12
2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request
........................................................................................................................................ 13
2.2.9 Time up to execution of interrupt processing routine .............................................. 14
2.2.10 Timing chart after acceptance of interrupt request .............................................. 14
2.2.11 Interrupt control diagram ............................................................................................ 15
2.2.12 Example of multiple interrupts ................................................................................... 17
2.2.13 Connection example and port P0 block diagram when using key input interrupt .
...................................................................................................................................... 19
2.2.14 Registers setting related to key input interrupt (corresponding to Figure 2.2.13) .
...................................................................................................................................... 20
2.2.15 Sequence of changing relevant register .................................................................. 21
2.2.16 Sequence of check of interrupt request bit ............................................................. 22
2.3.1 Memory map of registers related to timers ............................................................... 23
2.3.2 Structure of Prescaler 12, Prescaler X ...................................................................... 23
2.3.3 Structure of Timer 1 ..................................................................................................... 24
2.3.4 Structure of Timer 2, Timer X ..................................................................................... 24
2.3.5 Structure of Timer X mode register ............................................................................ 25
2.3.6 Structure of Interrupt request register 1 .................................................................... 26
2.3.7 Structure of Interrupt request register 2 .................................................................... 26
2.3.8 Structure of Interrupt control register 1 ..................................................................... 27
2.3.9 Structure of Interrupt control register 2 ..................................................................... 27
2.3.10 Timers connection and setting of division ratios .................................................... 29
2.3.11 Related registers setting ............................................................................................ 29
2.3.12 Control procedure ........................................................................................................ 30
2.3.13 Peripheral circuit example .......................................................................................... 31
2.3.14 Timers connection and setting of division ratios .................................................... 31
2.3.15 Related registers setting ............................................................................................ 32
2.3.16 Control procedure ........................................................................................................ 32
2.3.17 Judgment method of valid/invalid of input pulses .................................................. 33
2.3.18 Related registers setting ............................................................................................ 34
2.3.19 Control procedure ........................................................................................................ 35
2.3.20 Timers connection and setting of division ratios .................................................... 36
2.3.21 Related registers setting ............................................................................................ 37
2.3.22 Control procedure ........................................................................................................ 38
2.4.1 Memory map of registers related to Serial I/O ......................................................... 40
2.4.2 Structure of Transmit/Receive buffer register ........................................................... 41
2.4.3 Structure of Serial I/O status register ........................................................................ 41
2.4.4 Structure of Serial I/O control register ....................................................................... 42
2.4.5 Structure of UART control register ............................................................................. 42
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 7 of 13
List of figures
38K0 Group
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
2.4.6 Structure of Baud rate generator ................................................................................ 43
2.4.7 Structure of Interrupt edge selection register ........................................................... 43
2.4.8 Structure of Interrupt request register 2 .................................................................... 44
2.4.9 Structure of Interrupt control register 2 ..................................................................... 44
2.4.10 Serial I/O connection examples (1) .......................................................................... 45
2.4.11 Serial I/O connection examples (2) .......................................................................... 46
2.4.12 Serial I/O transfer data format .................................................................................. 47
2.4.13 Connection diagram .................................................................................................... 48
2.4.14 Timing chart ................................................................................................................. 48
2.4.15 Registers setting related to transmitting side ......................................................... 49
2.4.16 Registers setting related to receiving side .............................................................. 50
2.4.17 Control procedure of transmitting side ..................................................................... 51
2.4.18 Control procedure of receiving side ......................................................................... 52
2.4.19 Connection diagram .................................................................................................... 53
2.4.20 Timing chart ................................................................................................................. 53
2.4.22 Setting of serial I/O transmission data .................................................................... 54
2.4.21 Registers setting related to Serial I/O ..................................................................... 54
2.4.23 Control procedure of Serial I/O ................................................................................. 55
2.4.24 Connection diagram .................................................................................................... 56
2.4.25 Timing chart ................................................................................................................. 57
2.4.26 Related registers setting ............................................................................................ 57
2.4.27 Control procedure of master unit .............................................................................. 58
2.4.28 Control procedure of slave unit ................................................................................ 59
2.4.29 Connection diagram (Communication using UART) ............................................... 60
2.4.30 Timing chart (using UART) ........................................................................................ 60
2.4.31 Registers setting related to transmitting side ......................................................... 62
2.4.32 Registers setting related to receiving side .............................................................. 63
2.4.33 Control procedure of transmitting side ..................................................................... 64
2.4.34 Control procedure of receiving side ......................................................................... 65
2.4.35 Sequence of setting serial I/O control register again ............................................ 67
2.7.1 Memory map of registers related to A/D converter .................................................. 71
2.7.2 Structure of AD control register .................................................................................. 71
2.7.3 Structure of AD conversion register 1 ....................................................................... 72
2.7.4 Structure of AD conversion register 2 ....................................................................... 72
2.7.5 Structure of Interrupt request register 2 .................................................................... 73
2.7.6 Structure of Interrupt control register 2 ..................................................................... 73
2.7.7 Connection diagram ...................................................................................................... 74
2.7.8 Related registers setting .............................................................................................. 74
2.7.9 Control procedure for 8-bit read ................................................................................. 75
2.7.10 Control procedure for 10-bit read ............................................................................. 75
2.8.1 Memory map of registers related to watchdog timer ............................................... 77
2.8.2 Structure of Watchdog timer control register ............................................................ 77
2.8.3 Structure of CPU mode register ................................................................................. 78
2.8.4 Watchdog timer connection and division ratio setting ............................................. 79
2.8.5 Related registers setting .............................................................................................. 80
2.8.6 Control procedure .......................................................................................................... 80
2.9.1 Example of poweron reset circuit ............................................................................... 81
2.9.2 RAM backup system ..................................................................................................... 81
2.10.1 Memory map of registers related to PLL ................................................................. 83
2.10.2 Structure of USB control register ............................................................................. 83
2.10.3 Structure of CPU mode register ............................................................................... 84
2.10.4 Structure of PLL control register .............................................................................. 84
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 8 of 13
List of figures
38K0 Group
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
2.10.5 Block diagram for frequency synthesizer circuit ..................................................... 85
2.10.6 Related registers setting when hardware reset ...................................................... 86
2.10.7 Related registers setting when stop mode .............................................................. 87
2.10.8 Related registers setting when recovery from stop mode .................................... 88
2.11.1 Memory map of registers related to clock generating circuit ............................... 89
2.11.2 Structure of USB control register ............................................................................. 89
2.11.3 Structure of CPU mode register ............................................................................... 90
2.11.4 Structure of PLL control register .............................................................................. 90
2.11.5 Related registers setting ............................................................................................ 91
2.11.6 Related registers setting ............................................................................................ 93
2.12.1 Memory map of registers related to standby function ........................................... 94
2.12.2 Structure of MISRG .................................................................................................... 94
2.12.3 Oscillation stabilizing time at restoration by reset input ....................................... 96
2.12.4 Execution sequence example at restoration by occurrence of INT0 interrupt request
...................................................................................................................................... 98
2.12.5 Reset input time ........................................................................................................ 100
2.13.1 Memory map of flash memory version for 38K0 Group ...................................... 102
2.13.2 Memory map of registers related to flash memory .............................................. 103
2.13.3 Structure of Flash memory control register ........................................................... 103
2.13.4 Rewrite example of built-in flash memory in standard serial I/O mode ............ 106
2.13.5 Connection example in standard serial I/O mode (1) .......................................... 107
2.13.6 Connection example in standard serial I/O mode (2) .......................................... 107
2.13.7 Connection example in standard serial I/O mode (3) .......................................... 108
2.13.8 Example of rewrite system for built-in flash memory in CPU rewrite mode .... 109
2.13.9 CPU rewrite mode beginning/release flowchart .................................................... 110
CHAPTER 3 APPENDIX
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.1.1 Output switching characteristics measurement circuit ............................................. 11
3.1.2 USB output switching characteristics measurement circuit (1) for D0- ................. 13
3.1.3 USB output switching characteristics measurement circuit (2) for D0+ ................ 13
3.1.4 Timing chart (1) ............................................................................................................. 14
3.1.5 Timing chart (2) ............................................................................................................. 15
3.1.6 Timing chart (3) ............................................................................................................. 16
3.1.7 Timing chart (4) ............................................................................................................. 17
3.1.8 Timing chart (5) ............................................................................................................. 18
3.1.9 Timing chart (6) ............................................................................................................. 19
3.2.1 Sequence of changing relevant register .................................................................... 22
3.2.2 Sequence of check of interrupt request bit ............................................................... 23
3.2.3 Sequence of setting serial I/O control register again .............................................. 25
3.2.4 Initialization of processor status register ................................................................... 29
3.2.5 Sequence of PLP instruction execution ..................................................................... 29
3.2.6 Stack memory contents after PHP instruction execution ........................................ 29
3.2.7 Status flag at decimal calculations ............................................................................. 30
3.3.1 Selection of packages .................................................................................................. 32
3.3.3 Wiring for clock I/O pins .............................................................................................. 33
3.3.4 Wiring for CNV SS pin ..................................................................................................... 33
3.3.5 Wiring for the V PP pin of the flash memory version ................................................. 34
3.3.6 Bypass capacitor across the V SS line and the V CC line ........................................... 34
3.3.7 Analog signal line and a resistor and a capacitor ................................................... 35
3.3.8 Wiring for ___________
a large current signal line ......................................................................... 36
3.3.9 Wiring of RESET pin .................................................................................................... 36
3.3.10 V SS pattern on the underside of an oscillator ......................................................... 37
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 9 of 13
List of figures
38K0 Group
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.3.11 Setup for I/O ports ...................................................................................................... 37
3.3.12 Watchdog timer by software ...................................................................................... 38
3.4.1 Structure of Port Pi ....................................................................................................... 39
3.4.2 Structure of Port Pi direction register ........................................................................ 39
3.4.3 Structure of USB control register ................................................................................ 40
3.4.4 Structure of USB function enable register ................................................................. 40
3.4.5 Structure of USB function address register ............................................................... 40
3.4.6 Structure of Frame number register Low ................................................................... 41
3.4.7 Structure of Frame number register High .................................................................. 41
3.4.8 Structure of USB interrupt source enable register ................................................... 41
3.4.9 Structure of USB interrupt source register ................................................................ 42
3.4.10 Structure of Endpoint index register ......................................................................... 42
3.4.11 Structure of EP00 stage register .............................................................................. 43
3.4.12 Structure of EP01 set register .................................................................................. 43
3.4.13 Structure of EP02 set register .................................................................................. 44
3.4.14 Structure of EP03 set register .................................................................................. 44
3.4.15 Structure of EP00 control register 1 ........................................................................ 45
3.4.16 Structure of EP01 control register 1 ........................................................................ 45
3.4.17 Structure of EP02 control register 1 ........................................................................ 45
3.4.18 Structure of EP03 control register 1 ........................................................................ 46
3.4.19 Structure of EP00 control register 2 ........................................................................ 46
3.4.20 Structure of EP01 control register 2 ........................................................................ 46
3.4.21 Structure of EP02 control register 2 ........................................................................ 47
3.4.22 Structure of EP03 control register 2 ........................................................................ 47
3.4.23 Structure of EP00 control register 3 ........................................................................ 47
3.4.24 Structure of EP01 control register 3 ........................................................................ 48
3.4.25 Structure of EP02 control register 3 ........................................................................ 48
3.4.26 Structure of EP03 control register 3 ........................................................................ 48
3.4.27 Structure of EP00 interrupt source register ............................................................ 49
3.4.28 Structure of EP01 interrupt source register ............................................................ 50
3.4.29 Structure of EP02 interrupt source register ............................................................ 50
3.4.30 Structure of EP03 interrupt source register ............................................................ 51
3.4.31 Structure of EP00 byte number register .................................................................. 51
3.4.32 Structure of EP01 byte number register 0 .............................................................. 51
3.4.33 Structure of EP02 byte number register 0 .............................................................. 52
3.4.34 Structure of EP03 byte number register 0 .............................................................. 52
3.4.35 Structure of EP01 byte number register 1 .............................................................. 52
3.4.36 Structure of EP02 byte number register 1 .............................................................. 53
3.4.37 Structure of EP03 byte number register 1 .............................................................. 53
3.4.38 Structure of Prescaler12, Prescaler X ..................................................................... 53
3.4.39 Structure of Timer 1 ................................................................................................... 54
3.4.40 Structure of Timer 2, Timer X ................................................................................... 54
3.4.41 Structure of Timer X mode register ......................................................................... 55
3.4.42 Structure of Transmit/Receive buffer register ......................................................... 55
3.4.43 Structure of Serial I/O status register ...................................................................... 56
3.4.44 Structure of EXB interrupt source enable register ............................................... 56
3.4.45 Structure of EXB interrupt source register .............................................................. 57
3.4.46 Structure of EXB index register ................................................................................ 57
3.4.47 Structure of Register window 1 ................................................................................. 58
3.4.48 Index00[low]; Structure of External I/O configuration register ............................ 58
3.4.49 Index01[low]; Structure of Transmit/Receive buffer register ................................. 59
3.4.50 Index02[low]; Structure of Memory channel operation mode register ................. 59
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 10 of 13
List of figures
38K0 Group
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.4.51
3.4.52
3.4.53
3.4.54
3.4.55
3.4.56
3.4.57
3.4.58
3.4.59
3.4.60
3.4.61
3.4.62
3.4.63
3.4.64
3.4.65
3.4.66
3.4.67
3.4.68
3.4.69
3.4.70
3.4.71
3.4.72
3.4.73
3.4.74
3.4.75
3.4.76
3.4.77
3.4.78
3.4.79
3.4.80
3.4.81
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Index03[low]; Structure of Memory address counter .............................................. 59
Index04[low]; Structure of End address register .................................................... 60
Structure of Register window 2 ................................................................................. 60
Index00[high]; Structure of External I/O configuration register ........................... 60
Index03[high]; Structure of Memory address counter ............................................ 61
Index04[high]; Structure of End address register ................................................... 61
Structure of AD control register ................................................................................ 61
Structure of AD conversion register 1 ..................................................................... 62
Structure of AD conversion register 2 ..................................................................... 62
Structure of Watchdog timer control register .......................................................... 63
Structure of CPU mode register ............................................................................... 63
Structure of Interrupt request register 1 .................................................................. 64
Structure of Interrupt request register 2 .................................................................. 64
Structure of Interrupt control register 1 ................................................................... 65
Structure of Interrupt control register 2 ................................................................... 65
Structure of Serial I/O control register ..................................................................... 66
Structure of UART control register ........................................................................... 66
Structure of Baud rate generator .............................................................................. 67
Structure of EP01 MAX. packet size register ......................................................... 67
Structure of EP02 MAX. packet size register ......................................................... 67
Structure of EP03 MAX. packet size register ......................................................... 68
Structure of EP00 buffer area set register .............................................................. 68
Structure of EP01 buffer area set register .............................................................. 68
Structure of EP02 buffer area set register .............................................................. 69
Structure of EP03 buffer area set register .............................................................. 69
Structure of Port P0 pull-up control register ........................................................... 70
Structure of Port P5 pull-up control register ........................................................... 70
Structure of Interrupt edge selection register ......................................................... 71
Structure of PLL control register .............................................................................. 71
Structure of MISRG .................................................................................................... 72
Structure of Flash memory control register ............................................................. 72
page 11 of 13
List of tables
38K0 Group
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1 Pin description ................................................................................................................... 4
2 List of 38K0 group products (L version) ....................................................................... 6
3 Push and pop instructions of accumulator or processor status register .................. 8
4 Set and clear instructions of each bit of processor status register .......................... 9
5 I/O ports functions .......................................................................................................... 13
6 Interrupt vector addresses and priority ........................................................................ 17
7 USB interrupt sources .................................................................................................... 30
8 Summary of 38K0 group’s flash memory version ...................................................... 82
9 List of software commands (CPU rewrite mode) ....................................................... 87
10 Definition of each bit in status register ..................................................................... 89
11 Description of pin function (Standard Serial I/O Mode) .......................................... 95
12 Software commands (Standard serial I/O mode) ..................................................... 97
13 Status register (SRD) ................................................................................................. 104
14 Status register 1 (SRD1) ........................................................................................... 104
15 Relative formula for a reference voltage VREF of A/D converter and Vref ...... 111
16 Change of AD conversion register during A/D conversion ................................... 111
CHAPTER 2 APPLICATION
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
2.1.1 Handling of unused pins ............................................................................................. 5
2.2.1 Interrupt sources, vector addresses and priority of 38K0 group ......................... 11
2.2.2 List of interrupt bits according to interrupt source ................................................ 16
2.3.1 CNTR 0 active edge selection bit function ............................................................... 25
2.4.1 Setting examples of Baud rate generator values and transfer bit rate values . 61
2.10.1 PLL operation mode selection bits setting example ........................................... 85
2.10.2 USB clock division ratio selection bits setting example ..................................... 86
2.11.1 Example of internal clock f(f) generation using main clock f(X IN) ..................... 91
2.11.2 Example of internal clock f(f) generation using fSYN ........................................ 92
2.12.1 State in stop mode .................................................................................................. 95
2.12.2 State in wait mode ................................................................................................... 99
2.13.1 Setting of programmers when parallel programming ........................................ 104
2.13.2 Connection example to flash programmer when serial programming (4 wires) ..
................................................................................................................................ 104
Table 2.13.3 Setting condition in serial I/O mode .................................................................. 106
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 12 of 13
List of tables
38K0 Group
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings .......................................................................................... 2
Table 3.1.2 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20
to 85°C, unless otherwise noted) ............................................................................ 3
Table 3.1.3 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20
to 85°C, unless otherwise noted) ............................................................................ 4
Table 3.1.4 Electrical characteristics (1) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C,
unless otherwise noted) ............................................................................................ 5
Table 3.1.5 Electrical characteristics (2) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C,
unless otherwise noted) ............................................................................................ 6
Table 3.1.6 AD Converter characteristics (VCC = 3.00 to 5.25 V, V SS = 0 V, Ta = –20 to 85°C,
unless otherwise noted) ............................................................................................ 7
Table 3.1.7 Timing requirements (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless
otherwise noted) ......................................................................................................... 8
Table 3.1.8 Timing requirements (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless
otherwise noted) ......................................................................................................... 8
Table 3.1.9 Timing requirements of external bus interface (EXB) (1) (VCC = 4.00 to 5.25 V, VSS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted) ............................................ 9
Table 3.1.10 Timing requirements of external bus interface (EXB) (2) (VCC = 3.00 to 4.00 V, VSS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted) .......................................... 10
Table 3.1.11 Switching characteristics (1) (V CC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C,
unless otherwise noted) .......................................................................................... 11
Table 3.1.12 Switching characteristics (2) (V CC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C,
unless otherwise noted) .......................................................................................... 11
Table 3.1.13 Switching characteristics of external bus interface (EXB) (1) (V CC = 4.00 to 5.25
V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) .............................. 12
Table 3.1.14 Switching characteristics of external bus interface (EXB) (2) (V CC = 3.00 to 4.00
V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) .............................. 12
Table 3.1.15 Switching characteristics (USB ports) (V CC = 3.00 to 5.25 V, V SS = 0 V, Ta = –20
to 85 °C, unless otherwise noted) ........................................................................ 13
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 13 of 13
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USAGE
DATA REQUIRED FOR MASK ORDERS
FUNCTIONAL DESCRIPTION
SUPPLEMENT
HARDWARE
38K0 Group
DESCRIPTION/FEATURES/PIN CONFIGURATION
DESCRIPTION
• Timers ............................................................................. 8-bit ✕ 3
•Watchdog timer ............................................................. 16-bit ✕ 1
• Serial Interface
The 38K0 group is the 8-bit microcomputer based on the 740 family core technology.
The 38K0 group has the USB function, an 8-bit bus interface, a
Serial Interface, three 8-bit timers, and an 8-channel 10-bit A/D
converter, which are available for the PC peripheral I/O device.
The various microcomputers in the 38K0 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
Serial I/O (UART or Clock-synchronized) ...................... 8-bit ✕ 1
A/D converter ................................................ 10-bit ✕ 8 channels
(8-bit reading available)
LED direct drive port ................................................................... 4
Clock generating circuit
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage (L version)
System clock/Internal clock division mode
At 12 MHz/2-divide mode(φ = 6 MHz) ................... 4.00 to 5.25 V
At 8 MHz/Through mode (φ = 8 MHz) ................... 4.00 to 5.25 V
At 6 MHz/Through mode (φ = 6 MHz) ................... 3.00 to 5.25 V
Power dissipation
At 5 V power source voltage .................................. 125 mW (typ.)
(at 8 MHz system clock, in through mode)
At 3.3 V power source voltage ................................ 30 mW (typ.)
(at 6 MHz system clock, in through mode)
Operating temperature range .................................... –20 to 85°C
Packages
FP ............................ PLQP0064GA-A (64-pin 14 ✕ 14 mm LQFP)
HP ............................ PLQP0064KB-A (64-pin 10 ✕ 10 mm LQFP)
•
•
•
•
FEATURES
• Basic machine-language instructions ....................................... 71
• The minimum instruction execution time .......................... 0.25 µs
(at 8 MHz system clock✻)
Reference frequency to internal circuit except
USB function
•
• Memory size
•
•
33
34
35
36
37
38
41
39
42
40
43
44
45
46
P05
P04
P03
P02
P01
P00
P57
P56
P55
P54
P53
P52/INT1
P51/CNTR0
P50/INT0
P27
P26
47
48
PIN CONFIGURATION (TOP VIEW)
P06
P07
P40/EXDREQ/RXD
P41/EXDACK/TXD
49
32
50
31
51
30
52
29
P42/EXTC/SCLK
P43/EXA1/SRDY
P30
P31
P32
P33/EXINT
P34/EXCS
P35/EXWR
P36/EXRD
P37/EXA0
P10/DQ0/AN0
P11/DQ1/AN1
53
28
54
27
55
56
M38K07M4L-XXXFP/HP
57
58
26
25
24
M38K09F8LFP/HP
23
11
12
13
14
15
16
XIN
XOUT
VCC
CNVSS2
P60(LED0)
10
VCCE
VREF
VSS
P12/DQ2/AN2
P13/DQ3/AN3
P14/DQ4/AN4
P15/DQ5/AN5
P16/DQ6/AN6
P17/DQ7/AN7
CNVSS
RESET
8
17
7
18
64
6
19
63
4
20
62
5
21
61
3
22
60
1
59
2
•
•
•
•
•
ROM ................................................................ 16 K to 32 K bytes
RAM ............................................................... 1024 to 2048 bytes
Programmable input/output ports ............................................. 48
Software pull-up resistors
Interrupts .................................................. 15 sources, 15 vectors
USB function (Full-Speed USB2.0 specification) ...... 4 endpoints
External bus interface ....................................... 8-bit ✕ 1 channel
9
System
clock✻:
P25
P24
P23
P22
P21
P20
D0D0+
TrON
USBVREF
DVCC
PVCC
PVSS
P63(LED3)
P62(LED2)
P61(LED1)
Package type : PLQP0064GA-A (64P6U-A)/PLQP0064KB-A (64P6Q-A)
Fig. 1 Pin configuration of 38K0 group
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 2 of 112
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
12
Fig. 2 Functional block diagram
page 3 of 112
13
P6 (4)
35 36 37 38 39 40 41 42
INT1
INT0
RAM
P5 (8)
Watchdog timer
Clock
generating
circuit
21
51 52 53 54
P4 (4)
SI/O
RAM
I/F
9
VCCE
14
VCC
P3 (8)
55 56 57 58 59 60 61 62
EXTBUS (8)
ROM
Data bus
11
VSS
23
24
25
26
DVCC
TrON
D0USBVREF
D0+
22
USB
CPU
27 28 29 30 31 32 33 34
P2 (8)
8
RESET
VREF
10
P1 (8)
63 64 1 2 3 4 5 6
10-bit A/D
converter (8)
CNTR0
Timer X (8)
Timer 2 (8)
P0(8)
43 44 45 46 47 48 49 50
15
7
Timer 1 (8)
CNVSS2
CNVSS
38K0 Group
16 17 18 19
20
PVSS PVCC XIN XOUT
FUNCTIONAL BLOCK DIAGRAM (Package : PLQP0064GA-A/PLQP0064KB-A)
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
HARDWARE
38K0 Group
PIN DESCRIPTION
PIN DESCRIPTION
Table 1. Pin description
Pin
VCC, VSS
VCCE
CNVSS
CNVSS2
VREF
Function
Name
Function except a port function
Power source
Analog power
source
CNVSS
DVCC
PVCC, PVSS
RESET
XIN
CNVSS2
Analog reference
voltage input
Analog power
source
Reset input
Clock input
XOUT
Clock output
USBVREF
USB reference
power source
TrON
USB reference
voltage output
USB upstream
I/O
D0+, D0-
P00–P07
I/O port P0
P10/DQ0/AN0– I/O port P1
P17/DQ7/AN7
P20–P27
I/O port P2
P30–P32
I/O port P3
P33/ExINT
P34/ExCS
P35/ExWR
P36/ExRD
P37/ExA0
P40/ExDREQ/RxD I/O port P4
P41/ExDACK/TxD
P42/ExTC/SCLK
P43/ExA1/SRDY
P50/INT0
P51/CNTR0
P52/INT1
P53–P57
P60–P63
I/O port P5
I/O port P6
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
• Apply voltage of 3.0 V – 5.25 V (L version) to VCC, and 0 V to VSS.
• Power source pin for ports P1, P3, P4 and analog circuit. Connect this pin to VCC.
• This pin controls the operation mode of the chip. Connect this pin to VSS. In the flash memory
mode, this pin becoems VPP power source input pin.
• This pin controls the operation mode of the chip. Connect this pin to VSS.
• Reference voltage input pin for A/D converter.
• Power source pin for analog circuit.
• Connect the DVCC and PVCC pins to VCC, and the PVSS pin to VSS.
• Reset input pin for active “L”
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• Power source pin for USB port circuit.
In Vcc = 4.00 to 5.25 V use the built-in USB reference voltage circuit. In Vcc = 3.60 to 4.00 V apply
3.3 V power supply from the external because use of the built-in USB reference voltage circuit is
prohibited in this voltage range. In Vcc = 3.00 to 3.60 V connect this pin to VCC because use of the
built-in USB reference voltage circuit is prohibited in this voltage range.
• Output pin to pull-up D0+ by 1.5 kΩ external resistor.
• USB upstream I/O port
• USB input level
• USB output level output structure
• 8-bit I/O port
• Key input pins (key-on wake up interrupt)
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Pull-up control is enabled.
• 8-bit I/O port
• A/D converter input pins
• I/O direction register allows each pin to be individually
• External bus interface function pins
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit I/O port
• I/O direction register allows each pin to be individually
• External bus interface function pins
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• 4-bit I/O port
• Serial I/O function pins
• I/O direction register allows each pin to be individually
• External bus interface function pins
programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit I/O port
• Interrupt input pin
• I/O direction register allows each pin to be individually
• Timer X funciton pin
programmed as either input or output.
• Interrupt input pin
• CMOS compatible input level
• CMOS 3-state output structure
• 4-bit I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• CMOS compatible input level
• CMOS 3-state output structure
• Output large current for LED drive is enabled.
page 4 of 112
HARDWARE
38K0 Group
PART NUMBERING
PART NUMBERING
Product M38K0 7 M 4 - XXX FP
Package type
FP : PLQP0064GA-A package
HP : PLQP0064KB-A package
ROM number
Omitted in the flash memory version.
– : Standard
Omitted in the flash memory version.
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used as a
user’s ROM area.
However, they can be programmed or erased in
the flash memory version, so that users can
use them.
Memory type
M : Mask ROM version
F : Flash memory version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 3 Part numbering
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 5 of 112
HARDWARE
38K0 Group
GROUP EXPANSION
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 38K0 group as follows.
PLQP0064GA-A ...................... 0.8 mm-pitch plastic molded LQFP
PLQP0064KB-A ....................... 0.5 mm-pitch plastic molded LQFP
100D0M ........................... 0.65 mm-pitch metal seal PIGGY BACK
Memory Type
Support for mask ROM and flash memory versions.
Memory Size
Flash memory size .......................................................... 32 Kbytes
Mask ROM size ............................................................... 16 Kbytes
RAM size .......................................................... 1024 to 2048 bytes
Memory Expansion Plan
ROM size
(bytes)
: Mass Production
60K
M38K09F8L
32K
M38K07M4L
16K
8K
256
512
1,024
2,048
RAM size (bytes)
Fig. 4 Memory expansion plan
Currently products are listed below.
Table 2. List of 38K0 group products (L version)
As of October 2006
ROM size (bytes)
ROM size for User in ( )
RAM size (bytes)
M38K07M4L-XXXFP
M38K07M4L-XXXHP
M38K09F8LFP
M38K09F8LHP
M38K09RFS
16384
(16254)
1024
32768
(32638)
2048
—
2048
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 6 of 112
Product
Package
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
100D0M
Remarks
Mask ROM version
Flash memory version
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
[Stack Pointer (S)]
[Accumulator (A)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
Figure 6 shows the store and the return movement into the stack.
If there are registers other than those described in Figure 5, the
users need to store them with the program.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Program Counter (PC)]
The 38K0 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The CPU has the 6 registers. The register structure is shown in
Figure 5.
The program counter is a 16-bit counter consisting of two 8-bit
registers PC H and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
PCH
Stack pointer
b0
Program counter
PCL
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 7 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
POP return
address from stack
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
(S)
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 8 of 112
Push instruction to stack
Pop instruction from stack
PHA
PHP
PLA
PLP
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
N flag
Set instruction
SEC
–
SEI
SED
–
SET
–
–
Clear instruction
CLC
–
CLI
CLD
–
CLT
CLV
–
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 9 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
0
1
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1:
1 0:
Not available
1 1:
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Not used (returns “0” when read)
(Do not write “1” to this bit)
System clock selection bit
0 : Main clock (XIN)
1 : fSYN
System clock division ratio selection bits
b7 b6
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
Fig. 7 Structure of CPU mode register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 10 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs. In
the flash memory version, program and erase can be performed in
the reserved area.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 0000 16 to 00FF 16 are called the
zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page
addressing mode.
RAM area
RAM size
(bytes)
Address
XXXX16
192
00FF16
256
013F16
384
01BF16
512
023F16
640
02BF16
768
033F16
896
03BF16
1024
043F16
1536
063F16
2048
083F16
000016
SFR area
Zero page
004016
010016
RAM
XXXX16
Not used
0FE016
0FFF16
SFR area
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ16
4096
F00016
F08016
YYYY16
Reserved ROM area
(128 bytes)
8192
E00016
E08016
12288
D00016
D08016
16384
C00016
C08016
20480
B00016
B08016
24576
A00016
A08016
28672
900016
908016
32768
800016
808016
36864
700016
708016
40960
600016
608016
45056
500016
508016
49152
400016
408016
53248
300016
308016
FFFE16
57344
200016
208016
FFFF16
61440
100016
108016
Fig. 8 Memory map diagram
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 11 of 112
ZZZZ16
ROM
FF0016
FFDC16
Interrupt vector area
Reserved ROM area
Special page
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
000216 Port P1 (P1)
000316 Port P1 direction register (P1D)
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
000616 Port P3 (P3)
000716 Port P3 direction register (P3D)
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
000A16 Port P5 (P5)
000B16 Port P5 direction register (P5D)
000C16 Port P6 (P6)
000D16 Port P6 direction register (P6D)
000E16 Reserved (Note)
000F16 Reserved (Note)
001016 USB control register (USBCON)
001116 USB function enable register (USBAE)
002016 Prescaler 12 (PRE12)
002116 Timer 1 (T1)
002216 Timer 2 (T2)
002316 Timer X mode register (TM)
002416 Prescaler X (PREX)
002516 Timer X (TX)
002616 Transmit/Receive buffer register (TB/RB)
002716 Serial I/O status register (SIOSTS)
002816 Reserved (Note)
002916 Reserved (Note)
002A16 Reserved (Note)
002B16 Reserved (Note)
002C16 Reserved (Note)
002D16 Reserved (Note)
002E16 Reserved (Note)
002F16 Reserved (Note)
003016 EXB interrupt source enable register (EXBICON)
003116 EXB interrupt source register (EXBIREQ)
001216 USB function address register (USBA0)
001316 Reserved (Note)
001416 Frame number register Low (FNUML)
003216 Reserved (Note)
003316 EXB index register (EXBINDEX)
003416 EXB field register 1 (EXBREG1)
001516 Frame number register High (FNUMH)
001616 USB interrupt source enable register (USBICON)
001716 USB interrupt source register (USBIREQ)
001816 Endpoint index register (USBINDEX)
001916 Endpoint field register 1 (EPXXREG1)
003516 EXB field register 2 (EXBREG2)
003616 AD control register (ADCON)
003716 AD conversion register 1 (AD1)
001A16 Endpoint field register 2 (EPXXREG2)
001B16 Endpoint field register 3 (EPXXREG3)
001C16 Endpoint field register 4 (EPXXREG4)
001D16 Endpoint field register 5 (EPXXREG5)
003A16 Reserved (Note)
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1(IREQ1)
003816 AD conversion register 2 (AD2)
003916 Watchdog timer control register (WDTCON)
001E16 Endpoint field register 6 (EPXXREG6)
001F16 Endpoint field register 7 (EPXXREG7)
003D16 Interrupt request register 2(IREQ2)
003E16 Interrupt control register 1(ICON1)
003F16 Interrupt control register 2(ICON2)
0FE016 Serial I/O control register (SIOCON)
0F E116 UART control register (UARTCON)
0FE216 Baud rate generator (BRG)
0FF016 Port P0 pull-up control register (PULL0)
0FF116 Reserved (Note)
0FF216 Port P5 pull-up control register (PULL5)
0F E316 Reserved (Note)
0F E416 Reserved (Note)
0FF316
0FF416
0FF516
0FF616
0FE516 Reserved
0F E616 Reserved
0F E716 Reserved
0FE816 Reserved
0F E916 Reserved
(Note)
(Note)
(Note)
(Note)
(Note)
0FEA16 Reserved (Note)
0FEB16 Reserved (Note)
0FEC16 Endpoint field register 8 (EPXXREG8)
0FED16 Endpoint field register 9 (EPXXREG9)
0FEE16 Reserved (Note)
0FEF16 Reserved (Note)
Interrupt edge selection register (INTEDGE)
Reserved (Note)
Reserved (Note)
Reserved (Note)
0FF716 Reserved (Note)
0FF816 PLL control register (PLLCON)
0FF916 Reserved (Note)
0FFA16 Reserved (Note)
0FFB16 MISRG
0FF C16 Reserved (Note)
0FF D16 Reserved (Note)
0FFE16 Flash memory control register (FMCR)
0F FF16 Reserved (Note)
Note: Do not write any data to these addresses, because these areas are reserved.
Fig. 9 Memory map of special function register (SFR)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 12 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Table 5 I/O ports functions
Pin
Name
P00–P07
Port P0
P10–P17
Port P1
P20–P27
Port P2
P30–P32
P33/ExINT
Port P3
P34/ExCS
P35/ExWR
P36/ExRD
P37/ExA0
P40/RxD/
ExDREQ
Input/Output
I/O Format
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
(Power source is
VCCE)
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
(Power source is
VccE)
Port P4
P41/TxD/
ExDACK
P42/SCLK/
ExTC
P43/SRDY/
ExA1
P50/INT0
P52/INT1
P51/CNTR0
P53–P57
P60–P63
CMOS compatible
input level
CMOS 3-state output
Port P5
Non-Port Function
Diagram No.
Port P0 pull-up control
register
(1)
A/D conversion input
External bus interface
funciton I/O
AD control register
EXB control register
(2)
(3)
External bus interface
funciton output
External bus interface
funciton input
EXB control register
(4)
(5)
EXB control register
(6)
Serial I/O input
External bus interface
funciton output
Serial I/O output
External bus interface
funciton input
Serial I/O I/O
External bus interface
funciton input
Serial I/O output
External bus interface
funciton input
External interrupt input
Serial I/O control
register
EXB control register
Serial I/O control
register
EXB control register
Serial I/O control
register
EXB control register
Serial I/O control
register
EXB control register
Port P5 pull-up control
register
Interrupt edge selection
register
Timer X mode register
(7)
Timer X function I/O
Port P6
Related SFRs
Key-on wake up
(8)
(9)
(10)
(11)
(12)
(13)
(14)
Note: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 13 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(1) Port P0
(4) Ports P30–P32
Pull-up control bit
Direction register
Direction register
Data bus
Port latch
Data bus
VCCE
Port latch
Key-on wake-up input
(5) Port P33
(2) Port P1
EXOE
VCCE
VCCE
External bus interface enable bit
External bus interface enable bit
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
EXINT output
EXB data output
Output buffer
EXB data input
Input buffer
(6) Ports P34, P35, P36, P37
VCCE
External bus interface enable bit
A/D conversion input
Direction register
Analog input pin selection bit
Data bus
Port latch
(3) Port P2
Direction register
Data bus
Port latch
Fig. 10 Port block diagram (1)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 14 of 112
EXCS(P34)
EXWR(P35)
EXRD(P36)
EXA0(P37)
External bus interface enable bit
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(11) Ports P50, P52
(7) Port P40
Pull-up control bit
Serial I/O enable bit
Receive enable bit
VCCE
Direction register
External bus interface enable bit
Direction register
Data bus
Data bus
Port latch
Port latch
INT0 (P50), INT1 (P52) interrupt input
EXDreq output
Serial I/O input
(8) Port P41
(12) Port P51
Serial I/O enable bit
Receive enable bit
VCCE
Direction register
External bus interface enable bit
Direction register
Port latch
Data bus
Data bus
Port latch
Pulse output mode
Timer output
CNTR0 interrupt input
Serial I/O output
EXDack
External bus interface enable bit
(13) Ports P53–P57
(9) Port P42
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O synchronous clock selection bit
Serial I/O enable bit
External bus interface enable bit
Direction register
Data bus
Direction register
VCCE
Port latch
Data bus
Port latch
Serial I/O clock output
(14) Port P6
Serial I/O external clock input
Serial I/O synchronous clock selection bit
External bus interface enable bit
EXTC
(10) Port P43
Data bus
Serial I/O mode selection bit
Serial I/O enable bit
SRDY output enable bit
VCCE
External bus interface enable bit
Direction register
Data bus
Port latch
Serial I/O output
EXA1
Fig. 11 Port block diagram (2)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 15 of 112
External bus interface enable bit
Direction register
Port latch
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b7
b0
Port P0 pull-up control register
(PULL0 : address 0FF016)
P00 pull-up control bit
0 : No pull-up
1 : Pull-up
P01 pull-up control bit
0 : No pull-up
1 : Pull-up
P02 pull-up control bit
0 : No pull-up
1 : Pull-up
P03 pull-up control bit
0 : No pull-up
1 : Pull-up
P04 pull-up control bit
0 : No pull-up
1 : Pull-up
P05 pull-up control bit
0 : No pull-up
1 : Pull-up
P06 pull-up control bit
0 : No pull-up
1 : Pull-up
P07 pull-up control bit
0 : No pull-up
1 : Pull-up
b7
b0
Port P5 pull-up control register
(PULL5 : address 0FF216)
P50 pull-up control bit
0 : No pull-up
1 : Pull-up
Nothing is arranged for this bit. This is a write disabled bit.
When this bit is read out, the contents are “0”.
P52 pull-up control bit
0 : No pull-up
1 : Pull-up
Nothing is arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0”.
Fig. 12 Structure of port I/O-related registers
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 16 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
INTERRUPTS
■Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address
0FF3 16 ), Timer X mode register (address
002316)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit (active edge switch bit).
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding interrupt enable bit to “1” (enabled).
Interrupts occur by fifteen sources: four external, ten internal, and
one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Table 6 Interrupt vector addresses and priority
Interrupt Source
Priority
Reset (Note 2)
USB bus reset
USB SOF
USB device
1
2
3
4
External bus
INT0
Timer X
Timer 1
Timer 2
INT1
(Note 3)
Serial I/O
reception
Serial I/O
transmission
CNTR0
Key-on wake up
A/D conversion
BRK instruction
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
Interrupt Request
Generating Conditions
FFE716
FFE816
FFE616
At reset
At detection of USB bus reset signal (2.5 µs interval SE0)
At detection of USB SOF signal
At detection of resume signal (K state or SE0) or suspend signal (3
ms interval bus idle), or at completion of transaction
At completion of reception or transmission or at completion of DMA
transmission
At detection of either rising or falling edge of INT0 input
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or falling edge of INT1 input
(Note 4)
At completion of serial I/O data reception
12
FFE516
FFE416
At completion of serial I/O data transmission
13
14
15
16
FFE316
FFE216
FFE016
FFDE16
FFDC16
At detection of either rising or falling edge of CNTR0 input
At falling of conjunction of input level for port P0 (at input mode)
At completion of A/D conversion
At BRK instruction execution
FFFB16
FFF716
FFFA16
FFF816
FFF616
5
FFF516
FFF416
6
7
8
9
10
—
11
FFF316
FFF116
FFED16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFF916
FFEF16
FFEB16
FFE916
FFE116
FFDF16
FFDD16
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: Nothing is arranged in these vector addresses.
4: Fix bit 1 of interrupt control register 2 (address 003F16) to “0”.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 17 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Interrupt request
BRK instruction
Reset
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 0FF316)
INT0 interrupt edge selection bit
Not used (return “0” when read)
INT1 interrupt edge selection bit
Not used (return “0” when read)
b7
b0
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
(IREQ1 : address 003C16)
b7
b0
USB bus reset interrupt request bit
USB SOF interrupt request bit
USB device interrupt request bit
EXB interrupt request bit
INT0 interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt control register 1
(ICON1 : address 003E16)
USB bus reset interrupt enable bit
USB SOF interrupt enable bit
USB device interrupt enable bit
EXB interrupt enable bit
INT0 interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
✽ “0” can be set by software, but “1”
cannot be set.
b7
b0
Interrupt request register 2
(IREQ2 : address 003D16)
INT1 interrupt request bit
Nothing is arranged for this bit. This is a
write disabled bit. When this bit is read
out, the contents are “0”.
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
CNT R0 interrupt request bit
Key-on wake-up interrupt request bit
A/D conversion interrupt request bit
Nothing is arranged for this bit. This is a
write disabled bit. When this bit is read
out, the contents are “0”.
0 : No interrupt request issued
1 : Interrupt request issued
✽ “0” can be set by software, but “1”
cannot be set.
Fig. 14 Structure of interrupt-related registers
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 18 of 112
b7
b0
Interrupt control register 2
(ICON2 : address 003F16)
INT1 interrupt enable bit
Fix this bit to “0”.
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
CNT R0 interrupt enable bit
Key-on wake-up interrupt enable bit
A/D conversion interrupt enable bit
Fix this bit to “0”.
0 : Interrupts disabled
1 : Interrupts enabled
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Key Input Interrupt (Key-on Wake Up)
A Key-on wake up interrupt request is generated by applying a
falling edge to any pin of port P0 that have been set to input mode.
In other words, it is generated when AND of input level goes from
“1” to “0”. An example of using a key input interrupt is shown in
Figure 15, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P00–P03.
Port PXx
“L” level output
PULL 0 register
Bit 7 = “0”
✽
✽✽
Port P07
direction register = “1”
Key input interrupt request
Port P07
latch
P07 output
PULL 0 register
Bit 6 = “0”
✽
✽✽
Port P06
direction register = “1”
Port P06
latch
P06 output
PULL 0 register
Bit 5 = “0”
✽
✽✽
Port P05
direction register = “1”
Port P05
latch
P05 output
PULL 0 register
Bit 4 = “0”
✽
✽✽
Port P04
direction register = “1”
Port P04
latch
P04 output
PULL 0 register
Bit 3 = “1”
✽
✽✽
Port P03
direction register = “0”
P03 input
PULL 0 register
Bit 2 = “1”
✽
✽✽
Port P02
direction register = “0”
Port P02
latch
P02 input
PULL 0 register
Bit 1 = “1”
✽
✽✽
P01 input
Port P01
direction register = “0”
Port P01
latch
PULL 0 register
Bit 0 = “1”
✽
P00 input
✽✽
Port P0
Input reading circuit
Port P03
latch
Port P00
direction register = “0”
Port P00
latch
✽ P-channel transistor for pull-up
✽ ✽ CMOS output buffer
Fig. 15 Connection example when using key input interrupt and port P0 block diagram
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 19 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
TIMERS
Timer 1 and Timer 2
The 38K0 group has three timers: timer X, timer 1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
The count source of prescaler 12 is the system clock divided by
16. The output of prescaler 12 is counted by timer 1 and timer 2,
and a timer underflow periodically sets the interrupt request bit.
Timer X
Timer X can each select in one of four operating modes by setting
the timer X mode register.
(1) Timer Mode
b7
The timer counts the count source selected by timer count source
selection bit.
b0
Timer X mode register
(TM : address 002316)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNT R0 active edge switch bit
0 : Falling edge active for CNTR0 interrupt
Count at rising edge in event counter mode
1 : Rising edge active for CNTR0 interrupt
Count at falling edge in event counter mode
Timer X count stop bit
0 : Count start
1 : Count stop
Not used (return “0” when read)
Fig. 16 Structure of timer X mode register
(2) Pulse Output Mode
The timer counts the system clock divided by 16. Whenever the
contents of the timer reach “00 16”, the signal output from the
CNTR0 pin is inverted. If the CNTR0 active edge selection bit is
“0”, output begins at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P51 direction register to output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 pin.
When the CNTR0 active edge selection bit is “0”, the rising edge of
the CNTR0 pin is counted.
When the CNTR0 active edge selection bit is “1”, the falling edge
of the CNTR0 pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 active edge selection bit is “0”, the timer counts the
system clock divided by 16 while the CNTR 0 pin is at “H”. If the
CNTR0 active edge selection bit is “1”, the timer counts it while the
CNTR0 pin is at “L”.
The count can be stopped by setting “1” to the timer X count stop
bit in any mode. The corresponding interrupt request bit is set
each time a timer underflows.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 20 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Data bus
Divider
System clock
1/16
Pulse width
m easurem ent
mode
Prescaler X latch (8)
Timer mode
Pulse output
mode
Prescaler X (8)
P51/CNTR0
CNTR0 active
edge selection bit
“0”
Event
counter
mode
Timer X latch (8)
Timer X (8)
Timer X count stop bit
CNTR0 interrupt
request bit
“1”
CNTR0 active
edge selection bit
Port P51
direction
register
Timer X interrupt
request bit
“1”
“0”
Port P51
latch
Q
Q
Toggle
flip-flop
R
T
Timer X latch write
Pulse output mode
Pulse output mode
Data bus
Prescaler 12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
Timer 1 (8)
Timer 2 (8)
Divider
System clock
1/16
Prescaler 12 (8)
Timer 2 interrupt
request bit
Timer 1 interrupt
request bit
Fig. 17 Timer block diagram
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 21 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
SERIAL I/O
also provided for baud rate generation.
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is
Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O control register (bit 6 of address 0FE016) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the Trancemit/Receive buffer register.
(1) Clock Synchronous Serial I/O Mode
Data bus
Serial I/O control register
Address 002616
Receive buffer register
Receive interrupt request (RI)
Receive shift register
P40/EXDREQ/RxD
Address 0FE016
Receive buffer full flag (RBF)
Shift clock
Clock control circuit
P42/EXTC/SCLK
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
System clock
Baud rate generator
P43/EXA1/SRDY
F/F
1/4
Address 0FE216
1/4
Clock control circuit
Falling-edge detector
Shift clock
P41/EXDACK/TxD
Transmit shift register
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address 002716
Transmit buffer register
Serial I/O status register
Address 002616
Data bus
Fig. 18 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RXD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY
Write signal to receive/transmit
buffer register (address 002616)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1 : T he transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE = 1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
3 : T he receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 19 Operation of clock synchronous serial I/O function
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 22 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(2) Asynchronous Serial I/O (UART) Mode
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Clock asynchronous serial I/O mode (UART) can be selected by
setting the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 002616
P40/EXDREQ/RxD
Serial I/O1 control register Address 0FE016
OE
Receive buffer register
Character length selection bit
STdetector
7 bits
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/16
8 bits
UART control register
Address 0FE116
SP detector
PE FE
Clock control circuit
Serial I/O synchronous clock selection bit
P42/EXTC/SCLK
BRG count source selection bit
Frequency division ratio 1/(n+1)
System clock
Baud rate generator
Address 0FE216
1/4
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
1/16
Transmit shift register
P41/EXDACK/TxD
Character length selection bit
Transmit buffer register
Address 002616
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O status register Address 002716
Data bus
Fig. 20 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE=0
TBE=0
TSC=0
TBE=1
Serial output TXD
TSC=1✽
TBE=1
ST
D0
D1
SP
ST
D0
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
✽ Generated
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
D1
SP
ST
D0
D1
SP
at 2nd bit in 2-stop-bit mode
RBF=1
SP
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : T he transmit interrupt (TI) can be generated to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3 : T he receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 21 Operation of UART serial I/O function
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 23 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
[Serial I/O Control Register (SIOCON)] 0FE016
The serial I/O control register contains eight control bits for the serial I/O function.
[UART Control Register (UARTCON)] 0FE116
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer.
[Serial I/O Status Register (SIOSTS)] 002716
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Transmit Buffer/Receive Buffer Register (TB/
RB)] 002616
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is writeonly and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer register is “0”.
[Baud Rate Generator (BRG)] 0FE216
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
■Notes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
➀Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃Set the serial I/O transmit interrupt enable bit to “1” (enabled).
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 24 of 112
HARDWARE
38K0 Group
b7
FUNCTIONAL DESCRIPTION
b0
Serial I/O status register
(SIOSTS : address 002716)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
b0
Serial I/O control register
(SIOCON : address 0FE016)
BRG count source selection bit (CSS)
0: System clock
1: System clock/4
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
External clock input divided by 16 when UART is selected.
Overrun error flag (OE)
0: No error
1: Overrun error
SRDY output enable bit (SRDY)
0: P43 pin operates as ordinary I/O pin
1: P43 pin operates as SRDY output pin
Parity error flag (PE)
0: No error
1: Parity error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Framing error flag (FE)
0: No error
1: Framing error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Not used (returns “1” when read)
Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
b7
b7
b0 UART control regi ster
(UART CON : address 0FE116)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (ST PS)
0: 1 stop bit
1: 2 stop bits
Not used (return “0” when read)
(This is a write disabled bit.)
Not used (return “1” when read)
Fig. 22 Structure of serial I/O control registers
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 25 of 112
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P40–P43 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P40–P43 can operate as serial I/O pins)
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
USB FUNCTION
38K0 Group is equipped with a USB function control circuit
(USBFCC) that enables effective interfacing with the host-PC.
This circuit is in compliance with USB2.0’s Full-Speed Transfer
Mode (12 Mbps, equivalent to USB1.1). This circuit also supports
all four transfer-types specified in the standard USB specification.
The USBFCC has four endpoints that can select its transfer type.
Although Endpoint 0 is fixed to Control Transfer, the Endpoints 1
to 3 can be set to Interrupt Transfer, Bulk Transfer, or Isochronous
Transfer.
A dedicated circuit automatically performs stage management for
Control Transfer and packet management for transactions, which
are necessary for matching of data transmit/receive timing, error
detection, and retry after error. This dedicated control circuit enables the user to develop a program or timing design very easily.
Each endpoint can be programmed for data transfer conditions so
that the endpoints are adaptive for all USB device class transfer
systems.
The data buffer of each endpoint can be assigned to any area in
the multi-channel RAM. This feature offers highly efficient memory
usage by avoiding re-buffering and enabling simple data modification.
The transmit/receive data is directly transferred to the data buffer
via the control circuit (direct RAM access type) without disturbing
the CPU operation. This mechanism enables the CPU to transfer
data smoothly with no drop in performance. In addition to this
buffer function, a double-buffer setting will keep a re-buffering stall
at a minimum and increase the overall data throughput (max. 64
bytes X 2 channels).
As other special signals control, the endpoints have detection
functions for the USB bus reset signal, resume signal, suspend
signal, and SOF signal, and also have a remote wake-up signal
transmit function.
When completing data transfer or receiving a special signal, the
endpoint generates the corresponding interrupt to the CPU (3 vectors/18 factors).
With all this essential yet comprehensive built-in hardware, your
system using the 38K0 group will be ready for any USB application that comes its way.
38K0 Group MCU
Built-in Peripheral
Functions
Program ROM
CPU
External MCU
Interrupt request
External Bus Interface
(EXB)
Multi-channel RAM
USB
USB Bus
(USB-Host)
Data transmit/Receive path
[Direct RAM Access Type]
Fig. 23 USB function overview
USB Data Transfer
The USB specification promises 12 Mbps data transfer in the fullspeed mode, that is equivalent to 1.5 M bytes per second of data
transactions.
However, in USB data transfer, bit-stuffing may be executed depending on the bit patterns of the transfer data, possibly resulting
in 1-byte data (normally 8 bits) handled as up to 10 bits.
Because USB uses asynchronous transfers, the clock cycle of the
USB internal reference clock may change to adjust to the clock
phase. Therefore, the access timing of the USBFCC for the multichannel RAM will change owing to the frequency of internal clock φ:
When the USBFCC is operating at φ =8 MHZ, access for a normal
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 26 of 112
transfer is performed every 5 to 6 cycles and access for a bit-stuffing transfer is performed in up to 7 cycles.
If the EXB function is enabled in the above conditions, this function generates a maximum wait of 1 clock cycle, so that the
access is performed every 4 to 8 cycles.
When operating at φ = 6MHZ, a normal access is performed every
4 cycles. If the clock-phase correction of the reference clock occurs, access is performed every 3 to 5 cycles.
If bit stuffing occurs at this clock rate, the access cycle will be extended to up to 6 cycles. When the EXB function that generates a
maximum 1-wait cycle is used in this condition, the access cycle
will be 2 (min.) to 7 (max.) cycles.
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
USB Function Control Circuit (USBFCC)
Block Diagram
The following diagram shows the USBFCC block diagram. The circuit comprises:
(1) Serial Interface Engine (SIE)
(2) Device Control Unit (DCU)
(3) Internal Memory Interface (MIF)
(4) CPU Interface (CIF)
USB Function Control Circuit
DCU control
MIF control
USB Transceiver
SIE
DCU
SIE status
MIF
CIF
CPU
DCU status
SIE control
D0+
D0-
Transmit/Receive
data
Multi-Channel RAM
Fig. 24 USB Function Control Circuit (USBFCC) block diagram
(1) Serial Interface Engine (SIE)
The SIE performs the following USB lower-layer protocols (packets, transactions):
•Sampling of receive data and clock, generation of transmit clock
•Serial-to-parallel conversion of transmit/receive data
•NRZI (Non Return Zero Invert) encode/decode
•Bit stuffing/unstuffing
•SYNC (Synchronization Pattern) detection, EOP (End of
Packet) detection
•USB address detection, endpoint detection
•CRC (Cyclic Redundancy Check) generation and checking
(2) Device Control Unit (DCU)
The DCU manages the following USB upper-layer protocols (address/endpoint and control-transfer sequence):
•Status control for each endpoint
•Control-transfer sequence control
•Memory interface status control
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 27 of 112
(3) Memory Interface (MIF)
The MIF controls the flow of data transfer between the SIE and the
multi-channel RAM under the management of the DCU.
(4) CPU Interface (CIF)
The CIF performs the following functions:
•Mode setting via registers, DCU control signal generation, DCU
status signal reading
•Interrupt signal generation
•Internal bus interface control.
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
USB Port External Circuit Configuration
The operation mode of the USB port driver circuit can be configured by USB control register (address 001016).
Figure 25 and Figure 26 show the USB port external circuit block
diagram.
VREFCON
VREFE
DVCC
0
1
0
Hiz
Hiz
1
3.3V output
Normal mode
3.3V output
Low-power mode
USBVREF status
VREFE
USBVREF
USB Reference
Voltage Circuit
VREFCON
2.2 µF
0.1 µF
TRON
TRONCON
TRONE
XOUT
Full
Speed
fVCO “1”
PLL
1.5 kΩ
D0+
27 Ω
D0-
27 Ω
fUSB
USB
Module
“0”
USBE
+
-
UCLKCON
USBDIFE
USBE
Full
Speed
USBE
Fig. 25 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (4.0V ≤ VCC ≤ 5.25V)
3.0V to 3.6V
(Note)
USBVREF
0.1 µF
TRON
TRONCON
TRONE
XOUT
PLL
1.5 kΩ
Full
Speed
fVCO “1”
D0+
27 Ω
D0-
27 Ω
fUSB
“0”
USB
Module
USBE
+
-
UCLKCON
USBDIFE
USBE
Full
Speed
USBE
Note: In Vcc = 3.0 V to 3.6 V connect this pin to Vcc.
Fig. 26 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram (3.0V ≤ VCC ≤ 4.0V)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 28 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Endpoint Buffer Area Setting
The buffer area used in data transfer can be assigned to any area
of the multi-channel RAM for each endpoint.
Memory
002016
●Buffer area beginning address
The buffer area configuration register (address 0FED 16) defines
the beginning address of the buffer area (every 32 bytes) for each
Endpoint. However, the only RAM area is configurable.
•00h [Address 000016], 01h [Address 002016]: Not configurable
•02h [Address 004016] to 1Fh [Address 03E016]: Configurable
●Interrupt-source dependant buffer area offset address
An offset value is added to the beginning address of each source,
which is specified by the interrupt source register (address
001D16), for each endpoint.
This section describes in detail the beginning address specified by
the buffer area set register as offset address 00h, according to
each endpoint.
(1) Endpoint 00
Endpoint 00 has two kinds of interrupt sources for accessing the
buffer. The respective address offsets are:
•BSRDY00 (SETUP Buffer Ready Interrupt): Offset address = 00h
•BRDY00 (OUT or IN Buffer Ready Interrupt):
Offset address = 08h
(2) Endpoint 01
The buffer area offset address for each interrupt source for of Endpoint 01 varies according to the contents of the EP01 set register
(address 001916).
•In single buffer mode (DBLB01 = “0”):
Endpoint 01 has only one interrupt source for accessing the
buffer.
B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h
(a) When selecting Endpoint 00
Offset
Memory
02A016
00h
02
006016
03
02A016
15
03E016
1F
Fig. 27 Example setting of buffer area beginning address
•In double buffer mode (DBLB01 = “1”):
Endpoint 01 has two kinds of interrupt sources for accessing the
buffer.
B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h
B1RDY01 (Buffer 1 Ready Interrupt):
The offset address varies according to the double buffer beginning address set bit (BSIZ01).
-Offset address = 08h when BSIZ01 = 00
-Offset address = 10h when BSIZ01 = 01
-Offset address = 40h when BSIZ01 = 10
-Offset address = 80h when BSIZ01 = 11
(3) Endpoints 02 and 03
Same as Endpoint 01.
Notes
The selected RAM area must be within addresses 0040 16 to
03FF16.
Make sure the buffer area beginning address is set in agreement
with the offset address and the number of transmit/receive data
bytes.
This is particularly important when in the double buffer mode or
when handling 64-byte data.
00h
(c) When selecting Double Buffer Mode
(when BSIZ01 = 11)
Offset
Memory
00h
02A016
B0RDY01
08h
B0RDY01
80h
032016
BRDY00
B1RDY01
Fig. 28 Examples of interrupt source dependant buffer area offset address
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Disabled to be used
01
004016
BSRDY00
02A816
SFR
RAM
Offset
02A016
00
0000 0010 1010 0000
(b) When selecting Single Buffer Mode
Memory
0FED16
000016
0FED16 = 15h
page 29 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
USB Interrupt Function
USB Interrupt Control Circuit (USBINTCON) has 3 requests and
16 USB-device interrupt request sources. Each interrupt source
register enables the user to easily determine which interrupt has
occurred.
Table 7 shows the list of USB interrupt sources.
Table 7 USB interrupt sources
Interrupt request bit
(IREQ1: Address 003C16)
USB bus reset
USB interrupt bit
(USBIREQ: Address 001716)
—
USB SOF
—
USB device
EP00
EP01
EP02
EP03
SUS
RSM
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 30 of 112
Interrupt source
At USB bus reset signal detection:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 2.5 µs SE0 state is detected in D0+/D0- port.
(Equivalent to 120-clock length when fUSB = 48 MHz)
At SOF packet receive:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when SOF packet is detected in D0+/D0- port.
Its occurrence does not depend on frame-time or CRC value after SOF
packet is transferred.
(Normally, SOF packet detection occurs only when fUSB = 48 MHz)
At Endpoint 00 data transfer complete:
•Buffer ready (read/write enabled state)
•Control transfer completed
•Status stage transition
•SETUP buffer ready (read enabled state)
•Control transfer error
At Endpoint 01 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
At Endpoint 02 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
At Endpoint 03 data transfer complete:
•Buffer 0 ready (read/write enabled state)
•Buffer 1 ready (read/write enabled state)
•Transfer error
At suspend signal detection:
After enabling the USB module (USBE = “1”), an interrupt request occurs
when 3 ms J state is detected in D0+/D0- port.
(Equivalent to 144,000 clock-length when fUSB = 48MHz)
At resume signal detection:
After enabling the USB module (USBE = “1”) and resume interrupt (RSME
= “1”), an interrupt request occurs when a bus state change (J state to
SE0 or K state) is detected in D0- port.
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
[USBIREQ]
[EPXXREG5]
[USBICON]
[EP00REQ]
BRDY00
EP00E
CTEND00
USB device
interrupt request
EP00
CTSTS00
BSYDY00
ERR00
[EP01REQ]
EP01E
B0RDY01
B1RDY01
EP01
ERR01
[EP02REQ]
EP02E
B0RDY02
B1RDY02
EP02
ERR02
[EP03REQ]
EP03E
B0RDY03
B1RDY03
EP03
ERR03
SUSE
SUS
RSME
RSM
Fig. 29 USB device interrupt control
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 31 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
USB Register List
The USB register list is shown below.
SYMBOL
USB SFR
Address
Register Name
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
USB control register
USB function enable register
USB function address register
USBCON
USBAE
USBA0
Frame number register Low
Frame number register High
USB interrupt source enable register
USB interrupt source register
Endpoint index register
Endpoint field register 1
Endpoint field register 2
Endpoint field register 3
Endpoint field register 4
Endpoint field register 5
Endpoint field register 6
Endpoint field register 7
Endpoint field register 8
Endpoint field register 9
FNUML
FNUMH
USBICON
USBIREQ
USBINDEX
EPXXREG1
EPXXREG2
EPXXREG3
EPXXREG4
EPXXREG5
EPXXREG6
EPXXREG7
EPXXREG8
EPXXREG9
EP00 stage register
EP00 control register 1
EP00 control register 2
EP00 control register 3
EP00 interrupt source register
EP00 byte number register
EP00STG
EP00CON1
EP00CON2
EP00CON3
EP00REQ
EP00BYT
EP00 buffer area set register
EP00BUF
EP01 set register
EP01 control register 1
EP01 control register 2
EP01 control register 3
EP01 interrupt source register
EP01 byte number register 0
EP01 byte number register 1
EP01 MAX. packet size register
EP01 buffer area set register
EP01CFG
EP01CON1
EP01CON2
EP01CON3
EP01REQ
EP01BYT0
EP01BYT1
EP01MAX
EP01BUF
TYP01[1:0]
EP02 set register
EP02 control register 1
EP02 control register 2
EP02 control register 3
EP02 interrupt source register
EP02 byte number register 0
EP02 byte number register 1
EP02 MAX. packet size register
EP02 buffer area set register
EP02CFG
EP02CON1
EP02CON2
EP02CON3
EP02REQ
EP02BYT0
EP02BYT1
EP02MAX
EP02BUF
TYP02[1:0]
EP03 set register
EP03 control register 1
EP03 control register 2
EP03 control register 3
EP03 interrupt source register
EP03 byte number register 0
EP03 byte number register 1
EP03 MAX. packet size register
EP03 buffer area set register
EP03CFG
EP03CON1
EP03CON2
EP03CON3
EP03REQ
EP03BYT0
EP03BYT1
EP03MAX
EP03BUF
TYP03[1:0]
bit 7
bit 6
USBE
UCLKCON
bit 5
USBDIFE
bit 4
bit 3
bit 2
bit 1
bit 0
VREFE
VREFCON
TRONE
TRONCON
WKUP
AD0E
USBADD0[6:0]
FNUM[7:0]
RSME
RSM
SUSE
SUS
EP03E
EP03
EP02E
EP02
FNUM[10:8]
EP01E
EP00E
EP01
EP00
EPIDX[1:0]
(1) Endpoint 00
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
ERR00
BSRDY00
SETUP00
PID00[1:0]
BVAL00
CTENDE00
CTSTS00
CTEND00
BRDY00
BBYT00[3:0]
BADD00[4:0]
(2) Endpoint 01
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
DIR01
ITMD01
SQCL01
DBLB01
ERR01
BSIZ01[1:0]
PID01[1:0]
B0VAL01
B1VAL01
B1RDY01
B0RDY01
B0BYT01[6:0]
B1BYT01[6:0]
MXPS01[6:0]
BADD01[4:0]
(3) Endpoint 02
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
DIR02
ITMD02
SQCL02
DBLB02
ERR02
BSIZ02[1:0]
PID02[1:0]
B0VAL02
B1VAL02
B1RDY02
B0RDY02
B0BYT02[6:0]
B1BYT02[6:0]
MXPS02[6:0]
BADD02[4:0]
(4) Endpoint 03
001916
001A16
001B16
001C16
001D16
001E16
001F16
0FEC16
0FED16
DIR03
ITMD03
SQCL03
DBLB03
ERR03
BSIZ03[1:0]
PID03[1:0]
B0VAL03
B1VAL03
B1RDY03
B0RDY03
B0BYT03[6:0]
B1BYT03[6:0]
MXPS03[6:0]
BADD03[4:0]
: Not used
Fig. 30 USB related registers
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 32 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
USB Related Registers
The USB related registers are shown below.
b0
b7
USB control register (USBCON) [address 001016]
Bit symbol
WKUP
TRONCON
TRONE
VREFCON
VREFE
USBDIFE
UCLKCON
USBE
At reset
R W
H/W S/W
0 : Returning to BUS idle state by writing “1” first and 0
Remote wakeup bit
– O O
then “0”. (Remote wakeup signal)
1 : K-state output
0 : “L” output mode (valid in TRONE = “1”)
TrON output control bit
0
– O O
1 : “H” output mode (valid in TRONE = “1”)
0 : TrON port output disabled (Hi-Z state)
TrON output enable bit
0
– O O
1 : TrON port output enabled
USB reference voltage control bit 0 : Normal mode (valid in VREFE = “1”)
0
– O O
1 : Low current mode (valid in VREFE = “1”)
USB reference voltage enable bit 0 : USB reference voltage circuit operation disabled
0
– O O
1 : USB reference voltage circuit operation enabled
USB difference input enable bit 0 : Upstream-port difference input circuit operation disabled
0
– O O
1 : Upstream--port difference input circuit operation enabled
0 : External oscillating clock f(XIN)
USB clock select bit
0
– O O
1 : PLL circuit output clock fVCO
USB module operation enable bit 0 : USB module reset
0
– O O
1 : USB module operation enabled
Bit name
Function
–: State remaining
Fig. 31 Structure of USB control register
b0
b7
0
0 0
0 0 0
0
USB function enable register (USBAE) [address 001116]
Bit symbol
Bit name
AD0E
USB function enable bit
b7:b1
Not used
Function
0: USB function address register invalidated
1: USB function address register validated
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 32 Structure of USB function enable register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 33 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b0
b7
USB function address register (USBA0) [address 001216]
0
Bit symbol
Function
Bit name
USBADD0
[6:0]
USB function address bit
b7
Not used
In AD0E = “0”, this value changes after writing.
In AD0E = “1”, this value changes after completion of
SET_ADDRESS control transferring.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
0 O O
–
–
O O
–: State remaining
Fig. 33 Structure of USB function address register
b0
b7
Frame number register Low (FNUML) [address 001416]
Bit symbol
FNUM
[7:0]
Function
Bit name
Frame number low bit
The frame number is updated at SOF reception.
At reset
R W
H/W S/W
InIn- O ✕
definite definite
Fig. 34 Structure of Frame number register Low
b0
b7
0
0 0
0 0
Frame number register High (FNUMH) [address 001516]
Bit symbol
FNUM
[10:8]
b7:b3
Bit name
Function
Frame number high bit
The frame number is updated at SOF reception.
Not used
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
InIn- O ✕
definite definite
–
–
O O
–: State remaining
Fig. 35 Structure of Frame number register High
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 34 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
0
USB interrupt source enable register (USBICON) [address 001616]
Bit symbol
Bit name
b5:b4
USB function/Endpoint 0 interrupt
enable bit
USB function/Endpoint 1 interrupt
enable bit
USB function/Endpoint 2 interrupt
enable bit
USB function/Endpoint 3 interrupt
enable bit
Not used
SUSE
Suspend interrupt enable bit
RSME
Resume interrupt enable bit
EP00E
EP01E
EP02E
EP03E
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Write “0” when writing.
“0” is read when reading.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
0
0
O O
–
–
O O
0
0
O O
0
0
O O
–: State remaining
Fig. 36 Structure of USB interrupt source enable register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 35 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
USB interrupt source register (USBIREQ) [address 001716]
0
Bit symbol
Bit name
EP00
USB function/Endpoint 0
interrupt bit
EP01
USB function/Endpoint 1
interrupt bit
EP02
USB function/Endpoint 2
interrupt bit
EP03
USB function/Endpoint 3
interrupt bit
b5:b4
Not used
SUS
Suspend interrupt bit
RSM
Resume interrupt bit
At reset
R W
H/W S/W
This bit is set to “1” when any one of EP00 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP00 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP01 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP01 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP02 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP02 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP03 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP03 interrupt
source register to “0016”.
Writing to this bit causes no state change.
Write “0” when writing.
–
– O O
“0” is read when reading.
0 : No interrupt request issued
0
0 O O
1 : Interrupt request issued
This bit is set to “1” when detecting 3 ms or more of Jstate, using USB clock (fUSB) at 48 MHz.
“0” can be set by software, but “1” cannot be set.
This bit is set to “1” when the USB bus state changes 0
0 O ✕
from J-state to K-state or SE0 in the resume interrupt
enable bit = “1”. It is also “1” in the condition of internal
clock stopped.
This bit is cleared to “0” by clearing the resume
interrupt enable bit.
Writing to this bit causes no state change.
Function
–: State remaining
Fig.37 Structure of USB interrupt source register
b0
b7
0
0 0
0 0
0
Endpoint index register (USBINDEX) [address 001816]
Bit symbol
Bit name
EPIDX [1:0] Endpoint index bit
b7:b3
Not used
Function
b1 b0
0 0 : Endpoint 0
0 1 : Endpoint 1
1 0 : Endpoint 2
1 1 : Endpoint 3
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 38 Structure of Endpoint index register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 36 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(1) Endpoint 00
b0
b7
0
0
0
0 0
EP00 stage register (EP00STG) [address 001916]
0 0
Bit symbol
Function
Bit name
SETUP00
SETUP packet detection bit
b7:b1
Not used
This bit is set to “1” at reception of SETUP packet.
Writing “0” to this bit clears this bit if the next SETUP
token does not occur.
Writing “1” to this bit causes no state change of the
status flags.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
1
1 O O
–
–
O O
–: State remaining
Fig. 39 Structure of EP00 stage register
b0
b7
0
0
0
0 0
EP00 control register 1 (EP00CON1) [address 001A16]
0
Bit symbol
Function
Bit name
PID00 [1:0]
Response PID bit
b7:b2
Not used
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of control transfer error:
B1 is set to “1” by the hardware.
At reception of SETUP token:
B1 and b0 are cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 40 Structure of EP00 control register 1
b0
b7
0
0
0 0
0 0
0
EP00 control register 2 (EP00CON2) [address 001B16]
Bit symbol
Bit name
BVAL00
Buffer enable bit
b7:b1
Not used
Function
0 : NAK transmission (SIE is disabled to read a buffer.)
1 : Transmitting/receiving data set state (SIE is possible
to read from/write to a buffer.)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 41 Structure of EP00 control register 2
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 37 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
0
0 0
0 0
EP00 control register 3 (EP00CON3) [address 001C16]
0
Bit symbol
CTENDE00 Control transfer completion
enable bit
b7:b1
Function
Bit name
Not used
0 : NAK transmission in the status stage
1 : Control transfer completion enabled (SIE transmits
NULL/ACK.) (valid in PID00 = “012”)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 42 Structure of EP00 control register 3
b7
0 0 0
b0
EP00 interrupt source register (EP00REQ) [address 001D16]
Bit symbol
BRDY00
CTEND00
CTSTS00
BSRDY00
ERR00
b7:b5
Bit name
Function
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 0 control 0: No interrupt request issued
transfer completion interrupt bit 1: Interrupt request issued
This bit is set to “1” when control transfer is completed
(NULL/ACK transmission in the status stage) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 0 status 0: No interrupt request issued
1: Interrupt request issued
stage transition interrupt bit
This bit is set to “1” when transition to status stage
occurs in CTENDE00 = “0” (control transfer completion
disabled) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
<Transition to status stage occurrence factor>
At transfer of control write:
When receiving IN-token in data stage (OUT)
At transfer of control read:
When receiving OUT-token in data stage (IN)
At no data transfer:
Nothing occurs.
USB function/Endpoint 0 SETUP 0: No interrupt request issued
1: Interrupt request issued
buffer ready interrupt bit
This bit is set to “1” when the exclusive buffer for
SETUP is ready state (enabled to be read) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
USB function/Endpoint 0 error
1: Interrupt request issued
interrupt bit
This bit is set to “1” when control transfer error occurs
on USB function/Endpoint 0.
This bit is cleared to “0” by the hardware when
receiving SETUP token.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
Not used
“0” is read when reading.
USB function/Endpoint 0 buffer
ready interrupt bit
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
0
0
O O
0
0
O O
–
–
O O
–: State remaining
Fig. 43 Structure of EP00 interrupt source register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 38 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
0
0
EP00 byte number register (EP00BYT) [address 001E16]
0
Bit symbol
BBYT00
[3:0]
b7:b4
Function
Bit name
Transmit/receive byte number bit OUT : The received byte number is automatically set.
IN : Set the transmitting byte number.
Write 0 when writing.
Not used
0 is read when reading.
At reset
R W
H/W S/W
0
— O O
—
—
O O
—: State remaining
Fig. 44 Structure of EP00 byte number register
b0
b7
0
0 0
EP00 buffer area set register (EP00BUF) [address 0FED16]
Bit symbol
Bit name
BADD00
[4:0]
EP00 beginning address set bit
b7:b5
Not used
Function
Set the beginning address of EP00’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 45 Structure of EP00 buffer area set register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 39 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(2) Endpoint 01
b0
b7
EP01 set register (EP01CFG) [address 001916]
Bit symbol
BSIZ01
[1:0]
DBLB01
SQCL01
ITMD01
DIR01
TYP01
[1:0]
At reset
R W
H/W S/W
Double buffer beginning address set In double buffer mode set the beginning address of 0
– O O
buffer 1 area, using a relative value for the beginning
bit
address of buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
0 : Single buffer mode
Buffer mode select bit
0
– O O
1 : Double buffer mode
0 : Toggle bit clear disabled
Sequence toggle bit clear bit
0
– O O
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Interrupt toggle mode select bit 0 : Normal mode
0
– O O
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0 : OUT (Data is received from the host.)
Transfer direction bit
0
– O O
1 : IN (Data is transmitted to the host.)
b7b6
Transfer type bite
0
– O O
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
Function
Bit name
–: State remaining
Fig. 46 Structure of EP01 set register
b0
b7
0 0 0
0
0
0
EP01 control register 1 (EP01CON1) [address 001A16]
Bit symbol
Bit name
PID01
[1:0]
Response PID bit
b7:b2
Not used
Function
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 47 Structure of EP01 control register 1
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 40 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
0
0 0
0
0
0
EP01 control register 2 (EP01CON2) [address 001B16]
Bit symbol
Bit name
B0VAL01
Buffer 0 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 48 Structure of EP01 control register 2
b0
b7
0 0 0 0
EP01 control register 3 (EP01CON3) [address 001C16]
0 0 0
Bit symbol
Bit name
B1VAL01
Buffer 1 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
–
– O O
Write “0” when writing.
“0” is read when reading.
Function
–: State remaining
Fig. 49 Structure of EP01 control register 3
b0
b7
0
0
0
0
0
EP01 interrupt source register (EP01REQ) [address 001D16]
Bit symbol
B0RDY01
B1RDY01
ERR01
b7:b3
Bit name
USB function/Endpoint 1 buffer 0 0: No interrupt request issued
ready interrupt bit
1: Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 1 buffer 1 0: No interrupt request issued
ready interrupt bit
1: Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 1
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 1 error
0: No interrupt request issued
interrupt bit
1: Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
Not used
Write “0” when writing.
“0” is read when reading.
Fig. 50 Structure of EP01 interrupt source register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Function
page 41 of 112
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
–
–
O O
HARDWARE
38K0 Group
b7
FUNCTIONAL DESCRIPTION
b0
EP01 byte number register 0 (EP01BYT0) [address 001E16]
0
Bit symbol
B0BYT01
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
Single buffer mode : The received byte number is
automatically set.
Double buffer mode : The received byte number of buffer 0
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 51 Structure of EP01 byte number register 0
b7
b0
EP01 byte number register 1 (EP01BYT1) [address 001F16]
0
Bit symbol
B1BYT01
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
Single buffer mode: These bits are invalid.
Double buffer mode : The received byte number of buffer 1
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 52 Structure of EP01 byte number register 1
b7
0
b0
EP01 MAX. packet size register (EP01MAX) [address 0FEC16]
Bit symbol
MXPS01
[6:0]
b7
Bit name
Max. packet size bit
Not used
Function
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 53 Structure of EP01 MAX. packet size register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 42 of 112
HARDWARE
38K0 Group
b0
b7
0 0
FUNCTIONAL DESCRIPTION
0
EP01 buffer area set register (EP01BUF) [address 0FED16]
Bit symbol
Bit name
BADD01
[4:0]
EP01 beginning address set bit
b7:b5
Not used
Function
Set the beginning address of EP01’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 54 Structure of EP01 buffer area set register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 43 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(3) Endpoint 02
b0
b7
EP02 set register (EP02CFG) [address 001916]
Bit symbol
BSIZ02
[1:0]
DBLB02
SQCL02
ITMD02
DIR02
TYP02
[1:0]
At reset
R W
H/W S/W
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1 0
– O O
area, using a relative value for the beginning address of
bit
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
0 : Single buffer mode
Buffer mode select bit
0
– O O
1 : Double buffer mode
0 : Toggle bit clear disabled
Sequence toggle bit clear bit
0
– O O
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Interrupt toggle mode select bit 0 : Normal mode
0
– O O
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0 : OUT (Data is received from the host.)
Transfer direction bit
0
– O O
1 : IN (Data is transmitted to the host.)
b7b6
Transfer type bite
0
– O O
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
Function
Bit name
–: State remaining
Fig. 55 Structure of EP02 set register
b0
b7
0 0
0
0
0 0
EP02 control register 1 (EP02CON1) [address 001A16]
Bit symbol
Bit name
PID02
[1: 0]
Response PID bit
b7:b2
Not used
Function
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 56 Structure of EP02 control register 1
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 44 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
0
0
0 0
0
EP02 control register 2 (EP02CON2) [address 001B16]
0
Bit symbol
Bit name
B0VAL02
Buffer 0 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 57 Structure of EP02 control register 2
b0
b7
0
0
0
0 0
0
0
EP02 control register 3 (EP02CON3) [address 001C16]
Bit symbol
Bit name
B1VAL02
Buffer 1 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 58 Structure of EP02 control register 3
b0
b7
0
0
0
0
0
EP02 interrupt source register (EP02REQ) [address 001D16]
Bit symbol
B0RDY02
B1RDY02
ERR02
b7 to b3
Bit name
USB function/Endpoint 2 buffer 0 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 2 buffer 1 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 2
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 2 error
0 : No interrupt request issued
interrupt bit
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
Not used
Write “0” when writing.
“0” is read when reading.
Fig. 59 Structure of EP02 interrupt source register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Function
page 45 of 112
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
–
–
O O
HARDWARE
38K0 Group
b7
FUNCTIONAL DESCRIPTION
b0
EP02 byte number register 0 (EP02BYT0) [address 001E16]
0
Bit symbol
B0BYT02
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
Single buffer mode: The received byte number is
automatically set.
Double buffer mode : The received byte number of buffer 0
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 60 Structure of EP02 byte number register 0
b7
b0
EP02 byte number register 1 (EP02BYT1) [address 001F16]
0
Bit symbol
B1BYT02
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
Single buffer mode: These bits are invalid.
Double buffer mode : The received byte number of buffer 1
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 61 Structure of EP02 byte number register 1
b7
0
b0
EP02 MAX. packet size register (EP02MAX) [address 0FEC16]
Bit symbol
MXPS02
[6:0]
b7
Bit name
Max. packet size bit
Not used
Function
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 62 Structure of EP02 MAX. packet size register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 46 of 112
HARDWARE
38K0 Group
b0
b7
0 0
FUNCTIONAL DESCRIPTION
0
EP02 buffer area set register (EP02BUF) [address 0FED16]
Bit symbol
Bit name
BADD02
[4:0]
EP02 beginning address set bit
b7:b5
Not used
Function
Set the beginning address of EP02’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 63 Structure of EP02 buffer area set register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 47 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(4) Endpoint 03
b0
b7
EP03 set register (EP03CFG) [address 001916]
Bit symbol
BSIZ03
[1:0]
DBLB03
SQCL03
ITMD03
DIR03
TYP03
[1:0]
At reset
R W
H/W S/W
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1 0
– O O
area, using a relative value for the beginning address of
bit
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
0 : Single buffer mode
Buffer mode select bit
0
– O O
1 : Double buffer mode
0 : Toggle bit clear disabled
Sequence toggle bit clear bit
0
– O O
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Interrupt toggle mode select bit 0 : Normal mode
0
– O O
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0 : OUT (Data is received from the host.)
Transfer direction bit
0
– O O
1 : IN (Data is transmitted to the host.)
b7b6
Transfer type bit
0
– O O
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
Function
Bit name
–: State remaining
Fig. 64 Structure of EP03 set register
b0
b7
0 0 0
0
0
0
EP03 control register 1 (EP03CON1) [address 001A16]
Bit symbol
Bit name
PID03
[1:0]
Response PID bit
b7:b2
Not used
Function
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 65 Structure of EP03 control register 1
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 48 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
0
0
0 0
0
0
EP03 control register 2 (EP03CON2) [address 001B16]
Bit symbol
Bit name
B0VAL03
Buffer 0 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 66 Structure of EP03 control register 2
b0
b7
0 0 0 0
EP03 control register 3 (EP03CON3) [address 001C16]
0 0 0
Bit symbol
Bit name
B1VAL03
Buffer 1 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 67 Structure of EP03 control register 3
b0
b7
0 0 0 0
0
EP03 interrupt source register (EP03REQ) [address 001D16]
Bit symbol
B0RDY03
B1RDY03
ERR03
b7:b3
Bit name
USB function/Endpoint 3 buffer 0 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 3 buffer 1 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 3
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 3 error
0 : No interrupt request issued
interrupt bit
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
Not used
Write “0” when writing.
“0” is read when reading.
Fig. 68 Structure of EP03 interrupt source register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Function
page 49 of 112
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
–
–
O O
HARDWARE
38K0 Group
b7
FUNCTIONAL DESCRIPTION
b0
EP03 byte number register 0 (EP03BYT0) [address 001E16]
0
Bit symbol
B0BYT03
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
Single buffer mode: The received byte number is
automatically set.
Double buffer mode : The received byte number of buffer 0
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 69 Structure of EP03 byte number register 0
b7
b0
EP03 byte number register 1 (EP03BYT1) [address 001F16]
0
Bit symbol
B1BYT03
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
Single buffer mode: These bits are invalid.
Double buffer mode : The received byte number of buffer 1
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 70 Structure of EP03 byte number register 1
b7
0
b0
EP03 MAX. packet size register (EP03MAX) [address 0FEC16]
Bit symbol
MXPS03
[6:0]
b7
Bit name
Max. packet size bit
Not used
Function
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 71 Structure of EP03 MAX. packet size register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 50 of 112
HARDWARE
38K0 Group
b0
b7
0 0
FUNCTIONAL DESCRIPTION
0
EP03 buffer area set register (EP03BUF) [address 0FED16]
Bit symbol
Bit name
BADD03
[4:0]
EP03 beginning address set bit
b7:b5
Not used
Function
Set the beginning address of EP03’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 72 Structure of EP03 buffer area set register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 51 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
EXTERNAL BUS INTERFACE (EXB)
The external bus interface (EXB) controls the data transfer between the external MCU and the 38K0 group’s CPU or its
memory (multichannel RAM). The external bus interface is shown
below.
38K0 group
CPU
Program ROM
Peripheral functions
External MCU
CPU channel
[Interrupt type]
External bus interface
(EXB)
Multichannel RAM
USB
USB bus
(USB host)
Memory channel
[Direct RAM access type]
Fig. 73 External bus interface
●CPU channel
It is a data transfer course by the interrupt processing between the
external MCU and the 38K0 group’s CPU.
●Memory channel
It is a data transfer course by direct RAM access of the memory
channel controller between the external MCU and the 38K0
group’s memory (multichannel RAM)
●Data transfer of memory channel
When the burst mode is selected with the burst bit of the memory
channel operation mode register, data transfer can be carried out
at the highest speed. After the external bus interface detects a rise
of external read signal/write signal and synchronizes it with the internal clock φ, it completes the data transfer between the transmit/
receive buffer and the multichannel RAM in two clocks.
However, the waiting time of two clocks at a maximum is generated to access the multichannel RAM in USB being operating
because the USB has priority to access.
Therefore, it is necessary to set up the access interval which fills
the following timing with the external MCU bus side.
In φ = 8 MHz, data transfer at about 2 Mbytes/second is possible
at a maximum. When there is access simultaneously from the
USB, it is about 1.3 Mbytes/second.
In φ = 6 MHz, data transfer at about 1.5 Mbytes/second is possible
at a maximum. When there is access simultaneously from the
USB, it is about 1 Mbytes/second.
Address
CS, RD, WR,
DMA acknowledge
Access cycle time from externals:
•3 clocks or more of φ + Signal delay time + Data setup
time of external MCU in USB inactive
•5 clocks or more of φ + Signal delay time + Data setup
time of external MCU in USB active
Fig. 74 Data transfer timing of memory channel
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 52 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
EXB Pin Assignment
The external bus interface (EXB) pins are shown bellow.
The 38K0 group can transmit/receive a data to/from an external
MCU, using the following signals:
•Control input signal ................ 4 (ExCS, ExA0, ExRD, ExWR)
•Data input/output pin .............. 8 (DQ0 to DQ7)
•Interrupt output signal ............ 1 (ExINT)
Additionally, the DMA interface signal and the buffer status read
select signal of 38K0 group can be set up per one by the program.
•Control input signal ................ 3 (ExTC, ExDACK, ExRD, ExA1)
•Interrupt output signal ............ 1 (ExDREQ)
38K0 group
External bus interface
(EXB)
External pins
External chip select
External address
External read
External write
External data
External interrupt
8
P34/ExCS [ L ]
P37/ExA0 [address]
P36/ExRD [ L ]
P35/ExWR [ L ]
P10/DQ0/AN0—P17/DQ7/AN7 [data]
P33/ExINT [ L ]
DMA request
Terminal count
DMA acknowledge
P40/ExDREQ/RxD [ L ]
P42/ExTC/SCLK [ L ]
P41/ExDACK/TxD [ L ]
Status read select
P43/ExA1/SRDY [ H ]
: Functions as normal ports
just after reset.
Fig. 75 External bus interface (EXB) pin assignment
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 53 of 112
CPU
Multichannel RAM
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
EXB Block Diagram
The block diagram of external bus interface (EXB) is shown below.
The external bus interface (EXB) consists of:
(1) External I/O interface part
(2) CPU interface part
(3) Internal memory interface part
(4) Transmit/Receive data buffer part
External I/O interface
CPU interface
Configuration
signal
Index register
External I/O
configuration
register
EXB interrupt
source enable register
Cch_WR
External MCU bus
Cch_RD
P34/ExCS
TxB_RDY
CPU channel
controller
Decoder data selector
RxB_RDY
Command decoder
P37/ExA0
P36/ExRD
P35/ExWR
Memory channel
control
Mch_RD
Mch_WR
Mch_TC
P41/ExDACK/TxD
P42/ExTC/SCLK
mRX_enb
mTX_enb
Memory channel
status
Internal memory
interface
Memory channel
operation mode register
P43/ExA1/SRDY
Memory address
Output selector
Memory address
counter
P40/ExDREQ/RxD
End address register
Mch_req
FIFO_stt
Request acknowledge
Memory channel
controller
MRDsel
Memory channel
transmit buffer control
stt_sel
Buf_WR
ExOE
Transmit/Receive data
buffer
Memory read data
P10/DQ0/AN0–
P17/DQ7/AN7
Transmit buffer register
Memory write data
Receive buffer register
: Functions as normal ports just after reset.
Fig. 76 Block diagram of external bus interface (EXB)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 54 of 112
Multichannel RAM
P33/ExINT
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(1) External I/O Interface Part
(2) CPU Interface Part
The external I/O interface part consists of a command decoder
and an output selector. A command decoder generates the following signals to each unit.
The CPU interface part consists of the decoder/data selector of
the CPU channel, the CPU write register and CPU channel controller
●CPU interface part
•CPU channel read (Cch_RD)
•CPU channel write (Cch_WR)
●Decoder/data selector of CPU channel
A write operation to the CPU register is performed by generating a
write signal for each register with an address decode signal and a
write signal.
A read operation from the CPU register is performed by generating an output enable signal of the internal data bus with an module
select signal and a read signal and generating a select signal for
each register with an address decode signal.
●Internal memory interface part
•Memory channel read (Mch_RD)
•Memory channel write (Mch_WR)
•Memory channel terminal count (Mch_TC)
●Transmit/receive data buffer part
•Buffer write (Buf_WR)
●External I/O interface part
•Status selection (stt_sel)
•Output enable (ExOE)
Access to the CPU channel can be controlled only by setup of
external signals.
Access to the memory channel can be controlled by the value of
the external I/O configuration register and the state (mRX_enb,
mTX_enb signals) of the internal memory interface part.
The output selector has the function which selects from the state
of CPU channel (TxB_RDY and RxD_RDY) and the state of
memory channel (Mch_req) as the signal assigned to P3 3 /
ExINT pin and P40/ExDREQ/RxD pin.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 55 of 112
●CPU write register
There are three CPU write registers as follows:
•EXB interrupt source enable register
•Index register
•External I/O configuration register
The EXB interrupt source register is a read-only register.
A status signal of the CPU channel controller and a status signal
of the memory channel controller in the internal memory interface
part are generated.
●CPU channel controller
The CPU channel controller generates the following signals, using
bits 0 and 1 (RXB_ENB, TXB_ENB) of EXB interrupt source enable register.
•Memory channel transmitting buffer control signal (MRD_sel),
generated in the internal memory interface part
•CPU channel command signal (Cch_RD, Cch_WR), generated
in the external I/O interface part
•Signals RxB_RDY/RxB_full and TxB_RDY/TxB_empty, generated with read/write signals from the CPU channel
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(3) Internal Memory Interface Part
(5) External Pin
The internal memory interface part consists of the CPU register
and the memory channel controller.
The external bus interface has the following pins to connect with
an external MCU bus.
•Chip select ........................... P34/ExCS
•Address ................................ P37/ExA0
•Data ...................................... P10/DQ0/AN0 to P17/DQ7/AN7
•Read .................................... P36/ExRD
•Write ..................................... P35/ExWR
•Interrupt request .................. P33/ExINT
●CPU register
The CPU register consists of the follows:
•Memory channel operation mode register
•Memory address counter
•End address register
The CPU can set the beginning address into the memory address
counter when the memory channel operation enable bit
(MC_ENB) of EXB interrupt source enable register is “0”. When
this bit is “1”, the write operation from the CPU is invalid and each
access from the external bus causes count-up operation.
●Memory channel controller
The CPU register consists of the follows:
•Main sequencer
•Internal memory request signal generating circuit
•External memory channel request signal generating circuit
•Address end detection circuit
•Terminal end input processing circuit
(4) Transmit/Receive Data Buffer Part
The transmit/receive data buffer part consists of the 8-bit transmit
buffer register (TXBUF) and the 8-bit receive buffer register
(RXBUF).
Both CPU channel and memory channel use the same transmit
buffer register/receive buffer register to transfer a data to an external MCU bus.
It also has the following pins to connect with an external DMAC.
Each pin can be programmed for an ordinary port function or a
DMA interface pin function.
•DMA request ........................ P40/ExDREQ/RxD
•DMA acknowledgment ......... P41/ExDACK/TxD
•Terminal count ..................... P42/ExTC/SCLK
It also has the status read select pin (P43/ExA1/SRDY pin) to confirm a ready status of the data buffer from an external MCU bus
This pin functions as a port just after reset. The status read select
function can be set by a program.
•Status read select ................ P43/ExA1/SRDY
●CPU channel: Communication with 38K0 group CPU
When a read/write operation is performed from an external MCU
bus in address signal ExA0 = “H”, the interrupt is generated and
the 38K0 group CPU can confirm its access. The 38K0 group CPU
judges the interrupt source and it starts a data transmission/reception with an external MCU bus.
●Memory channel: Communication with 38K0 group memory
multichannel RAM
When a read/write operation is performed from an external MCU
bus in address signal ExA0 = “L”, access to the multichannel RAM
is performed. Then an address of the multichannel RAM is made
by the external bus interface and it is increased at each access
completion. Consequently, FIFO access is performed.
Even if a read/write operation is performed in DACK = “L” instead
of ExCS = “L” and ExA0 = “L”, FIFO access to the multichannel
RAM is performed.
The beginning address and the end address must be set by the
CPU in advance.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 56 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
●P33/ExINT pin
Any one of the following signals for this pin can be selected:
•TxB_RDY (transmit buffer ready) output
•RxB_RDY (receive buffer ready) output
•Mch_req (memory channel request) output
Either TxB_RDY or RxB_RDY is normally selected. The memory
channel request is for an access request signal to the memory
channel.
In a small system, a data transfer processing to the internal
memory is performed in the interrupt routine. According to that
situation, the 38K0 group has the function automatically to switch
an interrupt factor attached on the interrupt pin by program.
●P40/ExDREQ/RxD pin
This pin is a port at the initial state. Which signal can be set by
program.
•RxB_RDY (receive buffer ready) output
•Mch_req (memory channel request) output
Mch_req of DMAC is normally selected. The output method of the
memory channel request signal depends on the burst bit (BURST)
of memory channel operation mode register. When the burst bit is
“0”, this signal is periodically output at each 1-byte transfer. (See
Figures 94 and 97.)
When the burst bit is “1”, this signal is continuously output while
the memory address counter is counting from the beginning address to the end address (See Figures 95 and 98.)
●P41/ExDACK/TxD pin
This pin is a port at the initial state. The DMA acknowledge signal
can be set by program.
The DMA acknowledge signal DACK = “L” is the same state as
that of CS = “L” and A0 = “L”. Access to multichannel RAM is
started by a rise of read signal or write signal which is set during
this term.
Note: If the DMA acknowledge signal and the chip select signal
are simultaneously active (DACK = “L” and CS = “L”), also
set the address signal A0 to “L”. If A0 is “H”, the memory
channel and the CPU channel are activated simultaneously
and it might cause some error.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 57 of 112
●P42/ExTC/SCLK pin
This pin is a port at the initial state. The terminal count signal can
be set by program.
If the terminal count signal is set at one bus cycle while a memory
channel operation write is being performed, the 38K0 group confirms that its bus cycle is the write cycle of the last data and sets
the memory channel status bits to “112”, and the interrupt is generated and the memory channel operation ends even if the memory
address counter has not reached the end address.
The CPU can obtain the last address where the data is written by
reading out the value of memory address counter. (See Figure
96.)
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
EXB Register List
The EXB register list is shown below.
Address
Register Name
EXB SFR
SYMBOL
003016
003116
EXB interrupt source enable register
EXB interrupt source register
EXBICON
EXBIREQ
003316
003416
003516
EXB index register
Register window 1 (low)
Register window 2 (high)
EXBINDEX
EXBREG1
EXBREG2
bit7
bit6
bit5
bit4
bit2
bit3
MC_ENB
MC_STS[1:0]
0
0
0
0
bit1
bit0
TXB_ENB
TXB_EMPTY
RXB_EMB
RXB_FULL
INDEX[2:0]
0
LOW_WIN[7:0]
HIGH_WIN[7:0]
: Not used
0 : “0” fixed
Fig. 77 EXB related registers (1)
•EXB interrupt source enable register
This register enables/disables access from an external bus and an
internal interrupt.
•EXB index register/Register windows 1, 2
The accessible register is switched by treating addresses 003416
and 003516 as a register window depending on the value of EXB
index register at address 003316.
•EXB interrupt source register
This register indicates the state of CPU channel’s transmit/receive
buffer register and the memory channel. The same value can be
read out from the external MCU bus by using the buffer status
read select signal (A1 pin = “H”).
Index
0016
low
high
low
Register Name
SYMBOL
External I/O configuration register
high
0116
low
Transmit/Receive
buffer register
low
low
low
bit4
bit3
EXBCFGL
A1_CTR
EXBCFGH
TC_CTR
bit2
bit1
INT_CTR[2:0]
DAK_CTR[1:0]
bit0
EXB_CTR
DRQ_CTR[1:0]
At CPU read : RXBUF[7:0]
At CPU write : TXBUF[7:0]
BURST
Memory channel ope- MCHMOD
ration mode register
MC_DIR[1:0]
—
Memory address
counter
high
0416
bit5
—
high
0316
bit6
RXBUF/TXBUF
high
0216
EXB SFR
bit7
MEMADL
MEMADH
IM_A[7:0]
0
0
0
0
high
ENDADH
IM_A[10:8]
0
END_A[10:8]
END_A[7:0]
ENDADL
End address
register
0
0
0
0
0
: Not used
0 : “0” fixed
Fig. 78 EXB related registers (2)
•External I/O configuration register
This register selects the function of each pin.
•Transmit/Receive buffer register
This register consists of the receive buffer register (RXBUF) and
the transmit buffer register (TXBUF)
•Memory channel operation mode register
This register sets the operation mode of the memory channel.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 58 of 112
•Memory address counter
This is a counter to set the beginning address which FIFO accesses. This register is increased by access from the external
MCU bus.
•End address register
This register is to set the end address which FIFO accesses.
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
EXB Related Registers
The EXB related registers are shown below.
b0
b7
0 0
0
0
EXB interrupt source enable register (EXBICON) [address 003016]
(Note)
0
Bit symbol
RXB_ENB
TXB_ENB
MC_ENB
b7:b3
Bit name
Function
CPU channel receive enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Receive buffer full interrupt enabled)
CPU channel transmit enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Transmit buffer empty interrupt enabled)
0 : Operation disabled (Memory channel operation end
Memory channel operation
interrupt disabled)
enable bit
1 : Operation enabled (Memory channel operation end
interrupt disabled)
Write “0” when writing.
Not used
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
0
–
O O
–
–
O O
–: State remaining
Note: Do not set each bit simultaneously.
Fig. 79 Structure of EXB interrupt source enable register
b0
b7
0
0
0
0
EXB interrupt source register (EXBIREQ) [address 003116] (Note 1)
Bit symbol
Bit name
RXB_FULL
Receive buffer full bit
TXB_EMPTY Transmit buffer empty bit
MC_STS
[1:0]
(Note 2)
Memory channel status bits
b7:b4
Not used
Function
0 : Receive buffer empty
1 : Receive buffer full
0 : Transmit buffer full
1 : Transmit buffer empty
b3b2
0 0 : Memory channel operation stopped
0 1 : Memory channel being operating;
No external access
1 0 : Memory channel being operating;
External accessing
1 1 : Memory channel operation end; Memory
channel operation end interrupt generated
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
0 O –
(Note 3)
0
0
O –
(Note 4)
0
0
O –
–
–
O O
–: State remaining
Notes 1: When the the ExA1 pin control bit of external I/O configuration register is “1”, the external MCU bus can read this
register contents by setting the ExA1 pin to “H”.
2: The memory channel status bits indicate the status of memory channel. In MC_ENB = “0” these bits are always
“002”. When the memory channel operation ends, these bits are set to “112” and the memory channel operation
end interrupt is generated.
These bits can be read out during operation, so that it will show that whether the external MCU bus is accessing
or not.
3: This bit is cleared to “0” when reading the transmit/receive buffer register in the CPU channel receive enable bit =
“1” or when the CPU channel receive enable bit is “0”.
4: This bit is cleared to “0” when writing to the transmit/receive buffer register in the CPU channel transmit enable bit
= “1” or when the CPU channel transmit enable bit is “0”.
Fig. 80 Structure of EXB interrupt source register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 59 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
0
0
EXB index register (EXBINDEX) [address 003316]
0 0
Bit symbol
Bit name
INDEX
[2:0]
Index bits
b7:b3
Not used
At reset
R W
H/W S/W
– O O
The accessible register, using the register window, 0
depends on these index bits contents as follows:
b2b1b0
0 0 0 : External I/O configuration register
0 0 1 : Transmit/Receive buffer register
0 1 0 : Memory channel operation mode register
0 1 1 : Memory address counter
1 0 0 : End address register
1 0 1 : Do not set.
1 1 0 : Do not set.
1 1 1 : Do not set.
–
– O O
Write “0” when writing.
“0” is read when reading.
Function
–: State remaining
Fig. 81 Structure of EXB index register
b7
b0
Register window 1 (EXBREG1) [address 003416]
Bit symbol
LOW_WIN
[7:0]
Bit name
–
At reset
R W
H/W S/W
In- O O
The accessible register, using this register window, Independs on the EXB index register contents as definite definite
follows:
Index value
“0016”
: External I/O configuration register
“0116”
: Transmit/Receive buffer register
“0216”
: Memory channel operation mode register
“0316”
: Memory address counter
“0416”
: End address register
Function
Fig. 82 Structure of Register window 1
b7
b0
Register window 2 (EXBREG2) [address 003516]
Bit symbol
HIGH_WIN
[7:0]
Bit name
–
Fig. 83 Structure of Register window 2
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 60 of 112
At reset
R W
H/W S/W
In- O O
The accessible register, using this register window, Independs on the EXB index register contents as definite definite
follows:
Index value
: External I/O configuration register
“0016”
“0116”
: Transmit/Receive buffer register
: Memory channel operation mode register
“0216”
: Memory address counter
“0316”
: End address register
“0416”
Function
HARDWARE
38K0 Group
b0
b7
0
FUNCTIONAL DESCRIPTION
0
Index = 0016 : External I/O configuration register (EXBCFGL) [address 003416]
0
Bit symbol
EXB_CTR
INT_CTR
[2:0]
Function
Bit name
EXB pin control bit
(Pins P10 to P17, P30 to P34)
P33/ExINT pin control bit
A1_CTR
P43/ExA1 pin control bit
b7:b5
Not used
0 : Port
1 : EXB function pin
Selects a signal of P33/ExINT pin.
ON/OFF is programmed by each bit. An output logical
sum of P33/ExINT pins set for ON are performed and it
is output as an “L” active signal.
b3b2b1
0 0 1 : RxB_RDY (RxBuf ready) output
0 1 0 : TxB_RDY (TxBuf ready) output
1 0 0 : Mch_req (Memory channel request) output
Others : Do not set.
0 : Port
1 : A1 input (used to read status)
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
0
–
O O
–
–
O O
–: State remaining
Fig. 84 Index00[low]; Structure of External I/O configuration register
b0
b7
0
0
0
Index = 0016 : External I/O configuration register (EXBCFGH) [address 003516]
Bit symbol
Function
Bit name
DRQ_CTR
[1:0]
P40/ExDREQ/RxD pin control
bit
DAK_CTR
[1:0]
P41/ExDACK/TxD pin control
bit
TC_CTR
P42/ExTC/SCLK pin control bit
b7:b5
Not used
b1b0
0 0 : Port
0 1 : Do not set.
1 0 : ExDREQ function; RxB_RDY (RxBuf ready) output
1 1 : ExDREQ function; Mch_req (Memory channel
request) output
Specifies P41/ExDACK/TxD pin function.
Selects which mode; requiring read or write signal, or
not requiring it for use of DMA acknowledge function.
b3b2
0 0 : Port
0 1 : Do not set.
1 0 : ExDACK function; DMA acknowledge input
(Mode for read and write signals used together)
1 1 :ExDACK function; DMA acknowledge input
(Mode for read and write signals not required)
0 : Port
1 : ExTC (terminal count) input
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
0
–
O O
–
–
O O
–: State remaining
Fig. 85 Index00[high]; Structure of External I/O configuration register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 61 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b0
b7
Index =0116 : Transmit/Receive buffer register (RXBUF/TXBUF) [address 003416]
Bit symbol
RXBUF/
TXBUF
Bit name
–
At reset
R W
H/W S/W
– O O
The data received from an external bus is written here 0
at the rise timing of external write signal.
The data transmitted to an external bus is written here
at the timing of internal CPU write or memory write.
Function
The receive buffer register (RXBUF) contents can be read out by reading to this address with the CPU. The data which the
CPU has written to this address is stored in the transmit buffer register (TXBUF).
However, do not perform write operation with the CPU to this address if the memory channel direction control bits of
memory channel operation mode register is “102” (transmit mode) and the memory channel status bits of EXB interrupt
source register are “012” or “102” (memory channel being operating).
Fig. 86 Index01[low]; Structure of Transmit/Receive buffer register
b0
b7
0
0
0
0
Index =0216 : Memory channel operation mode register (MCHMOD) [address 003416]
0
Bit symbol
Function
Bit name
MC_DIR
[1:0]
Memory channel direction
control bit
BURST
Burst bit
b7:b3
Not used
b1b0
0 0 : Operation disabled
0 1 : Receive mode
1 0 : Transmit mode
1 1 : Do not set.
0 : Cycle mode (each byte transfer according to
assertion or negation)
1 : Burst mode (continuous transfer till the terminal
count)
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
–
–
O O
–: State remaining
Fig. 87 Index02[low]; Structure of Memory channel operation mode register
b7
b0
Index = 0316 : Memory address counter (MEMADL) [address 003416]
Bit symbol
IM_A
[7:0]
Bit name
–
Fig. 88 Index03[low]; Structure of Memory address counter
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 62 of 112
At reset
R W
H/W S/W
O
O
Register to set the low-order address of memory 0
–
channel operation beginning.
This contents are increased each time one memory
access ends.
Function
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b0
b7
0
0
0
0
Index = 0316 : Memory address counter (MEMADH) [address 003516]
0
Bit symbol
Bit name
IM_A
[10:8]
–
b7:b3
Not used
At reset
R W
H/W S/W
Register to set the high-order address of memory 0
– O O
channel operation start.
This contents are increased each time one memory
access ends.
Write “0” when writing.
–
– O O
“0” is read when reading.
Function
–: State remaining
Fig. 89 Index03[high]; Structure of Memory address counter
b0
b7
Index = 0416 : End address register (ENDADL) [address 003416]
Bit symbol
END_A
[7:0]
Bit name
–
At reset
R W
H/W S/W
Register to set the low-order address of memory 0
– O O
channel operation end.
Function
–: State remaining
Fig. 90 Index04[low]; Structure of End address register
b0
b7
0
0
0
0
0
Index = 0416 : End address register (ENDADH) [address 003516]
Bit symbol
END_A
[10:8]
b7:b3
Bit name
–
Not used
At reset
R W
H/W S/W
Register to set the high-order address of memory 0
– O O
channel operation end.
Write “0” when writing.
–
– O O
“0” is read when reading.
Function
–: State remaining
Fig. 91 Index04[high]; Structure of End address register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 63 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
EXB Operation Timing Diagram
(1) CPU Channel Receiving Operation
CPU channel receiving operation is shown bellow.
➀
➁
➂
Address ExA0
A0 = “1”
A0 = “1”
Chip select ExCS
CS = “0”
CS = “0”
Read ExRD
➁
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
Interrupt request ExINT
[RxB_RDY]
RxB_RDY
RxB_RDY
Receive buffer full bit RXB_FULL
Receive buffer RXBUF
#0
#1
Transmit buffer TXBUF
CPU channel receive enable bit
RXB_ENB
➀
Receive buffer read
➂
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P33/ExINT pin control) = 0012 (RxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
RXB_ENB (CPU channel receive enable) = “1” (Receive buffer full interrupt enabled)
➀ Writing the command for enabling operation makes RXB_RDY assertion and the P33/ExINT pin goes to “L”.
If the CPU channel receive enable bit (RXB_ENB) is “0”, both the receive buffer full bit (RXB_FULL) and the receive buffer ready signal (RxB_RDY) to an
external are inactive.
➁ When a write operation is performed from an external MCU bus in the condition of ExCS = “L” and WxA0 = “H”, it will result in as follows:
• The data is written into the receive buffer (RXBUF)
• Negation of the receive buffer ready signal (RxB_RDY) to an external is made
• The RXB_FULL interrupt is generated.
➂ When the CPU reads out the receive buffer (RXBUF) with an interrupt processing program, the receive buffer full bit (RXB_FULL) is cleared to “0”.
Fig. 92 CPU channel receiving operation
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 64 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(2) CPU Channel Transmitting Operation
CPU channel transmitting operation is shown bellow.
➀
➁
➂
➁’
Address ExA0
A0 = “1”
A0 = “1”
Chip select ExCS
CS = “0”
CS = “0”
➂
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
Interrupt request ExINT
[TxB_RDY]
TxB_RDY
TxB_RDY
Transmit buffer empty bit
TXB_EMPTY
Receive buffer RXBUF
Transmit buffer TXBUF
CPU channel transmit enable bit
TXB_ENB
#0
#1
➀
Transmit data write
➁’
➁
<Initial setting>
External I/O configuration register
INT_CTR[3:1] (P33/ExINT pin control) = 0102 (TxB_RDY interrupt)
<Operation start>
EXB interrupt source enable register
TXB_ENB (CPU channel transmit enable) = “1” (Transmit buffer empty interrupt enabled)
➀ Writing the command for enabling operation generates TXB_EMPTY interrupt.
If the CPU channel transmit enable bit (TXB_ENB) is “0”, both the transmit buffer empty bit (TXB_EMPTY) and the transmit buffer ready signal (TxB_RDY) to
an external are inactive.
➁ When the CPU writes the data into the transmit buffer (TXBUF) with an interrupt processing program, the transmit buffer empty bit (TXB_EMPTY) is cleared
to “0” and assertion of the transmit buffer ready signal (TxB_RDY) to an external is made.
➂ When a read operation is performed from an external MCU bus in the condition of ExCS = “L” and ExA0 = “H”, it will result in as follows:
• The contents of the transmit buffer (TXBUF) is read out
• The transmit buffer empty bit (TXB_EMPTY) is set to “1”
• Negation of the transmit buffer ready signal (TxB_RDY) to an external is made.
Fig. 93 CPU channel tranmitting operation
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 65 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(3) Memory Channel Receiving Operation (1)Cycle Mode
Memory channel receiving operation (1) is shown bellow.
➀
➁
➂
➃
➁’
Address ExA0
A0 = “0”
A0 = “0”
Chip select ExCS
CS = “0”
CS = “0”
➂’
➄
DMA acknowledge
ExDACK
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
mWR
➔
detection
mWR
➔
DMA request
ExDREQ
detection
Mch_req
Mch_req
Receive buffer RXBUF
#0
#1
➀
Operation enabled
Main sequencer
0
1
2
3
5
Memory channel operation
end interrupt
Internal memory access
req
Memory address
req
010016
010116
010216
Counter end
Acknowledgment of
internal memory access
ack
ack
➃
➄
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “0” (Cycle mode)
Memory address counter
(Example) 010016
End address register
(Example) 010116
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ In the memory channel receive mode when the command for enabling operation is written, operation starts (main sequencer starts) and assertion of the
memory channel request which synchronized with a rise of φ is made.
➁ When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExWR is detected in the condition of ExDACK = “L”, negation of the
memory channel request which synchronized with a rise of φ is made.
➂ When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal
memory within two clocks at a minimum.
➃ The memory address counter is increased simultaneously at write completion and assertion of the next memory channel request is made.
➄ When the write operation to the end address has been completed, the memory address counter is increased, but assertion of the next memory channel
request is not made and the memory channel operation end interrupt is generated.
Fig. 94 Memory channel receiving operation (1)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 66 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(4) Memory Channel Receiving Operation (2)Burst Mode
Memory channel receiving operation (2) is shown bellow.
➀
➁
➂
➁’
➃
➄
Address ExA0
A0 = “x”
A0 = “x”
A0 = “x”
Chip select ExCS
CS = “1”
CS = “1”
CS = “1”
Dack = “0”
Dack = “0”
Dack = “0”
DMA acknowledge
ExDACK
Read ExRD
➁’
➁
Write ExWR
Data DQ0 to DQ7
#0
#1
#2
Internal clock φ
mWR
➔
detection
mWR
➔
DMA request
ExDREQ
detection
Mch_req
Receive buffer RXBUF
#0
#1
#2
Operation enabled
➀
Main sequencer
0
1
2
3
5
Memory channel operation
end interrupt
Internal memory access
req
Memory address
req
010016
req
010116
010216
010316
Counter end
Burst end
Acknowledgment of
internal memory access
ack
ack
➂
ack
➃
➄
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
(Example) 010016
End address register
(Example) 010216
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ In the memory channel receive mode when the command for enabling operation is written, assertion of the memory channel request which synchronized
with a rise of φ is made.
➁ When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal
memory within two clocks at a minimum.
➂ The memory address counter is increased simultaneously at the former data write completion.
➃
When the memory address counter reaches the end address, the detection circuit of external write signal (ExWR) operation is enabled and negation of the
memory channel request which synchronized with the following φ is made.
➄ When
the write operation to the end address has been completed, the memory address counter is increased and the memory channel operation end
interrupt is generated.
Fig. 95 Memory channel receiving operation (2)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 67 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(5) Memory Channel Receiving Operation (3)Burst Mode (Terminal Count)
Memory channel receiving operation (3) is shown bellow.
➀’
Address ExA0
A0 = “x”
A0 = “x”
Chip select ExCS
CS = “1”
CS = “1”
Dack = “0”
Dack = “0”
DMA acknowledge
ExDACK
➁’
➀
➀
➀’
Terminal count ExTC
➁
TC
Write ExWR
Data DQ0 to DQ7
#0
#1
Internal clock φ
mWR
➔
detection
mWR
➔
DMA request
ExDREQ
detection
Mch_req
mTC
➔
Receive buffer RxBuf
#0
#1
detection
TC synchronizing
➁’
TC end
➁
➁’
Operation enabled
Main sequencer
0
1
2
3
(5)
5
Memory channel operation
end interrupt
➁’
req
Internal memory access
Memory address
010016
010116
➁’
010216
Counter end
Burst end
Acknowledgment of
internal memory access
ack
ack
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
(Example) 010016
End address register
(Example) 010716
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ When a rise of TC is detected, negation of the memory channel request which synchronized with a rise of φ is made.
➁ When the write operation to the end address has been completed, the memory channel operation end interrupt is generated.
Fig. 96 Memory channel receiving operation (3)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 68 of 112
➁
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(6) Memory Channel Transmitting Operation
(1)-Cycle Mode
Memory channel transmitting operation (1) is shown bellow.
➀
➁
➂
➃
➄
➂’
➅
Address ExA0
A0 = “x”
A0 = “x”
Chip select ExCS
CS = “1”
CS = “1”
DMA acknowledge
ExDACK
Dack = “0”
➂
Dack = “0”
➃
➂’
➅
Read ExRD
Write ExWR
#0
Data DQ0 to DQ7
#1
Internal clock φ
mRD
➔
detection
mRD
➔
DMA request
ExDREQ
detection
Mch_req
Mch_req
Transmission completed
Transmit buffer TXBUF
#0
➀
#1
Operation enabled
Main sequencer
0
1
2
3
4
5
Memory channel operation
end interrupt
req
Internal memory access
Memory address
req
010116
010016
010216
Counter end
Acknowledgment of
internal memory access
ack
ack
➄
➁
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)
Burst (burst) = “0” (Cycle mode)
Memory address counter
(Example) 010016
End address register
(Example) 010116
<Operation start command>
EXB interrupt source enable register
➀
MC_ENB (Memory channel operation enable) = “1” (Operation start)
In the memory channel transmit mode when the command for enabling operation is written, operation starts (main sequencer starts) and an internal
memory access sequence which synchronized with a rise of φ is activated.
➁ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
➂ When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExRD is detected in the condition of ExDACK = “L”, negation of the
memory channel request which synchronized with a rise of φ is made.
➃ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.
➄ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
When the read operation from the end address has been completed, the transition to the status to wait the memory channel operation end occurs.
➅ When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
Fig. 97 Memory channel tranmitting operation (1)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 69 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(7) Memory Channel Transmitting Operation
(2)-Burst Mode
Memory channel transmitting operation (2) is shown bellow.
➀
➁
➂
➃
➂’
➄
➅
Address ExA0
A0 = “x”
A0 = “x”
A0 = “x”
Chip select ExCS
CS = “1”
CS = “1”
CS = “1”
Dack = “0”
DMA acknowledge
ExDACK
Dack = “0”
➂
Dack = “0”
➅
➂’
Read ExRD
Write ExWR
Data DQ0 to DQ7
#0
#1
#2
Internal clock φ
mRD
➔
detection
mRD
➔
DMA request
ExDREQ
detection
Mch_req
Transmission completed
Transmit buffer TXBUF
#0
#1
#2
Operation enabled
➀
Main sequencer
0
1
2
3
4
Memory channel operation
end interrupt
Internal memory access
req
Memory address
req
010016
req
010116
010216
010316
Counter end
Burst end
Acknowledgment of
internal memory access
ack
ack
➁
ack
➃
➄
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
(Example) 010016
End address register
(Example) 010216
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
➀ In the memory channel transmit mode when the command for enabling operation is written, an internal memory access sequence which synchronized with
a rise of φ is activated.
➁ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
➂ When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.
➃ A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased.
➄ When the read operation from the end address has been completed, the detection circuit of external read signal (ExRD) operation is enabled and negation
of the memory channel request which synchronized with the following φ is made.
➅ When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
Fig. 98 Memory channel tranmitting operation (2)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 70 of 112
5
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
MULTICHANNEL RAM
The 38K0 group has the built-in multichannel RAM including the
small logic circuit (RAM I/F) instead of ordinary RAM.
The multichannel RAM has the USB channel and the EXB channel
in addition to the CPU channel.
The multichannel RAM controls access from CPU, USB and EXB,
synchronizing control with φ. The USB transfer rate is about 1.5
Mbytes/second. Access to the multichannel RAM is performed at
every about 5.3 clocks in φ = 8 MHz, or at every about 4 clocks in
φ = 6 MHz. The USB’s access has priority to the EXB’s.
The one wait function (ONW function) of 38000 series CPU is
used internally to control access with the CPU. When receiving an
access request from the USB or the EXB, the multichannel RAM
outputs ONW signal to wait the CPU for one clock, and access of
the USB or the EXB is performed.
If the multichannel RAM is outputting ONW signal while the CPU
is in the state of reading/writing for the RAM area, the CPU read
cycle or write cycle is extended by 1 period of φ.
No wait
No wait
No wait
ONW = “H”
Except RAM
No RD/WR
φ
CPU AD
CPU bus cycle
RAM area
Except RAM
RAM area
CPU
USB
CPU
RD/WR
USB REQ
Multichannel RAM
EXB REQ
ONW
RAM access right
RAM bus cycle
RAM RD/WR
Fig. 99 Multichannel RAM timing diagram (no wait)
One wait
CPU accessing RAM at the latter part
One wait
Prohibiting continuous access of
USB/EXB
Prior CPU
Prior CPU
One wait
USB having priority of USB/EXB
simultaneous access
Prior USB
One wait
2-cycle wait (max.) for EXB
Prior CPU
φ
CPU bus cycle
RAM area
CPU AD
RAM area
RAM area
RAM area
RD/WR
USB REQ
Multichannel RAM
EXB REQ
ONW
RAM access right
EXB
CPU
RAM bus cycle
RAM RD/WR
Fig. 100 Multichannel RAM timing diagram (one wait)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 71 of 112
USB
CPU
USB
CPU
EXB
CPU
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Multichannel RAM Operation Example
The multichannel RAM operation example is shown below.
This example shows the case that an external MCU uses the
38K0 group as a peripheral LSI (USB controller).
The following explains that the external MCU reads out the data
which is received via the USB.
➀ The data which is received via the USB is written into the multichannel RAM.
➁ Receive completion is propagated to the CPU.
➂ The external bus interface is activated owing to the CPU.
➃ (1) The external bus interface sets the data which is read from
the multichannel RAM into the internal data buffer.
(2) The external MCU reads out the data bus buffer of the external bus interface.
(3) The above operation is repeated by the number of the received bytes. After that, the data transfer is completed.
Program ROM
External MCU
CPU
➂ Activating
Peripheral functions
➁ Notice of receive completion
External MCU bus
External bus interface
➃ FIFO read of received data
by External bus interface
Fig. 101 Multichannel RAM operation example
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 72 of 112
Multichannel RAM
USB
➀ FIFO write of received data
by USB
USB bus
(USB host)
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
A/D CONVERTER
Comparator and Control Circuit
The functional blocks of the A/D converter are described below.
The comparator and control circuit compares an analog input voltage with the comparison voltage, and then stores the result in the
AD conversion registers 1, 2. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit
and the AD interrupt request bit to “1”.
Note that because the comparator consists of a capacitor coupling, set f(system clock) to 500 kHz or more during an A/D
conversion.
[AD Conversion Register 1, 2 (AD1, AD2)]
003716, 003816
The AD conversion register is a read-only register that stores the
result of an A/D conversion. When reading this register during an
A/D conversion, the previous conversion result is read.
Bit 7 of the AD conversion register 2 must be set to “0”.Not only
10-bit reading but also only high-order 8-bit reading of conversion
result can be performed by selecting the reading procedure of the
AD conversion registers 1, 2 after A/D conversion is completed (in
Figure 103).
The 8-bit reading inclined to MSB is performed when reading the
AD converter register 1 after A/D conversion is started or reset;
and when the AD converter register 1 is read after reading the AD
converter register 2, the 8-bit reading inclined to LSB is performed.
b7
b0
AD control register
(ADCON : address 003616)
Analog input pin selection bits
0 0 0 : P10/DQ0/AN0
0 0 1 : P11/DQ1/AN1
0 1 0 : P12/DQ2/AN2
0 1 1 : P13/DQ3/AN3
1 0 0 : P14/DQ4/AN4
1 0 1 : P15/DQ5/AN5
1 1 0 : P16/DQ6/AN6
1 1 1 : P17/DQ7/AN7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (indefinite at read)
(These bits are write disabled bits.)
[AD Control Register (ADCON)] 003616
The AD control register controls the A/D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A/D conversion. The value of this bit remains at “0”
during an A/D conversion, and changes to “1” when an A/D conversion ends. Writing “0” to this bit starts the A/D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
VREF and AVSS into 1024, and that outputs the comparison voltage.
The A/D converter successively compares the comparison voltage
Vref in each mode, dividing the VREF voltage (see below), with the
input voltage.
• 10-bit reading
VREF
Vref = 1024 ✕ n (n = 0–1023)
Fig. 102 Structure of AD control register
10-bit reading
(Read address 003816 before 003716)
b7
(address 003816)
0
b0
b9 b8
b7
(address 003716)
b0
b7 b6 b5 b4 b3 b2 b1 b0
• 8-bit reading
Vref = VREF ✕ n (n = 0–255)
256
Note : Bits 2 to 7 of address 003816 become “0”
at reading.
8-bit reading
Channel Selector
(Read only address 003716)
The channel selector selects one of the input ports P17/AN7–P10/
AN0.
b7
(address 003716)
b0
b9 b8 b7 b6 b5 b4 b3 b2
Fig. 103 10-bit A/D mode reading
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 73 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Data bus
AD control register
(address 003616)
b7
b0
3
Channel selector
P10/DQ0/AN0
P11/DQ1/AN1
P12/DQ2/AN2
P13/DQ3/AN3
P14/DQ4/AN4
P15/DQ5/AN5
P16/DQ6/AN6
P17/DQ7/AN7
Comparator
AD conversion register 2
(address 003816)
AD conversion register 1
(address 003716)
10
Resistor ladder
VREF
Fig. 104 A/D converter block diagram
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
A/D interrupt request
A/D control circuit
page 74 of 112
VSS
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
WATCHDOG TIMER
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916) permits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at system clock 8 MHz frequency.
When this bit is set to “1”, the count source becomes the system
clock divided by 16. The detection time in this case is set to 512
µs at system clock 8 MHz frequency. This bit is cleared to “0” after
resetting.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control register (address 003916) after resetting, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 0039 16 ) may be
started before an underflow. When the watchdog timer control register (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit (bit 6), and
watchdog timer H count source selection bit (bit 7) are read.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916) permits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
Once the STP instruction is executed, an internal reset occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L is set to “FF16.”
Data bus
“FF16” is set when
watchdog timer
control register is
written to.
Watchdog timer L (8)
System clock
1/16
“FF16” is set when
watchdog timer
control register is
written to.
“0”
“1”
Watchdog timer H (8)
Watchdog timer H count
source selection bit
STP instruction disable bit
STP instruction
Reset circuit
RESET
Internal reset
Fig. 105 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 003916)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: System clock/16
Fig. 106 Structure of Watchdog timer control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 75 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
Poweron
To reset the microcomputer, RESET pin should be held at an “L”
level for 16 cycles or more of XIN. Then the RESET pin is returned
to an “H” level (the power source voltage should be between 3.0 V
and 5.25 V for L version, and the oscillation should be stable), reset is released. After the reset is completed, the program starts
from the address contained in address FFFD16 (high-order byte)
and address FFFC16 (low-order byte). Make sure that the reset input voltage is under 0.6 V for VCC of 3.0 V (L version).
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ;
Vcc = 3.0 V (L version)
RESET
VCC
Power source
voltage detection
circuit
Fig. 107 Example of reset circuit
XIN
φ
RESET
Internal
reset
?
?
Address
?
?
FFFC
F FFD
ADH,L
Reset address from the vector table.
?
Data
?
?
?
ADL
ADH
SYNC
XIN: 10.5 to 18.5 clock cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 108 Reset sequence
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 76 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
PLL CIRCUIT (FREQUENCY SYNTHESIZER)
The PLL circuit generates f VCO (PLL output clock), which is required for f USB (USB clock) and f SYN (fUSB division clock), from
f(XIN) (external input reference clock). Figure 109 shows the PLL
circuit block diagram.
It is possible to input 6 or 12 MHz clock from the externals as a
standard clock input. When using the USB function, set the PLL
operation mode selection bit so that fvco may be set to 48 MHz.
The PLL circuit operates by setting the PLL operation enable bit to
“1”. When supplying fVCO to the USB block, wait for the oscillation
stable time (1ms or less) of PLL before selecting f VCO with the
USB clock selection bit.
According to the setting of the USB clock division ratio selection
bit, the division clock of fUSB is supplied to f SYN. When using this
clock as system clock, set the USB clock division ratio selection
bit so that it may be set to 6 MHz, 8 MHz or 12 MHz. (However,
using it only when fUSB is 48MHz is recommended).
fUSB
f(XIN)
PLL
fVCO
PLLCON
(address 0FF816)
Fig. 109 Block diagram of PLL circuit
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 77 of 112
Division circuit
USBCON
(address 001016)
fSYN
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b7
b0
PLL control register
(PLLCON: address 0FF816)
Not used (return “0” when read)
USB clock division ratio selection bits
b4b3
0 0: Divided by 8 (fSYN = fUSB/8)
0 1: Divided by 6 (fSYN = fUSB/6)
1 0: Divided by 4 (fSYN = fUSB/4)
1 1: Not selected
PLL operation mode selection bits
b6b5
0 0: Not multiplied (fVCO = fXIN)
0 1: Double (fVCO = fXIN ✕ 2)
1 0: Quadruple (fVCO = fXIN ✕ 4)
1 1: Multiplied by 8 (fVCO = fXIN ✕ 8)
PLL Enable Bit
0: Disabled
1: Enabled
Fig. 110 Structure of PLL control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 78 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
CLOCK GENERATING CIRCUIT
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT. Use the circuit constants in accordance with
the resonator manufacturer’s recommended values. No external
resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. (An external feed-back resistor may be needed
depending on conditions.)
Frequency Control
Either fSYN or f(XIN) can be selected as an internal system clock.
Furthermore, the frequency of internal clock φ can be selected by
the system clock division ratio selection bit.
(1) fSYN clock
f SYN clock is generated by the PLL circuit. f(X IN ) or fVCO can be
selected as an input clock. When using as an internal system
clock, there is restriction on use. Refer to the clause of “PLL CIRCUIT”.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and the XIN oscillator stops. When the oscillation stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. X IN
divided by 16 is compulsorily connected to the input of the
prescaler 12. Oscillator restarts when an external interrupt (including USB resume interrupt) is received, but the internal clock φ
remains at “H” until timer 1 underflows. The internal clock φ is not
supplied until timer 1 underflows. Because the sufficient time is required for the oscillation to stabilize when a ceramic resonator etc.
is used. When the oscillator is restarted by reset, apply “L” level to
the RESET pin until the oscillation is stable since a wait time will
not be generated automatically.
(2) f(XIN) clock
The frequency applied to the XIN pin is used as an internal system
clock frequency.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruction.
■Note
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 79 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
b7
XIN
b0
MISRG
(MISRG: address 0FFB16)
XOUT
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set nothing
Not used (indefinite at read)
Rd (Note)
COUT
CI N
Note : Insert a damping resistor if required.
The resistance will vary depending on the oscillator
and the oscillation drive capacity setting.
Use the value recommended by the maker of the
oscillator.
Also, if the oscillator manufacturer's data sheet
specifies that a feedback resistor be added external
to the chip though a feedback resistor exists on-chip,
insert a feedback resistor between XIN and XOUT
following the instruction.
Fig. 113 Structure of MISRG
Fig. 111 Ceramic resonator or quartz-crystal oscilltor circuit
XIN
XOUT
Open
External oscillation circuit
VCC
VSS
Fig. 112 External clock input circuit
XIN
XOUT
PLL
fvco USB clock selection bit
fUSB
1/4
1/6
1/8
USB clock division
ration selection bits
fSYN
System clock selection bit
fsio
fAD
1/2
1/2
1/2
1/2
Prescaler 12
Timer 1
Reset or STP
1/1
1/2
1/4
1/8
FF16
System clock division
ration selection bits
0116 instruction
Timing φ (internal clock)
Q S
R
S Q
STP instruction
WIT
instruction
R
Reset
Interrupt disable flag l
Interrupt request
Fig. 114 System clock generating circuit block diagram (single-chip mode)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 80 of 112
Reset
Q S
R
STP instruction
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Reset
CM6
“0”←→“1”
Note:
Set PLLCON [4:3] = 10 before
switching the system clock from XIN
to fSYN.
f(SYN) 2-divide mode
f(φ) = 6.0 MHz
CM 7 = 1
CM 6 = 0
CM 5 = 1
PLLCON [4:3] = 10
CM5
“0”←→“1”
CM6
“0”←→“1”
Note:
Set PLLCON [4:3] = 00 before switching
the system clock from XIN to fSYN.
CM5
“0”←→“1”
CM6
“0”←→“1”
Note:
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN.
CM6
“0”←→“1”
CM7
“1”←→“0”
XIN 4-divide mode
f(φ) = 1.5 MHz
CM7 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = xx
(arbitrary)
XIN through mode
f(φ) = 1.5 MHz
CM7 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = xx
(arbitrary)
CM5
“1”←→“0”
C
“0 M6
C M ”←
“1 7 →“
1”
”←
→
“0
”
CM7
“1”←→“0”
XIN 2-divide mode
f(φ) = 3.0 MHz
CM 7 = 1
CM 6 = 0
CM 5 = 0
PLLCON [4:3] = xx
(arbitrary)
CM5
“1”←→“0”
CM6
“0”←→“1”
”
6 →“1
CM ”←
1”
“0 M7 →“
C ”←
“0
XIN 8-divide mode
f(φ) = 0.75 MHz
CM7 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = 00
f(SYN) through mode
f(φ) = 12.0 MHz
CM7 = 1
CM6 = 1
CM5 = 1
PLLCON [4:3] = 10
Under planning
f(SYN) through mode
f(φ) = 6.0 MHz
CM7 = 1
CM6 = 1
CM5 = 1
PLLCON [4:3] = 00
f(SYN) through mode
f(φ) = 8.0 MHz
CM7 = 1
CM6 = 1
CM5 = 1
PLLCON [4:3] = 01
CM5
“0”←→“1”
Note:
Set PLLCON [4:3] = 00 before switching
the system clock from XIN to fSYN.
CM5
“0”←→“1”
Note:
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN.
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly
without an allow.)
2 : Set the USB clock (fUSB) to 48 MHz when switching the system clock to fSYN.
3 : Do not change a division ratio of USB clock when using fSYN as the system clock.
4 : See section “PLL CIRCUIT” in details for enabling/disabling PLL operation and usage notes of fSYN.
5 : Set the system clock to XIN when entering STOP mode.
6 : In all modes, switching to WAIT mode is possible. When it is released, the MCU returns to the original mode. In
WAIT mode the timers can operate.
Remarks : This diagram assumes that the 6 MHz signals are applied to XIN pin.
Fig. 115 State transitions of clock
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 81 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
FLASH MEMORY MODE
Summary
The 38K0 group’s flash memory version has an internal new
DINOR (DIvided bit line NOR) flash memory that can be rewritten
with a single power source when VCC is 4.5 to 5.25 V, and 2 power
sources when VCC is 3.0 to 4.5 V.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated
using a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit
(CPU).
Table 8 lists the summary of the 38K0 group’s flash memory version.
This flash memory version has some blocks on the flash memory
as shown in Figure 116 and each block can be erased. The flash
memory is divided into User ROM area and Boot ROM area.
In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a
standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user’s application system. This Boot ROM area can be rewritten in only parallel I/O
mode.
Table 8 Summary of 38K0 group’s flash memory version
Item
Power source voltage (Vcc)
Specifications
3.00 – 5.25 V (L version) (Program and erase in 4.00 to 5.25 V of Vcc.)
3.00 – 4.00 V (L version) (Program and erase in 3.00 to 5.25 V of Vcc.)
Program/Erase VPP voltage (VPP)
Flash memory mode
4.50 – 5.25 V
3 modes; Flash memory can be manipulated as follows:
•CPU rewrite mode: Manipulated by the Central Processing Unit (CPU).
•Parallel I/O mode: Manipulated using an external programmer (Note 1)
Erase block division
User ROM area
Boot ROM area
Program method
Erase method
Program/Erase control method
Number of commands
Number of program/Erase times
Data retention period
ROM code protection
•Standard serial I/O mode: Manipulated using an external programmer (Note 1)
1 block (32 Kbytes)
1 block (4 Kbytes) (Note 2)
Byte program
Batch erasing
Program/Erase control by software command
6 commands
100 times
10 years
Available in parallel I/O mode and standard serial I/O mode
Notes 1: In the parallel I/O mode or the standard serial I/O mode, use the exclusive external equipment flash programmer which supports the 38K0 Group
(flash memory version).
2: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be rewritten in only parallel I/O mode.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 82 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(1) CPU Rewrite Mode
Microcomputer Mode and Boot Mode
In CPU rewrite mode, the internal flash memory can be operated
on (read, program, or erase) under control of the Central Processing Unit (CPU).
In CPU rewrite mode, only the User ROM area shown in Figure
116 can be rewritten; the Boot ROM area cannot be rewritten.
Make sure the program and block erase commands are issued for
only the User ROM area and each block area.
The control program for CPU rewrite mode can be stored in either
User ROM or Boot ROM area. In the CPU rewrite mode, because
the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area to be
executed before it can be executed.
The control program for CPU rewrite mode must be written into
the User ROM or Boot ROM area in parallel I/O mode beforehand.
(If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.)
See Figure 116 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer
is reset with pulling CNVSS pin low. In this case, the CPU starts
operating using the control program in the User ROM area.
When the microcomputer is reset by pulling the P16 (CE) pin high,
the CNVSS pin high, the CPU starts operating using the control
program in the Boot ROM area. This mode is called the “Boot”
mode.
Block Address
Block addresses refer to the maximum address of each block.
These addresses are used in the block erase command.
User ROM area
800016
Block 1 : 32 Kbytes
Boot ROM area
F00016
FFFF16
FFFF16
4 Kbytes
Notes 1: The Boot ROM area can be rewritten in only parallel I/O mode. (Access to any other
areas is inhibited.)
2: To specify a block, use the maximum address in the block.
Fig. 116 Block diagram of built-in flash memory
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 83 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten in CPU rewrite mode.
In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This
rewrite control program must be transferred to a memory such as
the internal RAM before it can be executed.
The MCU enters CPU rewrite mode by applying 4.50 V to 5.25 V
to the CNVSS pin and setting “1” to the CPU Rewrite Mode Select
Bit (bit 1 of address 0FFE16). Software commands are accepted
once the mode is entered.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 117 shows the flash memory control register.
Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase
operations, it is “0” (busy). Otherwise, it is “1” (ready). This is
equivalent to the RY/BY pin function in parallel I/O mode.
Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to
“1”, the MCU enters CPU rewrite mode. Software commands are
accepted once the mode is entered. In CPU rewrite mode, the
b7
CPU becomes unable to access the internal flash memory directly.
Therefore, use the control program in a memory other than internal flash memory for write to bit 1. To set this bit to “1”, it is
necessary to write “0” and then write “1” in succession. The bit can
be set to “0” by only writing “0”.
Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in
CPU rewrite mode, so that reading this flag can check whether
CPU rewrite mode has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit
of internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the
control circuit. To set this bit to “1”, it is necessary to write “0” and
then write “1” in succession. To release the reset, it is necessary
to set this bit to “0”.
Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to
“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In Boot mode, this bit is set to “1” automatically. Reprogramming of this bit must be in a memory other
than internal flash memory.
Figure 118 shows a flowchart for setting/releasing CPU rewrite
mode.
b0
Flash memory control register (address 0FFE16)
FMCR (Note 1)
RY/BY status flag
0: Busy (being written or erased)
1: Ready
CPU rewrite mode select bit (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU rewrite mode entry flag
0: Normal mode (Software commands invalid)
1: CPU rewrite mode
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User area / Boot area select bit (Note 4)
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (indefinite at read/ “0” at write)
Notes 1: The contents of flash memory control register are “XXX00001” just after reset release.
2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not
this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt
will be generated during that interval.
Use the control program in the area except the built-in flash memory for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after
setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory for write to this bit.
Fig. 117 Structure of flash memory control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 84 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Start
Single-chip mode or Boot mode (Note 1)
Set CPU mode register (Note 2)
Transfer CPU rewrite mode control program to
memory other than internal flash memory
Jump to control program transferred in memory
other than internal flash memory
(Subsequent operations are executed by control
program in this memory)
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
Write “0” to CPU rewrite mode select bit
End
Notes 1: When starting the MCU in the single-chip mode or memory expansion mode, supply
4.5 V to 5.25 V to the CNVss pin until checking the CPU rewrite mode entry flag.
2: Set the system clock division ration selection bits of CPU mode register (bits 6 and
7 at address 003B16).
3: Before exiting the CPU rewrite mode after completing erase or program operation,
always be sure to execute the read array command or reset the flash memory.
Fig. 118 CPU rewrite mode set/release flowchart
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 85 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Notes on CPU Rewrite Mode
Take the notes described below when rewriting the flash memory
in CPU rewrite mode.
●Operation speed
During CPU rewrite mode, set the internal clock φ to 1.5 MHz or
less using the system clock division ratio selection bits (bits 6 and
7 of address 003B16).
●Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
●Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
●Watchdog timer
If the watchdog timer has been already activated, internal reset
due to an underflow will not occur because the watchdog timer is
surely cleared during program or erase.
●Reset
Reset is always valid. The MCU is activated using the boot mode
at release of reset in the condition of CNVss = “H”, so that the program will begin at the address which is stored in addresses
FFFC16 and FFFD16 of the boot ROM area.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 86 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
____
Software Commands
Table 9 lists the software commands.
After setting the CPU Rewrite Mode Select Bit to “1”, write a software command to specify an erase or program operation.
Each software command is explained below.
During the program movement, The RY/BY Status Flag of flash
memory control register is set to “0”. When the program completes, it becomes “1”.
At program end, program results can be checked by reading the
status register.
●Read Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7).
The read array mode is retained intact until another command is
written.
Start
Write 4016
Write Write address
Write data
●Read Status Register Command (7016)
When the command code “70 16” is written in the first bus cycle,
the contents of the status register are read out at the data bus (D0
to D7) by a read in the second bus cycle.
The status register is explained in the next section.
Status register
read
●Clear Status Register Command (5016)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
SR7 = 1 ?
or
RY/BY = 1 ?
●Program Command (4016)
Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, the control circuit of flash memory
(data programming and verification) will start a program.
Whether the write operation is completed can be confirmed by
_____
reading the status register or the RY/BY Status Flag. When the
program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus
(DB0 to DB 7). The status register bit 7 (SR7) is set to “0” at the
same time the write operation starts and is returned to “1” upon
completion of the write operation. In this case, the read status register mode remains active until the read array command (FF16) is
written.
SR4 = 0 ?
NO
YES
NO
Program
error
YES
Program
completed
Fig. 119 Program flowchart
Table 9 List of software commands (CPU rewrite mode)
Command
Cycle number
Mode
First bus cycle
Data
Address
(D0 to D7)
X
Second bus cycle
Data
Mode
Address
(D0 to D7)
Read array
1
Write
Read status register
2
Write
X
7016
Clear status register
1
Write
X
5016
Program
2
Write
X
4016
Write
WA (Note 2)
WD (Note 2)
Erase all blocks
2
Write
X
2016
Write
X
2016
Block erase
2
Write
X
2016
Write
(Note 3)
D016
(Note 4)
FF16
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address to be erased (Input the maximum address of each block.)
4: X denotes a given address in the User ROM area .
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 87 of 112
Read
X
BA
SRD (Note 1)
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
●Erase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that
follows, the operation of erase all blocks (erase and erase verify)
starts.
Whether the erase all blocks command is terminated can be con____
firmed by reading the status register or the RY/BY Status Flag of
flash memory control register. When the erase all blocks operation
starts, the read status register mode is entered automatically and
the contents of the status register can be read out at the data bus
(D0 to D7). The status register bit 7 (SR7) is set to “0” at the same
time the erase operation starts and is returned to “1” upon completion of the erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is written.
____
The RY/BY Status Flag is “0” during erase operation and “1” when
the erase operation is completed as is the status register bit 7.
After the erase all blocks end, erase results can be checked by
reading the status register. For details, refer to the section where
the status register is detailed.
●Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” and the block address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
Whether the block erase operation is completed can be confirmed
____
by reading the status register or the RY/BY Status Flag of flash
memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered,
so that the contents of the status register can be read out. The
status register bit 7 (SR7) is set to “0” at the same time the block
erase operation starts and is returned to “1” upon completion of
the block erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is written.
____
The RY/BY Status Flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status register bit 7.
After the block erase ends, erase results can be checked by reading the status register. For details, refer to the section where the
status register is detailed.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 88 of 112
Start
Write 2016
Write
2016/D016
Block address
2016:Erase all blocks
D016:Block erase
Status register
read
SR7 = 1 ?
or
RY/BY = 1 ?
NO
YES
SR5 = 0 ?
YES
Erase completed
Fig. 120 Erase flowchart
NO
Erase error
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Status Register (SRD)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
Also, the status register can be cleared by writing the clear status
register command (5016).
After reset, the status register is set to “8016”.
Table 10 shows the status register. Each bit in this register is explained below.
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write operation. When a write error occurs, it is set to “1”.
The program status is set to “0” when it is cleared.
If “1” is written for any of the SR5 and SR4 bits, the program,
erase all blocks, and block erase commands are not accepted.
Before executing these commands, execute the clear status register command (5016) and clear the status register.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
Table 10 Definition of each bit in status register
Each bit of
SRD0 bits
SR7 (bit7)
Sequencer status
SR6 (bit6)
SR5 (bit5)
Status name
Definition
“1”
“0”
Ready
Busy
Reserved
Erase status
Terminated in error
Terminated normally
SR4 (bit4)
SR3 (bit3)
Program status
Reserved
Terminated in error
-
Terminated normally
-
SR2 (bit2)
SR1 (bit1)
Reserved
Reserved
-
-
SR0 (bit0)
Reserved
-
-
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 89 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Full Status Check
By performing full status check, it is possible to know the execution results of erase and program operations. Figure 121 shows a
full status check flowchart and the action to be taken when each
error occurs.
Read status register
SR4 = 1 and
SR5 = 1 ?
YES
Command
sequence error
NO
SR5 = 0 ?
NO
Erase error
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Should an erase error occur, the block in error
cannot be used.
YES
SR4 = 0 ?
NO
Program error
Should a program error occur, the block in error
cannot be used.
YES
End (block erase, program)
Note: When one of SR5 and SR4 is set to “1”, none of the program, erase all blocks,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 121 Full status check flowchart and remedial procedure for errors
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 90 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode.
●ROM Code Protect Function
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control register (address FFDB16) in parallel I/O mode. Figure 122 shows the ROM code protect control
register (address FFDB16). (This address exists in the User ROM
area.)
b7
If one or both of the pair of ROM Code Protect Bits is set to “0”,
the ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM Code Protect Reset Bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be read out or modified. Once the ROM code
protect is turned on, the contents of the ROM Code Protect Reset
Bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM Code Protect Reset Bits.
b0
ROM code protect control register (address FFDB16)
ROMCP
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits (Note 3)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (Note 1)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
Notes 1: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
3: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite
mode.
Fig. 122 Structure of ROM code protect control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 91 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
ID Code Check Function
Use this function in standard serial I/O mode. When the contents
of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory
to see if they match. If the ID codes do not match, the commands
sent from the programmer are not accepted. The ID code consists
of 8-bit data, and its areas are FFD4 16 to FFDA16. Write a program which has had the ID code preset at these addresses to the
flash memory.
Address
FFD416
ID1
FFD516
ID2
FFD616
ID3
FFD716
ID4
FFD816
ID5
FFD916
ID6
FFDA16
ID7
FFDB16
ROM cord protect control
Interrupt vector area
Fig. 123 ID code store addresses
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 92 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(2) Parallel I/O Mode
Parallel I/O mode is the mode which parallel output and input software command, address, and data required for the operations
(read, program, erase, etc.) to a built-in flash memory. Use the exclusive external equipment flash programmer which supports the
38K0 Group (flash memory version). Refer to each programmer
maker’s handling manual for the details of the usage.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 116 can be rewritten. Both areas of flash memory can be operated
on in the same way.
The boot ROM area is 4 Kbytes in size. It is located at addresses
F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any
location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block.
The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial I/O mode, you must perform
program and block erase in the user ROM area.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 93 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(3) Standard Serial I/O Mode
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires a purpose-specific peripheral unit.The standard serial I/O mode is different from the
parallel I/O mode in that the CPU controls flash memory rewrite
(uses the CPU rewrite mode), rewrite data input and so forth. The
standard serial I/O mode is started by connecting “H” to the P16
(CE) pin and “H” to the P42 (SCLK) pin and “H” to the CNVSS (VPP)
pin (apply 4.5 V to 5.25 V to Vpp from an external source), and releasing the reset operation. (In the ordinary microcomputer mode,
set CNVss pin to “L” level.)
This control program is written in the Boot ROM area when the
product is shipped from Renesas Technology Corp.. Accordingly,
make note of the fact that the standard serial I/O mode cannot be
used if the Boot ROM area is rewritten in parallel I/O mode. Figure
124 shows the pin connections for the standard serial I/O mode.
In standard serial I/O mode, serial data I/O uses the four serial I/O
pins SCLK, RxD, TxD and SRDY (BUSY). The SCLK pin is the transfer clock input pin through which an external transfer clock is
input. The TxD pin is for CMOS output. The SRDY (BUSY) pin outputs “L” level when ready for reception and “H” level when
reception starts.
Serial data I/O is transferred serially in 8-bit units.
In standard serial I/O mode, only the User ROM area shown in
Figure 116 can be rewritten. The Boot ROM area cannot.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, commands sent from the peripheral
unit (programmer) are not accepted unless the ID code matches.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 94 of 112
Outline Performance (Standard Serial I/O
Mode)
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programer, etc.) using 4-wire clock-synchronized serial I/O.
In reception, software commands, addresses and program data
are synchronized with the rise of the transfer clock that is input to
the SCLK pin, and are then input to the MCU via the RxD pin. In
transmission, the read data and status are synchronized with the
fall of the transfer clock, and output from the TxD pin.
The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB
first.
When busy, such as during transmission, reception, erasing or
program execution, the SRDY (BUSY) pin is “H” level. Accordingly,
always start the next transfer after the S RDY (BUSY) pin is “L”
level.
Also, data and status registers in a memory can be read after inputting software commands. Status, such as the operating state of
the flash memory or whether a program or erase operation ended
successfully or not, can be checked by reading the status register.
Here following explains software commands, status registers, etc.
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Table 11 Description of pin function (Standard Serial I/O Mode)
Pin name
VCC,VSS
VCCE
CNVSS
CNVSS2
VREF
DVCC, PVCC
PVSS
____________
RESET
XIN
XOUT
USBVREF
TrON
D0+,D0P00 to P07
P10 to P15
P16
P17
P20 to P27
P30 to P37
P40
P41
P42
P43
P50 to P57
P60 to P63
Signal name
Power supply
Power supply
VPP
CNVSS2
Analog reference voltage
Analog power supply
Analog power supply
Reset input
Clock input
Clock output
USB reference voltage input
USB reference voltage output
USB upstream input
Input port P0
Input port P1
Input port P1
Input port P1
Input port P2
Input port P3
RxD input
TxD output
SCLK input
BUSY output
Input port P5
Input port P6
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 95 of 112
I/O
I
I
I
I
I
O
O
I/O
I
I
I
I
I
I
I
O
I
O
I
I
Function
Apply 3.00 to 5.25 V (L version) to the Vcc pin and 0 V to the Vss pin.
Connect this pin to Vcc.
Connect this pin to VPP (VPP = 4.50 to 5.25 V).
Connect this pin to Vss.
Connect this pin to Vcc when not using.
Connect this pin to Vcc.
Connect this pin to Vss.
To reset, input “L” level for 20 cycles or longer clocks of φ.
Connect a ceramic or crystal resonator between the XIN and XOUT pins. When
entering an externally drived clock, enter it from XIN and leave XOUT open.
Connect this pin to Vcc when not using.
Leave this pin open when not using.
Input “L” level when not using.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open. Input “H” level only at release of reset.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
This is a serial data input pin.
This is a serial data output pin.
This is a serial clock input pin.Input “H” level only at release of reset.
This is a BUSY output pin.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
HARDWARE
38K0 Group
P05
P04
P03
P02
P01
P00
P57
P56
P55
P54
P53
P52/INT1
P51/CNTR0
P50/INT0
P27
P26
FUNCTIONAL DESCRIPTION
Vcc
34
33
36
35
37
41
40
39
38
44
43
42
54
55
56
57
58
59
27
26
25
24
28
M38K09F8LFP/HP
23
22
21
20
60
61
19
18
17
62
63
15
16
13
14
11
12
8
9
10
4
P25
P24
P23
P22
P21
P20
D0D0+
TrON
USBVREF
DVCC
PVCC
PVSS
P63(LED3)
P62(LED2)
P61(LED1)
CE
Mode setup method
Value
4.5 to 5.25 V
RESET
Vcc (Note 2)
Vss → Vcc
CE
Vcc (Note 2)
(Note 1)
VPP
Signal
CNVss
SCLK
RESET
P12/DQ2/AN2
P13/DQ3/AN3
P14/DQ4/AN4
P15/DQ5/AN5
P16/DQ6/AN6
P17/DQ7/AN7
CNVSS
RESET
VCCE
VREF
VSS
XIN
XOUT
VCC
CNVSS2
P60(LED0)
1
64
5
6
7
SCLK
BUSY
32
31
30
29
3
RXD
TXD
49
50
51
52
53
2
P06
P07
P40/EXDREQ/RXD
P41/EXDACK/TXD
P42/EXTC/SCLK
P43/EXA1/SRDY
P30
P31
P32
P33/EXINT
P34/EXCS
P35/EXWR
P36/EXRD
P37/EXA0
P10/DQ0/AN0
P11/DQ1/AN1
47
46
45
48
Vss
Connect to oscillator circuit.
Notes 1: Connect to Vcc in the case of Vcc = 4.5 V to 5.25 V.
Connect to VPP (= 4.5 V to 5.25 V) in the case of Vcc = 3.0 V to 4.5 V.
2: Supply Vcc at releasimg Reset.
Package outline: PLQP0064GA-A, PLQP0064KB-A
Fig. 124 Pin connection diagram in standard serial I/O mode (1)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 96 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Software Commands
Table 12 lists software commands. In standard serial I/O mode,
erase, program and read are controlled by transferring software
commands via the RxD pin. Software commands are explained
here below. Basically, the software commands of the standard serial I/O mode are the same as that of the parallel I/O mode, but the
block erase function is excluded, and 4 commands are added: ID
check, download, version data output and Boot ROM area output
functions.
Table 12 Software commands (Standard serial I/O mode)
Control command
1st byte
transfer
2nd byte
3rd byte
4th byte
5th byte
6th byte
.....
When ID is
not verified
Data
output to
259th byte
Data input
to 259th
byte
Not
acceptable
1
Page read
FF16
Address
(middle)
Address
(high)
Data
output
Data
output
Data
output
2
Page program
4116
Address
(middle)
Address
(high)
Data
input
Data
input
Data
input
3
Erase all blocks
A716
D016
4
Read status register
7016
SRD
output
5
Clear status register
5016
6
ID check function
F516
Address
(low)
Address
(middle)
7
Download function
FA16
Size
(low)
8
Version data output function
FB16
9
Boot ROM area output
function
FC16
Version
data
output
Address
(middle)
Not
acceptable
Not
acceptable
Acceptable
SRD1
output
Not
acceptable
ID size
ID1
Size
(high)
Address
(high)
Checksum
Data
input
Version
data
output
Address
(high)
Version
data
output
Data
output
Version
data
output
Data
output
To
required
number
of times
Version
data
output
Data
output
To ID7
Acceptable
Not
acceptable
Version
data output
to 9th byte
Data
output to
259th byte
Acceptable
Not
acceptable
Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from a programmer to the internal flash memory microcomputer.
2: SRD refers to status register data. SRD1 refers to status register 1 data.
3: All commands can be accepted when the flash memory is totally blank.
4: Address low is A0 to A7; Address middle is A8 to A15; Address high is A16 to A23. Address-high A16 to A23 are always “0016”.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 97 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
(3) From the 4th byte onward, data (D0 to D 7) for the page (256
bytes) specified with addresses A 8 to A 23 will be output sequentially from the smallest address first synchronized with the
fall of the clock.
The contents of software commands are explained as follows.
●Page Read Command
This command reads the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page read
command as explained here following.
SCLK
RxD
FF16
A8 to
A15
A16 to
A23
TxD
data0
data255
SRDY (BUSY)
Fig. 125 Timing for page read
●Read Status Register Command
This command reads status information. When the “7016” command code is transferred with the 1st byte, the contents of the
status register (SRD) with the 2nd byte and the contents of status
register 1 (SRD1) with the 3rd byte are read.
SCLK
RxD
TxD
SRDY (BUSY)
Fig. 126 Timing for reading status register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 98 of 112
7016
SRD
output
SRD1
output
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
●Clear Status Register Command
This command clears the bits (SR3 to SR5) which are set when
the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are
cleared. When the clear status register operation ends, the SRDY
(BUSY) signal changes from “H” to “L” level.
SCLK
RxD
5016
TxD
SRDY (BUSY)
Fig. 127 Timing for clear status register
●Page Program Command
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page program command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
(3) From the 4th byte onward, as write data (D0 to D 7) for the
page (256 bytes) specified with addresses A8 to A23 is input
sequentially from the smallest address first, that page is automatically written.
When reception setup for the next 256 bytes ends, the S RDY
(BUSY) signal changes from “H” to “L” level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
SCLK
RxD
4116
TxD
SRDY (BUSY)
Fig. 128 Timing for page program
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 99 of 112
A8 to
A15
A16 to data0
A23
data255
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
●Erase All Blocks Command
This command erases the contents of all blocks. Execute the
erase all blocks command as explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D0 16” with the 2nd byte.
With the verify command code, the erase operation will start
and continue for all blocks in the flash memory.
When erase all blocks end, the SRDY (BUSY) signal changes from
“H” to “L” level. The result of the erase operation can be known by
reading the status register.
SCLK
RxD
TxD
SRDY (BUSY)
Fig. 129 Timing for erase all blocks
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 100 of 112
A716
D016
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
●Download Command
This command downloads a program to the RAM for execution.
Execute the download command as explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is
added to all data sent with the 5th byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches,
the downloaded program is executed. The size of the program will
vary according to the internal RAM.
SCLK
RxD
FA16
TxD
SRDY (BUSY)
Fig. 130 Timing for download
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 101 of 112
Data size Data size
(low)
(high)
Check
sum
Program
data
Program
data
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
●Version Information Output Command
This command outputs the version information of the control program stored in the Boot ROM area. Execute the version
information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward.
This data is composed of 8 ASCII code characters.
SCLK
RxD
FB16
TxD
‘V’
‘E’
‘R’
‘X’
SRDY (BUSY)
Fig. 131 Timing for version information output
●Boot ROM Area Output Command
This command reads the control program stored in the Boot ROM
area in page (256 bytes) unit. Execute the Boot ROM area output
command as explained here following.
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
(3) From the 4th byte onward, data (D0 to D 7) for the page (256
bytes) specified with addresses A 8 to A 23 will be output sequentially from the smallest address first synchronized with the
fall of the clock.
SCLK
RxD
TxD
SRDY (BUSY)
Fig. 132 Timing for Boot ROM area output
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 102 of 112
FC16
A 8 to A 15
A 1 6 to A23
data0
data255
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
●ID Check
This command checks the ID code. Execute the boot ID check
command as explained here following.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”)
of the 1st byte of the ID code with the 2nd, 3rd and 4th respectively.
(3) Transfer the number of data sets of the ID code with the 5th
byte.
(4) Transfer the ID code with the 6th byte onward, starting with the
1st byte of the code.
SCLK
RxD
F516
D416
FF16
0016
ID size
TxD
SRDY (BUSY)
Fig. 133 Timing for ID check
●ID Code
When the flash memory is not blank, the ID code sent from the serial programmer and the ID code written in the flash memory are
compared to see if they match. If the codes do not match, the
command sent from the serial programmer is not accepted. An ID
code contains 8 bits of data. Area is, from the 1st byte, addresses
FFD416 to FFDA16. Write a program into the flash memory, which
already has the ID code set for these addresses.
Address
FFD416
ID1
FFD516
ID2
FFD616
ID3
FFD716
ID4
FFD816
ID5
FFD916
ID6
FFDA16
ID7
FFDB16
ROM code protect control
Interrupt vector area
Fig. 134 ID code storage addresses
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 103 of 112
ID1
ID7
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
●Status Register (SRD)
The status register indicates operating status of the flash memory
and status such as whether an erase operation or a program
ended successfully or in error. It can be read by writing the read
status register command (70 16 ). Also, the status register is
cleared by writing the clear status register command (5016).
Table 13 lists the definition of each status register bit. After releasing the reset, the status register becomes “8016”.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the the
flash memory.
After power-on and recover from deep power down mode, the sequencer status is set to “1” (ready).
This status bit is set to “0” (busy) during write or erase operation
and is set to “1” upon completion of these operations.
•Erase status (SR5)
The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status
is cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write operation. If a write error occurs, it is set to “1”. When the program
status is cleared, it is set to “0”.
Table 13 Status register (SRD)
Definition
SRD0 bits
Status name
“1”
“0”
Ready
-
Busy
-
Terminated in error
Terminated in error
Terminated normally
Terminated normally
SR7 (bit7)
SR6 (bit6)
Sequencer status
Reserved
SR5 (bit5)
SR4 (bit4)
Erase status
Program status
SR3 (bit3)
SR2 (bit2)
Reserved
Reserved
-
-
SR1 (bit1)
SR0 (bit0)
Reserved
Reserved
-
-
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 104 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
●Status Register 1 (SRD1)
The status register 1 indicates the status of serial communications, results from ID checks and results from check sum
comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by
writing the clear status register command (5016).
Table 14 lists the definition of each status register 1 bit. This register becomes “0016” when power is turned on and the flag status is
maintained even after the reset.
•Boot update completed bit (SR15)
This flag indicates whether the control program was downloaded
to the RAM or not, using the download function.
•Check sum consistency bit (SR12)
This flag indicates whether the check sum matches or not when a
program, is downloaded for execution using the download function.
•ID check completed bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands
cannot be accepted without an ID check.
•Data reception time out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the received data is discarded and the MCU returns to the command
wait state.
Table 14 Status register 1 (SRD1)
SRD1 bits
SR15 (bit7)
SR14 (bit6)
Boot update completed bit
Reserved
SR13 (bit5)
SR12 (bit4)
Reserved
Checksum match bit
SR11 (bit3)
SR10 (bit2)
ID check completed bits
SR9 (bit1)
SR8 (bit0)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Definition
Status name
Data reception time out
Reserved
page 105 of 112
“1”
“0”
Update completed
-
Not Update
-
Match
00
01
Not verified
Verification mismatch
10
11
Reserved
Verified
Time out
-
Mismatch
Normal operation
-
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Full Status Check
Results from executed erase and program operations can be
known by running a full status check. Figure 135 shows a flowchart of the full status check and explains how to remedy errors
which occur.
Read status register
SR4 = 1 and
SR5 = 1 ?
YES
Command
sequence error
NO
SR5 = 0 ?
NO
Erase error
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Should an erase error occur, the block in error
cannot be used.
YES
SR4 = 0 ?
NO
Program error
Should a program error occur, the block in error
cannot be used.
YES
End (Erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks,
and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 135 Full status check flowchart and remedial procedure for errors
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 106 of 112
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION
Example Circuit Application for Standard
Serial I/O Mode
Figure 136 shows a circuit application for the standard serial I/O
mode. Control pins will vary according to a programmer, therefore
see a programmer manual for more information.
VCC
VCC
Clock input
SCLK
BUSY output
SRDY (BUSY)
Data input
RxD
Data output
TxD
VPP power
source input
CNVss
P16 (CE)
M38K09F8L
Notes 1: Control pins and external circuitry will vary according to a programmer. For more
information, see the programmer manual.
2: In this example, the VPP power supply is supplied from an external source (programmer).
To use the user’s power source, connect to 4.5 V to 5.25 V.
Fig. 136 Example circuit application for standard serial I/O mode
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 107 of 112
HARDWARE
38K0 Group
NOTES ON PROGRAMMING
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
• When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
• When a count source of timer X is switched, stop a count of timer
X.
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
A/D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(system clock) in the middle/highspeed mode is at least on 500 kHz during an A/D conversion.
Do not execute the STP or WIT instruction during an A/D conversion.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 108 of 112
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to
execute an instruction. However, When using the USB function or
EXB function, an occurrence of one-wait due to the multichannel
RAM will double an internal clock φ cycle.
HARDWARE
38K0 Group
NOTES ON PROGRAMMING
Definition of A/D Conversion Accuracy
The A/D conversion accuracy is defined below (refer to Figure
137).
•Relative accuracy
➀ Zero transition voltage (VOT)
This means an analog input voltage when the actual A/D conversion output data changes from “0” to “1.”
➁ Full-scale transition voltage (VFST)
This means an analog input voltage when the actual A/D conversion output data changes from “1023” to “1022.”
➂ Non-linearity error
This means a deviation from the line between VOT and VFST of
a converted value between VOT and VFST.
➃ Differential non-linearity error
This means a deviation from the input potential difference required to change a converted value between VOT and VFST by 1
LSB of the 1 LSB at the relative accuracy.
•Absolute accuracy
This means a deviation from the ideal characteristics between 0 to
VREF of actual A/D conversion characteristics.
Output data
Full-scale transition voltage (VFST)
1023
1022
Differential non-linearity error=
c
Non-linearity error= a [LSB]
b-a
a [LSB]
b
a
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB at relative accuracy
b: Vn+1-Vn
c: Difference between
the ideal Vn and actual Vn
Ideal line of A/D
conversion between
V0 to V1022
1
0
Vn
V0
V1
Zero transition voltage (V0T)
Vn+1
V1022
Analog voltage
VREF
Fig. 137 Definition of A/D conversion accuracy
Vn: Analog input voltage when the output data changes from “n” to “n + 1” (n = 0 to 1022)
VFST – V OT
1022
VREF
• 1 LSB at absolute accuracy →
1024
• 1 LSB at relative accuracy →
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 109 of 112
(V)
(V)
HARDWARE
38K0 Group
NOTES ON USAGE/DATA REQUIRED FOR MASK ORDERS
NOTES ON USAGE
Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less than
the recommended operating conditions and design a system not
to cause errors to the system by this unstable operation.
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ceramic or electrolytic capacitor of 1.0 µF is recommended.
USB Port Pins (D0+, D0-) Treatment
•The USB specification requires a driver-impedance 28 to 44 Ω. In
order to meet the USB specification impedance requirements,
connect a resistor (27 Ω recommended) in series to the USB port
pins.
In addition, in order to reduce the ringing and control the falling/
rising timing and a crossover point, connect a capacitor between
the USB port pins and the Vss pin if necessary.
The values and structure of those peripheral elements depend on
the impedance characteristics and the layout of the printed circuit
board. Accordingly, evaluate your system and observe waveforms
before actual use and decide use of elements and the values of
resistors and capacitors.
•Make sure the USB D+/D- lines do not cross any other wires.
Keep a large GND area to protect the USB lines. Also, make sure
you use a USB specification compliant connecter for the connection.
USBVREF pin Treatment (Noise Elimination)
•Connect a capacitor between the USBVREF pin and the Vss pin.
The capacitor should have a 2.2 µF capacitor (electrolytic capacitor) and a 0.1 µF capacitor (ceramic type capacitor) connected in
parallel.
•In Vcc = 3.0 to 3.6 V operation, connect the USBVREF pin directly
to the Vcc pin in order to supply power to the USB port circuit. In
addition, you will need to disable the built-in USB reference voltage circuit in this operation (set bit 4 of the USB control register
to “0”.) If you are using the bus powered supply in this condition,
the DC-DC converter must be placed outside the MCU.
•In Vcc = 4.00 to 5.25 V operation, do not connect the external
DC-DC converter to the USBVREF pin. Use the built-in USB reference voltage circuit.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 110 of 112
USB Communication
In applications requiring high-reliability, we recommend providing
the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB
communication from being terminated unexpectedly, for example
due to external causes such as noise.
Flash Memory Version
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss pin or Vcc pin via a
resistor.
Electric Characteristic Differences Between
Mask ROM and Flash Memory Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between Mask ROM and
Flash Memory version MCUs due to the difference in the manufacturing processes.
When manufacturing an application system with the Flash
Memory version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial
samples of the Mask ROM version.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
1. Mask ROM Order Confirmation Form✽
2. Mark Specification Form✽
3. Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
✽ For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com).
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
A/D Converter
By repeating the above operations up to the lowest-order bit of the
AD conversion register, an analog value converts into a digital
value.
A/D conversion completes at 122 clock cycles (15.25 µs at system
clock = 8 MHz, Through mode) after it is started, and the result of
the conversion is stored into the AD conversion register.
Concurrently with the completion of A/D conversion, A/D conversion
interrupt request occurs, so that the AD conversion interrupt request
bit is set to “1.”
A/D conversion is started by setting AD conversion completion bit to
“0.” During A/D conversion, internal operations are performed as follows.
1. After the start of A/D conversion, AD conversion register goes to
“0016.”
2. The highest-order bit of AD conversion register is set to “1,” and
the comparison voltage Vref is input to the comparator. Then, Vref
is compared with analog input voltage VIN.
3. As a result of comparison, when Vref < VIN, the highest-order bit
of AD conversion register becomes “1.” When V ref > VIN, the
highest-order bit becomes “0.”
Table 15 Relative formula for a reference voltage VREF of A/D
converter and Vref
When n = 0
Vref = 0
VREF
✕n
1024
n: Value of A/D converter (decimal numeral)
When n = 1 to 1023
Vref =
Table 16 Change of AD conversion register during A/D conversion
Change of AD conversion register
Value of comparison voltage (Vref)
At start of conversion
0
0
0
0
0
0
0
0
0
0
First comparison
1
0
0
0
0
0
0
0
0
0
Second comparison
✽1
1
0
0
0
0
0
0
0
0
Third comparison
✽1 ✽2
1
0
0
0
0
0
0
0
After completion of tenth
comparison
A result of A/D conversion
✽1 ✽ 2
✽3 ✽4 ✽5 ✽6
✽1–✽10: A result of the first comparison to the tenth comparison
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 111 of 112
✽ 7 ✽8 ✽ 9 ✽10
0
VREF
2
VREF
±
2
VREF
4
VREF
±
2
VREF
4
±
VREF
8
VREF
±
2
VREF
4
±
••••
±
VREF
1024
HARDWARE
38K0 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 138 shows the A/D conversion equivalent circuit, and Figure 139 shows the A/D conversion timing chart.
VCC
VCC VSS
VSS
About 2 kW
VIN
AN0
Sampling
clock
AN1
C
AN2
Chopper
amplifier
AN3
AN4
AD conversion register 2
AN5
AN6
AN7
AD conversion register 1
b2 b1 b0
AD control register
AD conversion interrupt request
Vref
VREF
Built-in
D/A converter
Reference
clock
VSS
Fig. 138 A/D conversion equivalent circuit
φ
Write signal for AD
control register
61 cycles
AD conversion
completion bit
Sampling clock
Fig. 139 A/D conversion timing chart
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 112 of 112
CHAPTER 2
APPLICATION
2.1 I/O port
2.2 Interrupt
2.3 Timer
2.4 Serial I/O
2.5 USB function
2.6 External bus interface (EXB)
2.7 A/D converter
2.8 Watchdog timer
2.9 Reset
2.10 Frequency synthesizer (PLL)
2.11 Clock generating circuit
2.12 Standby function
2.13 Flash memory
APPLICATION
38K0 Group
2.1 I/O port
2.1 I/O port
This paragraph explains the registers setting method and the notes related to the I/O ports.
2.1.1 Memory map
000016
Port P0 (P0)
000116
Port P0 direction register (P0D)
000216
Port P1 (P1)
000316
Port P1 direction register (P1D)
000416
Port P2 (P2)
000516
Port P2 direction register (P2D)
000616
Port P3 (P3)
000716
000816
Port P3 direction register (P3D)
000916
Port P4 direction register (P4D)
000A16
Port P5 (P5)
Port P4 (P4)
000B16 Port P5 direction register (P5D)
000C16 Port P6 (P6)
000D16 Port P6 direction register (P6D)
0FF016
Port P0 pull-up control register (PULL0)
0FF216
Port P5 pull-up control register (PULL5)
Fig. 2.1.1 Memory map of registers related to I/O port
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 2 of 111
APPLICATION
38K0 Group
2.1 I/O port
2.1.2 Related registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6) (Note)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16]
B
0 Port Pi0
Name
Function
●
1 Port Pi1
●
2 Port Pi2
3 Port Pi3
In output mode
Write Port latch
Read
In input mode
Write : Port latch
Read : Value of pins
At reset
R W
?
?
?
?
4 Port Pi4
?
5 Port Pi5
?
6 Port Pi6
?
7 Port Pi7
?
Note: Since the following ports are not allocated, the corrrsponding bits can not be used.
• P44 to P47
• P64 to P67
Fig. 2.1.2 Structure of Port Pi (i = 0 to 6)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6) (Note)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16]
B
0 Port Pi direction register
1
2
3
4
5
6
7
Function
Name
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
Note: Since the following ports are not allocated, the corrrsponding bits can not be used.
• P44 to P47
• P64 to P67
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 6)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 3 of 111
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
APPLICATION
38K0 Group
2.1 I/O port
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 pull-up control register (PULL0)
[Address : 0FF016]
Name
B
0
P00 pul l-up control bit
1
P00 pul l-up control bit
2
P00 pul l-up control bit
3
P00 pul l-up control bit
4
P00 pul l-up control bit
5
P00 pul l-up control bit
6 P00 pul l-up control bit
7
P00 pul l-up control bit
Function
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
At reset
RW
0
0
0
0
0
0
0
0
Fig. 2.1.4 Structure of Port P0 pull-up control register
Port P5 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P5 pull-up control register (PULL5)
[Address : 0FF216]
B
Name
0 P50 pul l-up control bit
1
Nothing is arranged for this bit. This is a write disabled bit.
When this bit is read out, the contents are “0”.
2 P52 pul l-up control bit
3
page 4 of 111
0 : No pull-up
1 : Pull-up
Nothing is arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0”.
At reset
0
0
0
0
4
0
5
0
6
0
7
0
Fig. 2.1.5 Structure of Port P5 pull-up control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Function
0 : No pull-up
1 : Pull-up
RW
APPLICATION
38K0 Group
2.1 I/O port
2.1.3 Handling of unused pins
Table 2.1.1 Handling of unused pins
Handling
Pins/Ports name
P0, P1, P2, P3, P4, •Set to the input mode and connect each to Vcc or Vss through a resistor of 1 kΩ
to 10 kΩ.
P5, P6
•Set to the output mode and open at “L” or “H” level.
VREF
•Connect to Vss (GND).
XOUT
•Open, only when using an external clock.
•Connect to V CC
USBVREF
TrON
D0+, D0-
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
•Open
•Connect each to Vss through a resistor of 1 kΩ to 10 kΩ.
page 5 of 111
APPLICATION
38K0 Group
2.1 I/O port
2.1.4 Notes on input and output pins
(1) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*1, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
* 1 bit managing instructions : SEB, and CLB instructions
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 6 of 111
APPLICATION
38K0 Group
2.1 I/O port
2.1.5 Termination of unused pins
(1) Terminate unused pins
➀ I/O ports :
• Set the I/O ports for the input mode and connect them to V CC or V SS through each resistor of
1 kΩ to 10 kΩ. With regard to ports which can select the built-in pull-up resistor, the built-in pullup resistor can be used.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the mode
of the ports is switched over to the output mode by the program after reset. Thus, the potential
at these pins is undefined and the power source current may increase in the input mode. With
regard to an effects on the system, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination shown
in (1).
➁ I/O ports :
When setting for the input mode, do not connect to V CC or V SS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or V SS).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to V CC or VSS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 7 of 111
APPLICATION
38K0 Group
2.2 Interrupt
2.2 Interrupt
This paragraph explains the registers setting method and the notes related to the interrupt.
2.2.1 Memory map
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
0FF316
Interrupt edge selection register (INTEDGE)
Fig. 2.2.1 Memory map of registers related to interrupt
2.2.2 Related registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1)
[Address : 3C16]
B
Name
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
SOF interrupt
1 USB
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
device interrupt
2 USB
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
interrupt
3 EXB
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
4 request bit
INT0 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
X interrupt
5 Timer
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
Timer 1 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
Timer 2 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
6 request bit
7 request bit
✽ “0” can be set by software, but “1” cannot be set.
Fig. 2.2.2 Structure of Interrupt request register 1
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 8 of 111
RW
Function
USB bus reset
0 interrupt request bit
APPLICATION
38K0 Group
2.2 Interrupt
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2)
[Address : 3D16]
Name
B
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
INT1 interrupt
0 request bit
1
RW
✽
I/O receive
2 Serial
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
I/O transmit
3 Serial
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
4 request bit
CNTR0 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
wake-up
5 Key-on
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
✽
6
A/D conversion
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
7
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
✽ “0” can be set by software, but “1” cannot be set.
Fig. 2.2.3 Structure of Interrupt request register 2
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1)
[Address : 3E16]
B
Name
USB bus reset
0 interrupt enable bit
SOF interrupt
1 USB
enable bit
device interrupt
2 USB
enable bit
interrupt
3 EXB
enable bit
INT0 interrupt
4 enable bit
X interrupt
5 Timer
enable bit
Timer 1 interrupt
6 enable bit
Timer 2 interrupt
7 enable bit
Fig. 2.2.4 Structure of Interrupt control register 1
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 9 of 111
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
RW
APPLICATION
38K0 Group
2.2 Interrupt
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2)
[Address : 3F16]
0
Name
B
INT1 interrupt
0 enable bit
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
1 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
I/O transmit
3 Serial
interrupt enable bit
wake-up
5 Key-on
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
A/D conversion
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
CNTR0 interrupt
6
0
0
I/O receive
2 Serial
interrupt enable bit
4 enable bit
RW
7 Fix this bit to “0”.
0
0
0
0
0
0
Fig. 2.2.5 Structure of Interrupt control register 2
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE)
[Address : 0FF316]
B
Name
page 10 of 111
At reset
0
1
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
2
INT1 interrupt edge
selection bit
0
3
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are “0”.
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0
0
4
0
5
0
6
0
7
0
Fig. 2.2.6 Structure of Interrupt edge selection register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Function
INT0 interrupt edge
selection bit
R W
APPLICATION
38K0 Group
2.2 Interrupt
2.2.3 Interrupt source
The 38K0 group permits interrupts of 15 sources. These are vector interrupts with a fixed priority system.
Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority
interrupt is accepted first. This priority is determined by hardware, but a variety of priority processing can
be performed by software, using an interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to Table 2.2.1.
Table 2.2.1 Interrupt sources, vector addresses and priority of 38K0 group
Reset (Note 2)
USB bus reset
1
2
USB SOF
USB device
3
4
FFF916
FFF716
FFF816
FFF616
External bus
5
FFF516
FFF416
INT0
6
FFF316
FFF216
Timer X
Timer 1
Timer 2
INT1
7
8
9
10
FFF116
FFEF16
FFED16
FFEB16
FFF016
FFEE16
FFEC16
FFEA16
(Note 3)
Serial I/O
reception
Serial I/O
transmission
CNTR0
—
11
FFE916
FFE716
FFE816
FFE616
12
FFE516
FFE416
13
FFE316
FFE216
Key-on wake up
14
FFE116
FFE016
A/D conversion
15
FFDF16
FFDE16
Interrupt Request
Generating Conditions
At reset
At detection of USB bus reset
signal (2.5 µs interval SE0)
At detection of USB SOF signal
At detection of resume signal (K
state or SE0) or suspend signal
(3 ms interval bus idle), or at
completion of transaction
At completion of reception or
transmission or at completion of
DMA transmission
At detection of either rising or
falling edge of INT0 input
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of INT1 input
(Note 4)
At completion of serial I/O data
reception
At completion of serial I/O data
transmission
At detection of either rising or
falling edge of CNTR0 input
At falling of conjunction of input
level for port P0 (at input mode)
At completion of A/D conversion
BRK instruction
16
FFDD16
FFDC16
At BRK instruction execution
Interrupt Source
Priority
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
FFFB16
FFFA16
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: Nothing is arranged in these vector addresses.
4: Fix bit 1 of interrupt control register 2 (address 003F16) to “0”.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 11 of 111
Remarks
Non-maskable
Valid when USB mode
Valid when USB mode
Valid when USB mode
Valid when external bus is selected
External interrupt
(active edge selectable)
STP release timer underflow
External interrupt
(active edge selectable)
(Note 4)
Valid when serial I/O is selected
Valid when serial I/O is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Non-maskable software interrupt
APPLICATION
38K0 Group
2.2 Interrupt
2.2.4 Interrupt operation
When an interrupt request is accepted, the contents of the following registers just before acceptance of the
interrupt requests is automatically pushed onto the stack area in the order of ➀, ➁ and ➂.
➀High-order contents of program counter (PCH)
➁Low-order contents of program counter (PCL)
➂Contents of processor status register (PS)
After the contents of the above registers are pushed onto the stack area, the accepted interrupt vector
address enters the program counter and consequently the interrupt processing routine is executed.
When the RTI instruction is executed at the end of the interrupt processing routine, the contents of the
above registers pushed onto the stack area are restored to the respective registers in the order of ➂, ➁
and ➀; and the microcomputer resumes the processing executed just before acceptance of the interrupts.
Figure 2.2.7 shows an interrupt operation diagram.
Executing routine
·······
Interrupt occurs
(Accepting interrupt request)
Suspended
operation
Resume processing
Contents of program counter (high-order) are pushed onto stack
Contents of program counter (low-order) are pushed onto stack
Contents of processor status register are pushed onto stack
·······
Interrupt
processing
routine
RTI instruction
Contents of processor status register are popped from stack
Contents of program counter (low-order) are popped from stack
Contents of program counter (high-order) are popped from stack
: Operation commanded by software
: Internal operation performed automatically
Fig. 2.2.7 Interrupt operation diagram
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 12 of 111
APPLICATION
38K0 Group
2.2 Interrupt
(1) Processing upon acceptance of interrupt request
Upon acceptance of an interrupt request, the following operations are automatically performed.
➀The processing being executed is stopped.
➁The contents of the program counter and the processor status register are pushed onto the stack
area. Figure 2.2.8 shows the changes of the stack pointer and the program counter upon acceptance
of an interrupt request.
➂Concurrently with the push operation, the jump destination address (the beginning address of the
interrupt processing routine) of the occurring interrupt stored in the vector address is set in the
program counter, then the interrupt processing routine is executed.
➃After the interrupt processing routine is started, the corresponding interrupt request bit is automatically
cleared to “0”. The interrupt disable flag is set to “1” so that multiple interrupts are disabled.
Accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination
address in the vector area corresponding to each interrupt.
Stack area
Program counter
PCL Program counter (low-order)
PCH Program counter (high-order)
Interrupt disable flag = “0”
Stack pointer
S
(S)
(S)
Interrupt
request is
accepted
Program counter
PCL
Vector address
PCH
(from Interrupt vector area)
Interrupt disable flag = “1”
(s) – 3
Processor status register
Stack pointer
S
Stack area
(S) – 3
Program counter (low-order)
(S) Program counter (high-order)
Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 13 of 111
APPLICATION
38K0 Group
2.2 Interrupt
(2) Timing after acceptance of interrupt request
The interrupt processing routine begins with the machine cycle following the completion of the
instruction that is currently being executed.
Figure 2.2.9 shows the time up to execution of interrupt processing routine and Figure 2.2.10 shows
the timing chart after acceptance of interrupt request.
Interrupt request generated
Start of interrupt processing
Waiting time for
Stack push and
post-processing of
Vector fetch
pipeline
Main routine
✽
2 cycles
0 to 16 cycles
Interrupt processing routine
5 cycles
7 to 23 cycles
(When f(XIN) = 6 MHz; system clock 8 MHz
/through mode (8 MHz), 0.875 µs to 2.875 µs)
✽ When executing DIV instruction
Fig. 2.2.9 Time up to execution of interrupt processing routine
Waiting time for pipeline
post-processing
Push onto stack
Vector fetch
Interrupt operation starts
φ
SYNC
RD
WR
Address bus
Data bus
PC
Not used
S, SPS
S-1, SPS S-2, SPS
PCH
P CL
PS
BL
BH
AL
AL, AH
AH
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
SPS : “0016” or “0116”
Fig. 2.2.10 Timing chart after acceptance of interrupt request
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 14 of 111
APPLICATION
38K0 Group
2.2 Interrupt
2.2.5 Interrupt control
The acceptance of all interrupts, excluding the BRK instruction interrupt, can be controlled by the interrupt
request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. Figure 2.2.11
shows an interrupt control diagram.
Interrupt request bit
Interrupt enable bit
Interrupt request
Interrupt disable flag
BRK instruction
Reset
Fig. 2.2.11 Interrupt control diagram
The interrupt request bit, interrupt enable bit and interrupt disable flag function independently and do not
affect each other. An interrupt is accepted when all the following conditions are satisfied.
●Interrupt request bit .......... “1”
●Interrupt enable bit ........... “1”
●Interrupt disable flag ........ “0”
Though the interrupt priority is determined by hardware, a variety of priority processing can be performed
by software using the above bits and flag. Table 2.2.2 shows a list of interrupt control bits according to the
interrupt source.
(1) Interrupt request bits
The interrupt request bits are allocated to the interrupt request register 1 (address 3C 16) and interrupt
request register 2 (address 3D 16).
The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to
“1”. The interrupt request bit is held in the “1” state until the interrupt is accepted. When the interrupt
is accepted, this bit is automatically cleared to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to “1”, by software.
(2) Interrupt enable bits
The interrupt enable bits are allocated to the interrupt control register 1 (address 003E 16) and the
interrupt control register 2 (address 3F 16).
The interrupt enable bits control the acceptance of the corresponding interrupt request.
When an interrupt enable bit is “0”, the corresponding interrupt request is disabled. If an interrupt
request occurs when this bit is “0”, the corresponding interrupt request bit is set to “1” but the
interrupt is not accepted. In this case, unless the interrupt request bit is set to “0” by software, the
interrupt request bit remains in the “1” state.
When an interrupt enable bit is “1”, the corresponding interrupt is enabled. If an interrupt request
occurs when this bit is “1”, the interrupt is accepted (when interrupt disable flag = “0”).
Each interrupt enable bit can be set to “0” or “1” by software.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 15 of 111
APPLICATION
38K0 Group
2.2 Interrupt
(3) Interrupt disable flag
The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable
flag controls the acceptance of interrupt request except BRK instruction.
When this flag is “1”, the acceptance of interrupt requests is disabled. When the flag is “0”, the
acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set
to “0” with the CLI instruction.
When a main routine branches to an interrupt processing routine, this flag is automatically set to “1”,
so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine. Figure 2.2.12 shows an example of multiple interrupts.
Table 2.2.2 List of interrupt bits according to interrupt source
Interrupt source
USB bus reset
USB SOF
USB device
External bus
INT0
Timer X
Timer 1
Timer 2
INT1
Serial I/O receive
Serial I/O transmit
CNTR 0
Key-on wake-up
A/D converter
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 16 of 111
Interrupt enable bit
Address
003E16
003E16
003E16
003E16
003E16
003E16
003E16
003E16
003F 16
003F 16
003F 16
003F 16
003F 16
003F 16
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b0
b2
b3
b4
b5
b6
Interrupt request bit
Address
003C 16
003C 16
003C 16
003C 16
003C 16
003C 16
003C 16
003C 16
003D 16
003D 16
003D 16
003D 16
003D 16
003D 16
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b0
b2
b3
b4
b5
b6
APPLICATION
38K0 Group
2.2 Interrupt
Interrupt request
Nesting
Reset
Time
Main routine
I=1
C1 = 0, C2 = 0
Interrupt
request 1
C1 = 1
I=0
Interrupt 1
Interrupt
request 2
I=1
Multiple interrupt
C2 = 1
I=0
Interrupt 2
I=1
RTI
I=0
RTI
I=0
I : Interrupt disable flag
C1 : Interrupt enable bit of interrupt 1
C2 : Interrupt enable bit of interrupt 2
: Set automatically.
: Set by software.
Fig. 2.2.12 Example of multiple interrupts
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 17 of 111
APPLICATION
38K0 Group
2.2 Interrupt
2.2.6 INT interrupt
The INT interrupt requests is generated when the microcomputer detects a level change of each INT pin
(INT0, INT 1).
(1) Active edge selection
INT 0 and INT1 can be selected from either a falling edge or rising edge detection as an active edge
by the interrupt edge selection register. In the “0” state, the falling edge of the corresponding pin is
detected. In the “1” state, the rising edge of the corresponding pin is detected.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 18 of 111
APPLICATION
38K0 Group
2.2 Interrupt
2.2.7 Key input interrupt
A key input interrupt request is generated by applying “L” level to any port P0 pin that has been set to the
input mode. In other words, it is generated when AND of the input level goes from “1” to “0”.
(1) Connection example when Key input interrupt is used
When using the Key input interrupt, compose an active-low key matrix which inputs to port P0. Figure
2.2.13 shows a connection example and the port P0 block diagram when using a key input interrupt.
In the connection example in Figure 2.2.13, a key input interrupt request is generated by pressing
one of the keys corresponding to ports P0 0 to P0 3.
Port PXx
“L” level output
PULL 0 register
Bit 7 = “0”
✽
✽✽
Port P07
direction register = “1”
Key input interrupt request
Port P07
latch
P07 output
PULL 0 register
Bit 6 = “0”
✽
✽✽
Port P06
direction register = “1”
Port P06
latch
P06 output
PULL 0 register
Bit 5 = “0”
✽
✽✽
Port P05
direction register = “1”
Port P05
latch
P05 output
PULL 0 register
Bit 4 = “0”
✽
✽✽
Port P04
direction register = “1”
Port P04
latch
P04 output
PULL 0 register
Bit 3 = “1”
✽
✽✽
Port P03
direction register = “0”
Port P03
latch
P03 input
PULL 0 register
Bit 2 = “1”
✽
✽✽
Port P02
direction register = “0”
Port P02
latch
P02 input
PULL 0 register
Bit 1 = “1”
✽
✽✽
P01 input
Port P01
direction register = “0”
Port P01
latch
PULL 0 register
Bit 0 = “1”
✽
P00 input
✽✽
Port P0
Input reading circuit
Port P00
direction register = “0”
Port P00
latch
✽ P-channel transistor for pull-up
✽ ✽ CMOS output buffer
Fig. 2.2.13 Connection example and port P0 block diagram when using key input interrupt
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 19 of 111
APPLICATION
38K0 Group
2.2 Interrupt
(2) Related registers setting
Figure 2.2.14 shows the related registers setting (corresponding to Figure 2.2.13).
Port P0 direction register (address 0116)
b7
P0D
b0
1 1 1 1 0 0 0 0
Bits corresponding to P07 to P00
0: Input port
1: Output port
Port P0 pull-up control register (address 0FF016)
b7
b0
PULL0
1 1 1 1
P00 to P03 pull-up
Interrupt request register 2 (address 3D16)
b7
b0
0
IREQ2
Key-on wake-up interrupt request
Interrupt control register 2 (address 3F16)
b7
ICON2
0
b0
1
0
Key-on wake-up interrupt: Enabled
Fig. 2.2.14 Registers setting related to key input interrupt (corresponding to Figure 2.2.13)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 20 of 111
APPLICATION
38K0 Group
2.2 Interrupt
2.2.8 Notes on interrupts
(1) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
•Interrupt edge selection register (address 0FF3 16)
•Timer X mode register (address 23 16)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit (active edge switch
bit) or the interrupt (source) select bit to “1”.
↓
NOP (One or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig. 2.2.15 Sequence of changing relevant register
■ Reason
When setting the following, the interrupt request bit may be set to “1”.
•When setting external interrupt active edge
Concerned register: Interrupt edge selection register (address 0FF3 16)
Timer X mode register (address 23 16)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 21 of 111
APPLICATION
38K0 Group
2.2 Interrupt
(2) Check of interrupt request bit
● When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one or
more instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 2.2.16 Sequence of check of interrupt request bit
■ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 22 of 111
APPLICATION
38K0 Group
2.3 Timer
2.3 Timer
This paragraph explains the registers setting method and the notes related to the timers.
2.3.1 Memory map
002016
Prescaler 12 (PRE12)
002116
Timer 1 (T1)
002216
Timer 2 (T2)
002316
Timer X mode register (TM)
002416
Prescaler X (PREX)
002516
Timer X (TX)
003C16
003D16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.3.1 Memory map of registers related to timers
2.3.2 Related registers
Prescaler 12, Prescaler X
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12) [Address : 2016]
Prescaler X (PREX) [Address : 2416]
B
Name
Function
0 •Set a count value of each prescaler.
•The value set in this register is written to both each prescaler
1 and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres2 ponding prescaler is read out.
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.3.2 Structure of Prescaler 12, Prescaler X
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset
page 23 of 111
R W
APPLICATION
38K0 Group
2.3 Timer
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 2116]
B
Name
Function
0 •Set a count value of timer 1.
At reset
R W
1
•The value set in this register is written to both timer 1 and timer 1
1 latch at the same time.
•When this register is read out, the timer 1’s count value is read
2 out.
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 2.3.3 Structure of Timer 1
Timer 2, Timer X
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address : 2216]
Timer X (TX) [Address : 2516]
Name
B
0 •Set a count value of each timer.
Function
•The value set in this register is written to both each timer and
1 each timer latch at the same time.
•When this register is read out, each timer’s count value is read
2
out.
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.3.4 Structure of Timer 2, Timer X
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset
page 24 of 111
R W
APPLICATION
38K0 Group
2.3 Timer
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register (TM) [Address : 2316]
B
Function
Name
At reset
0 Timer X operating mode bits
b1 b0
0
1
0
0
1
1
0
2 CNTR0 active edge selection
bit
3 Timer X count stop bit
4
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
The function depends on the
operating mode of Timer X.
(Refer to Table 2.3.1)
0
0 : Count start
1 : Count stop
0
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are “0”.
R W
0
5
0
6
0
7
0
Fig. 2.3.5 Structure of Timer X mode register
Table 2.3.1 CNTR 0 active edge selection bit function
Timer X operation modes
Timer mode
CNTR 0 active edge selection bit
(bits 2 of address 23 16) contents
“0” CNTR 0 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR 0 interrupt request occurrence: Rising edge
; No influence to timer count
Pulse output mode
“0” Pulse output start: Beginning at “H” level
CNTR 0 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR 0 interrupt request occurrence: Rising edge
Event counter mode
“0” Timer X: Rising edge count
CNTR 0 interrupt request occurrence: Falling edge
“1” Timer X: Falling edge count
CNTR 0 interrupt request occurrence: Rising edge
Pulse width measurement mode
“0” Timer X: “H” level width measurement
CNTR 0 interrupt request occurrence: Falling edge
“1” Timer X: “L” level width measurement
CNTR 0 interrupt request occurrence: Rising edge
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 25 of 111
APPLICATION
38K0 Group
2.3 Timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1)
[Address : 3C16]
Name
B
RW
Function
At reset
USB bus reset
0 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
SOF interrupt
1 USB
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
device interrupt
2 USB
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
interrupt
3 EXB
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
4 request bit
INT0 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
X interrupt
5 Timer
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
Timer 1 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
Timer 2 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
6 request bit
7 request bit
✽ “0” can be set by software, but “1” cannot be set.
Fig. 2.3.6 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2)
[Address : 3D16]
B
Name
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
INT1 interrupt
0 request bit
1
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
I/O transmit
3 Serial
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
4 request bit
CNTR0 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
wake-up
5 Key-on
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
✽
6
A/D conversion
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
7
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
Fig. 2.3.7 Structure of Interrupt request register 2
page 26 of 111
✽
I/O receive
2 Serial
interrupt request bit
✽ “0” can be set by software, but “1” cannot be set.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
RW
APPLICATION
38K0 Group
2.3 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1)
[Address : 3E16]
Name
B
USB bus reset
0 interrupt enable bit
SOF interrupt
1 USB
enable bit
device interrupt
2 USB
enable bit
interrupt
3 EXB
enable bit
INT0 interrupt
4 enable bit
X interrupt
5 Timer
enable bit
Timer 1 interrupt
6 enable bit
Timer 2 interrupt
7 enable bit
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
RW
0
0
0
0
0
Fig. 2.3.8 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2)
[Address : 3F16]
0
B
Name
INT1 interrupt
0 enable bit
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0
1 Fix this bit to “0”.
I/O receive
2 Serial
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
I/O transmit
3 Serial
interrupt enable bit
wake-up
5 Key-on
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
A/D conversion
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
CNTR0 interrupt
4 enable bit
6
7 Fix this bit to “0”.
Fig. 2.3.9 Structure of Interrupt control register 2
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 27 of 111
0
0
0
0
0
0
0
RW
APPLICATION
38K0 Group
2.3 Timer
2.3.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer 1, Timer 2)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request
occurs.
<Use>
•Generation of an output signal timing
•Generation of a wait time
[Function 2] Control of Cyclic operation (Timer X, Timer 1, Timer 2)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generation of cyclic interrupts
•Clock function (measurement of 10 ms); see Application example 1
•Control of a main routine cycle
[Function 3] Output of Rectangular waveform (Timer X)
The output level of the CNTR0 pin is inverted each time the timer underflows (in the pulse output
mode).
<Use>
•Piezoelectric buzzer output; see Application example 2
•Generation of the remote control carrier waveforms
[Function 4] Count of External pulses (Timer X)
External pulses input to the CNTR0 pin are counted as the timer count source (in the event counter
mode).
<Use>
•Frequency measurement; see Application example 3
•Division of external pulses
•Generation of interrupts due to a cycle using external pulses as the count source; count of a
reel pulse
[Function 5] Measurement of External pulse width (Timer X)
The “H” or “L” level width of external pulses input to CNTR 0 pin is measured (in the pulse width
measurement mode).
<Use>
•Measurement of external pulse frequency (measurement of pulse width of FG pulse ✽ for a
motor); see Application example 4
•Measurement of external pulse duty (when the frequency is fixed)
FG pulse ✽: Pulse used for detecting the motor speed to control the motor speed.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 28 of 111
APPLICATION
38K0 Group
2.3 Timer
(2) Timer application example 1: Clock function (measurement of 10 ms)
Outline: The input clock is divided by the timer so that the clock can count up at 10 ms intervals.
Specifications: •The clock f(X IN) = 6 MHz is divided by the timer.
•The clock is counted up in the process routine of the timer X interrupt which occurs
at 10 ms intervals.
Figure 2.3.10 shows the timers connection and setting of division ratios; Figure 2.3.11 shows the
related registers setting; Figure 2.3.12 shows the control procedure.
Fixed
Prescaler X
1/16
1/30
f(XIN) = 6 MHz
Timer X
Timer X interrupt
request bit
1/125
0 or 1
Dividing by 100 with software
1/100
10 ms
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.3.10 Timers connection and setting of division ratios
Timer X mode register (address 2316)
b7
b0
1
TM
0 0
Timer X operating mode: Timer mode
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 2416)
b7
b0
PREX
29
Timer X (address 2516)
b7
Set “division ratio – 1”
b0
124
TX
Interrupt request register 1 (address 3C16)
b0
b7
0
IREQ1
Timer X interrupt request
(becomes “1” at 10 ms intervals)
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
1
Timer X interrupt: Enabled
Fig. 2.3.11 Related registers setting
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 29 of 111
1 second
APPLICATION
38K0 Group
2.3 Timer
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
•All interrupts disabled
SEI
TM
IREQ1
ICON1
(address 2316) ← xxxx1x002
(address 3C16) ← xx0xxxxx2
(address 3E16), bit5 ← 1
PREX
TX
(address 2416)
(address 2516)
TM
(address 2316), bit3 ← 0
•Timer X operating mode : Timer mode
•Timer X interrupt request bit cleared
•Timer X interrupt enabled
← 30 – 1
← 125 – 1
•“Division ratio – 1” set to Prescaler X and Timer X
•Timer X count start
CLI
•Interrupts enabled
Main processing
.....
<Procedure for completion of clock set>
(Note 1)
TM
PREX
TX
IREQ1
TM
(address 2316), bit3 ←
(address 2416)
←
(address 2516)
←
(address 3C16), bit5 ←
(address 2316), bit3 ←
•Timer X count stop
•Timer reset to restart count from 0 second after completion of
clock set
1
30 – 1
125 – 1
0
0
•Timer X count start
Note 1: Perform procedure for completion of clock set only
when completing clock set.
Timer X interrupt process routine
Note 2: When using Index X mode flag (T)
Note 3: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
CLT (Note 2)
CLD (Note 3)
Push registers to stack
Clock stop ?
Y
•Judgment whether clock stops
N
Clock count up (1/100 second to year)
Pop registers
RTI
Fig. 2.3.12 Control procedure
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 30 of 111
•Clock counted up
•Pop registers pushed to stack
APPLICATION
38K0 Group
2.3 Timer
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(XIN) = 6 MHz into about 2 kHz (2038
Hz), is output from the P5 1/CNTR 0 pin.
•The level of the P51/CNTR 0 pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.3.13 shows a peripheral circuit example, and Figure 2.3.14 shows the timers connection and
setting of division ratios. Figures 2.3.15 shows the related registers setting, and Figure 2.3.16 shows
the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
CNTR0
output
P51/CNTR0
PiPiPi.....
245 µs 245 µs
Set a division ratio so that the
38K0 Group
underflow output period of the timer X
can be 245 µs.
Fig. 2.3.13 Peripheral circuit example
f(XIN) = 6 MHz
Fixed
Prescaler X
Timer X
Fixed
1/16
1
1/92
1/2
Fig. 2.3.14 Timers connection and setting of division ratios
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 31 of 111
CNTR0
APPLICATION
38K0 Group
2.3 Timer
Timer X mode register (address 2316)
b7
b0
TM
1 0 0 1
Timer X operating mode: Pulse output mode
CNTR0 active edge selection: Output starting at “H” level
Timer X count: Stop
Clear to “0” when starting count.
Timer X (address 2516)
b7
b0
91
TX
Set “division ratio – 1”.
Prescaler X (address 2416)
b0
b7
PREX
0
Fig. 2.3.15 Related registers setting
RESET
Initialization
.....
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
(address 0A16), bit1
(address 0B16)
P5
P5D
1
XXXxXX1X2
.....
ICON1
TM
TX
PREX
(address 3E16), bit4
(address 2316)
(address 2516)
(address 2416)
•Timer X interrupt disabled
•CNTR0 output stop; Piezoelectric buzzer output stop
•“Division ratio – 1” set to Timer X and Prescaler X
0
XXXX10012
92 – 1
1–1
.....
Main processing
.....
Output unit
Yes
•Processing piezoelectric buzzer request, generated during
main processing, in output unit
Piezoelectric buzzer request ?
No
TM (address 2316), bit3
TX (address 2516)
1
92 – 1
TM (address 2316), bit3
0
Piezoelectric buzzer output start
Stop piezoelectric buzzer output
Fig. 2.3.16 Control procedure
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 32 of 111
APPLICATION
38K0 Group
2.3 Timer
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P5 1/CNTR 0 pin with the timer.
•A reference value
Specifications: •The pulse is input to the P5 1/CNTR 0 pin and counted by the timer X.
•A count value is read out at about 2 ms intervals, the timer 1 interrupt interval.
When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note).
Note: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to 40 means the number
of valid value.
Figure 2.3.17 shows the judgment method of valid/invalid of input pulses; Figure 2.3.18 shows the
related registers setting; Figure 2.3.19 shows the control procedure.
......
Input pulse
71.4 µs or more
(14 kHz or less)
......
71.4 µs
(14 kHz)
Invalid
50 µs
(20 kHz)
Valid
2 ms = 28 counts
71.4 µs
Fig. 2.3.17 Judgment method of valid/invalid of input pulses
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 33 of 111
......
50 µs or less
(20 kHz or more)
Invalid
2 ms
50 µs
= 40 counts
APPLICATION
38K0 Group
2.3 Timer
Timer X mode register (address 2316)
b7
b0
1
TM
1 1 0
Timer X operating mode: Event counter mode
CNTR0 active edge selection: Falling edge count
Timer X count: Stop
Clear to “0” when starting count.
Prescaler 12 (address 2016)
b7
b0
PRE12
2
Timer 1 (address 2116)
b7
b0
T1
249
Set “division ratio – 1”.
Prescaler X (address 2416)
b7
b0
PREX
0
Timer X (address 2516)
b7
b0
TX
Set 255 just before counting pulses.
(After a certain time has passed, the number of input
pulses is decreased from this value.)
255
Interrupt control register 1 (address 3E16)
b7
b0
1 0
ICON1
Timer X interrupt: Disabled
Timer 1 interrupt: Enabled
Interrupt request register 1 (address 3C16)
b7
IREQ1
b0
0
Judge Timer X interrupt request bit.
( “1” of this bit when reading the count value indicates the 256 or more
pulses input in the condition of Timer X = 255)
Fig. 2.3.18 Related registers setting
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 34 of 111
APPLICATION
38K0 Group
2.3 Timer
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrary.
•All interrupts disabled
.....
Initialization
SEI
(address 2316) ← XXXX11102
(address 2016) ← 3 – 1
(address 2116) ← 250 – 1
(address 2416)
← 1–1
(address 2516)
← 256 – 1
(address 3E16), bit6 ← 1
•Timer 1 interrupt enabled
TM
(address 2316), bit3 ← 0
•Timer X count start
..... .....
TM
PRE12
T1
PREX
TX
ICON1
CLI
•Timer X operating mode : Event counter mode
(Count a falling edge of pulses input from CNTR0 pin.)
•Division ratio set so that Timer 1 interrupt will occur at
2 ms intervals.
•Interrupts enabled
Timer 1 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
1
IREQ1(address 3C16), bit5 ?
•Processing as out of range when the count value is 256 or more
0
(A)
← TX (address 2516)
•Count value read
•Count value into Accumulator (A) stored
In range
214 < (A) < 228
Out of range
Fpulse ← 0
TX
IREQ1
(address 2516)
← 256 – 1
(address 3C16), bit5 ← 0
•Read value with reference value
compared
•Comparison result to flag Fpulse
stored
Fpulse ← 1
•Counter value initialized
•Timer X interrupt request bit cleared
Process judgment result
Pop registers
RTI
Fig. 2.3.19 Control procedure
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 35 of 111
•Pop registers pushed to stack
APPLICATION
38K0 Group
2.3 Timer
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer X counts the “H” level width of the pulses input to the P5 1 /CNTR 0 pin. An
underflow is detected by the timer X interrupt and an end of the input pulse “H” level is
detected by the CNTR 0 interrupt.
Specifications: •The timer X counts the “H” level width of the FG pulse input to the P51/CNTR 0 pin.
<Example>
When the clock frequency is 6 MHz, the count source is 2.67 µs, which is obtained by dividing the
clock frequency by 16. Measurement can be performed to 175 ms in the range of FFFF16 to 000016.
Figure 2.3.20 shows the timers connection and setting of division ratio; Figure 2.3.21 shows the
related registers setting; Figure 2.3.22 shows the control procedure.
f(XIN) = 6 MHz
Fixed
Prescaler X
Timer X
Timer X interrupt
request bit
1/16
1/256
1/256
0 or 1
175 ms
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.3.20 Timers connection and setting of division ratios
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 36 of 111
APPLICATION
38K0 Group
2.3 Timer
Timer X mode register (address 2316)
b7
b0
1 0 1 1
TM
Timer X operating mode: Pulse width measurement mode
CNTR0 active edge selection: “H” level width measurement
Timer X count: Stop
Clear to “0” when starting count.
Prescaler X (address 2416)
b7
b0
PREX
255
Timer X (address 2516)
b7
Set “division ratio – 1”.
b0
TX
255
Interrupt control register 1 (address 3E16)
b0
b7
ICON1
1
Timer X interrupt: Enabled
Interrupt request register 1 (address 3C16)
b0
b7
IREQ1
0
Timer X interrupt request
(Set to “1” automatically when Timer X underflows)
Interrupt control register 2 (address 3F16)
b0
b7
1
ICON2
CNTR0 interrupt: Enabled
Interrupt request register 2 (address 3D16)
b0
b7
IREQ2
0
CNTR0 interrupt request
(Set to “1” automatically when “H” level input came to the end)
Fig. 2.3.21 Related registers setting
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 37 of 111
APPLICATION
38K0 Group
2.3 Timer
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
.....
•All interrupts disabled
TM
PREX
TX
IREQ1
ICON1
IREQ2
ICON2
•Timer X operating mode : Pulse width measurement mode
(Measure “H” level of pulses input from CNTR0 pin.)
•Set division ratio so that Timer X interrupt will occur at
175 ms intervals.
•Timer X interrupt request bit cleared
•Timer X interrupt enabled
•CNTR0 interrupt request bit cleared
•CNTR0 interrupt enabled
(address 2316), bit3 ← 0
•Timer X count start
.....
(address 2316) ← XXXX10112
(address 2416) ← 256 – 1
(address 2516) ← 256 – 1
(address 3C16), bit5 ← 0
(address 3E16), bit5 ← 1
(address 3D16), bit4 ← 0
(address 3F16), bit4 ← 1
TM
.....
•Interrupts enabled
CLI
Timer X interrupt process routine
Process errors
•Error occurs
RTI
CNTR0 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
(A)
← PREX
Low-order 8-bit result of ← Inverted (A)
pulse width measurement
(A)
← TX
High-order 8-bit result of ← Inverted (A)
pulse width measurement
PREX (address 2416) ← 256 – 1
TX
(address 2516) ← 256 – 1
Pop registers
RTI
Fig. 2.3.22 Control procedure
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 38 of 111
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
•Read the count value and store it to RAM
•Division ratio set so that Timer X interrupt will occur at
175 ms intervals.
•Pop registers pushed to stack
APPLICATION
38K0 Group
2.3 Timer
2.3.4 Notes on timer
● If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
● When switching the count source by the timer X count source selection bit, the value of timer count
is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 39 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
2.4 Serial I/O
This paragraph explains the registers setting method and the notes related to the Serial I/O.
2.4.1 Memory map
~
~
~
~
002616
Transmit/Receive buffer register (TB/RB)
002716
Serial I/O status register (SIOSTS)
~
~
003D16
~
~
Interrupt request register 2 (IREQ2)
~
~
003F16
~
~
Interrupt control register 2 (ICON2)
~
~
~
~
0FE016
Serial I/O control register (SIOCON)
0FE116
UART control register (UARTCON)
0FE216
Baud rate generator (BRG)
~
~
~
~
Interrupt edge selection register (INTEDGE)
0FF316
~
~
Fig. 2.4.1 Memory map of registers related to Serial I/O
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 40 of 111
~
~
APPLICATION
38K0 Group
2.4 Serial I/O
2.4.2 Related registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 2616]
B
Name
Function
0 The transmission data is written to or the receive data is read out
from this buffer register.
1 • At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read
2
out.
At reset
R W
?
?
?
3
?
4
?
5
?
6
?
7
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 2.4.2 Structure of Transmit/Receive buffer register
Serial I/O status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O status register (SIOSTS) [Address : 2716]
B
Name
0 Transmit buffer empty flag
Function
R W
0 : Buffer full
1 : Buffer empty
0
✕
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
0
✕
0
✕
3 Overrun error flag (OE)
0 : No error
1 : Overrun error
0
✕
4 Parity error flag (PE)
0 : No error
1 : Parity error
0
✕
5 Framing error flag (FE)
0 : No error
1 : Framing error
0
✕
6 Summing error flag (SE)
0 : (OE) U (PE) U (FE) = 0
1 : (OE) U (PE) U (FE) = 1
0
✕
1
✕
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the contents are “1”.
Fig. 2.4.3 Structure of Serial I/O status register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset
page 41 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
AA
Serial I/O control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address : 0FE016]
Name
0 BRG count source
B
selection bit (CSS)
1 Serial I/O synchronous
clock selection bit (SCS)
2 SRDY output enable bit
(SRDY)
3 Transmit interrupt
source selection bit (TIC)
4 Transmit enable bit (TE)
5 Receive enable bit (RE)
6 Serial I/O mode selection bit
(SIOM)
7 Serial I/O enable bit
(SIOE)
Function
At reset
0 : System clock
1 : System clock/4
• In clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
• In UART
0 : BRG output divided by 16
1 : External clock input divided by 16
R W
0
0
0 : P43 pin operates as ordinary I/O pin
1 : P43 pin operates as SRDY output pin
0
0 : Interrupt when transmit buffer has emptied
1 : Interrupt when transmit shift operation is
completed
0
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0
0 : Clock asynchronous(UART) serial I/O
1 : Clock synchronous serial I/O
0
0 : Serial I/O disabled
(pins P40 to P43 operate as ordinary I/O pins)
1 : Serial I/O enabled
(pins P40 to P43 operate as serial I/O pins)
0
0
Fig. 2.4.4 Structure of Serial I/O control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 0FE116]
Name
B
0 Character length selection bit
(CHAS)
1 Parity enable bit
(PARE)
2 Parity selection bit
(PARS)
3 Stop bit length selection bit
(STPS)
Function
At reset
0 : 8 bits
1 : 7 bits
0
0 : Parity checking disabled
1 : Parity checking enabled
0
0 : Even parity
1 : Odd parity
0
0 : 1 stop bit
1 : 2 stop bits
0
4 Nothing is allocated for this bit. This is a write disabled bit.
R W
0
✕
1
✕
6
1
✕
7
1
✕
When this bit is read out, the contents are “0”.
5 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the contents are “1”.
Fig. 2.4.5 Structure of UART control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 42 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 0FE216]
Function
B
Set
a
count
value
of
baud
rate
generator.
0
At reset
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
Fig. 2.4.6 Structure of Baud rate generator
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE)
[Address : 0FF316]
Function
Name
B
0
1
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
2
INT1 interrupt edge
selection bit
0
3
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0
0
4
0
5
0
6
0
7
0
Fig. 2.4.7 Structure of Interrupt edge selection register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset
INT0 interrupt edge
selection bit
page 43 of 111
R W
R W
APPLICATION
38K0 Group
2.4 Serial I/O
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2)
[Address : 3D16]
Name
B
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
INT1 interrupt
0 request bit
1
RW
✽
I/O receive
2 Serial
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
I/O transmit
3 Serial
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
4 request bit
CNTR0 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
wake-up
5 Key-on
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
✽
6
A/D conversion
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
7
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
✽ “0” can be set by software, but “1” cannot be set.
Fig. 2.4.8 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2)
[Address : 3F16]
0
B
Name
INT1 interrupt
0 enable bit
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0
1 Fix this bit to “0”.
I/O receive
2 Serial
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
I/O transmit
3 Serial
interrupt enable bit
wake-up
5 Key-on
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
A/D conversion
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
CNTR0 interrupt
4 enable bit
6
7 Fix this bit to “0”.
Fig. 2.4.9 Structure of Interrupt control register 2
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
0
page 44 of 111
0
0
0
0
0
0
RW
APPLICATION
38K0 Group
2.4 Serial I/O
2.4.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.4.10 shows connection examples of a peripheral IC equipped with the CS pin.
There are connection examples using a clock synchronous serial I/O mode.
(1) Only transmission
(Using the RXD pin as an I/O port)
Port
CS
SCLK
CLK
TXD
DATA
38K0 group
Peripheral IC
(OSD controller etc.)
(3) Transmission and reception
(When connecting RXD with TXD
(When connecting IN with OUT in
peripheral IC)
(2) Transmission and reception
Port
CS
SCLK
CLK
TXD
RXD
IN
38K0 group
OUT
Peripheral IC
2
(E PROM etc.)
(4) Connection of plural IC
Port
CS
Port
CS
SCLK
CLK
SCLK
CLK
TXD
IN
TXD
RXD
IN
R XD
Port
OUT
38K0 group ✽1 Peripheral IC ✽2
2
(E PROM etc.)
OUT
Peripheral IC 1
38K0 group
CS
CLK
✽1:
Select an N-channel open-drain output for TXD pin output control.
✽2: Use the OUT pin of peripheral IC which is an N-channel opendrain output and becomes high impedance during receiving data.
Notes: “Port” means an output port controlled by software.
Fig. 2.4.10 Serial I/O connection examples (1)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 45 of 111
IN
OUT
Peripheral IC 2
APPLICATION
38K0 Group
2.4 Serial I/O
(2) Connection with microcomputer
Figure 2.4.11 shows connection examples with another microcomputer.
(1) Selecting internal clock
SCLK
CLK
SCLK
CLK
TXD
IN
TXD
IN
RXD
OUT
RXD
OUT
38K0 group
Microcomputer
(3) Using SRDY signal output function
(Selecting an external clock)
SRDY
SCLK
TXD
R XD
38K0 group
RDY
CLK
IN
OUT
Microcomputer
Fig. 2.4.11 Serial I/O connection examples (2)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
(2) Selecting external clock
page 46 of 111
38K0 group
Microcomputer
(4) In UART
TXD
RXD
RXD
TXD
38K0 group
Microcomputer
APPLICATION
38K0 Group
2.4 Serial I/O
2.4.4 Setting of serial I/O transfer data format
A clock synchronous or clock asynchronous (UART) can be selected as a data format of Serial I/O.
Figure 2.4.12 shows the serial I/O transfer data format.
1ST-8DATA-1SP
ST
LSB
MSB
SP
1ST-7DATA-1SP
ST
LSB
MSB
SP
1ST-8DATA-1PAR-1SP
ST
LSB
MSB
PAR
PAR
SP
MSB
2SP
SP
1ST-7DATA-1PAR-1SP
ST
UART
LSB
MSB
1ST-8DATA-2SP
ST
LSB
1ST-7DATA-2SP
ST
Serial I/O
LSB
MSB
2SP
1ST-8DATA-1PAR-2SP
ST
LSB
MSB
PAR
PAR
2SP
1ST-7DATA-1PAR-2SP
ST
Clock synchronous
Serial I/O
LSB
MSB
LSB first
ST : Start bit
SP : Stop bit
PAR : Parity bit
Fig. 2.4.12 Serial I/O transfer data format
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 47 of 111
2SP
APPLICATION
38K0 Group
2.4 Serial I/O
2.4.5 Serial I/O application examples
(1) Communication using clock synchronous serial I/O (transmit/receive)
Outline : 2-byte
data is transmitted and received, using the clock synchronous serial I/O.
________
The SRDY signal is used for communication control.
Figure 2.4.13 shows a connection diagram, and Figure 2.4.14 shows a timing chart.
Figure 2.4.15 shows a registers setting related to the transmitting side, and Figure 2.4.16 shows
registers setting related to the receiving side.
Transmitting side
Receiving side
P52/INT1
SRDY
SCLK
SCLK
TXD
RXD
38K0 group
38K0 group
Fig. 2.4.13 Connection diagram
Specifications : •
•
•
•
The Serial I/O is used (clock synchronous serial I/O is selected.)
Synchronous clock frequency : 125 kHz (f(X IN) = 6 MHz is divided by 48)
The SRDY (receivable signal) is used.
The receiving side outputs the SRDY signal at intervals of 2 ms (generated by timer),
and 2-byte data is transferred from the transmitting side to the receiving side.
SRDY
••••
SCLK
••••
TXD
D0 D1 D2 D3 D4 D5 D6 D7
D 0 D 1 D2 D 3 D 4 D 5 D6 D7
2 ms
Fig. 2.4.14 Timing chart
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 48 of 111
D0 D1
••••
APPLICATION
38K0 Group
2.4 Serial I/O
Transmitting side
A
AA
A AA
Serial I/O status register (Address : 2716)
b7
SIOSTS
A
AA
A AA
b0
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O control register (Address : 0FE016)
b7
SIOCON
1 1 0 1
b0
0 0
BRG counter source selection bit : f(XIN)
Serial I/O synchronous clock selection bit : BRG/4
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O mode selection bit : Clock synchronous serial I/O
Serial I/O enable bit : Serial I/O enabled
Baud rate generator (Address : 0FE216)
b7
BRG
b0
Set “division ratio – 1”.
11
A
AA
A AA
Interrupt edge selection register (Address : 0FF316)
b7
INTEDGE
b0
0
INT1 interrupt edge selection bit : Falling edge active
Fig. 2.4.15 Registers setting related to transmitting side
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 49 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
Receiving side
AA AA
AA
Serial I/O status register (Address : 2716)
b7
SIOSTS
b0
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : At completing reception
“0” : At reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing.
Summing error flag
“1” : when any one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
AA
A
AA A
Serial I/O control register (Address : 0FE016)
b7
SIOCON 1 1 1 1
b0
1 1
Serial I/O synchronous clock selection bit : External clock
SRDY output enable bit : SRDY output enabled
Transmit enable bit : Transmit enabled
Set this bit to “1”, using SRDY output.
Receive enable bit : Receive enabled
Serial I/O mode selection bit : Clock synchronous serial I/O
Serial I/O enable bit : Serial I/O enabled
Fig. 2.4.16 Registers setting related to receiving side
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 50 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
Figure 2.4.17 shows a control procedure of the transmitting side, and Figure 2.4.18 shows a control
procedure of the receiving side.
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
.....
Initialization
SIOCON (Address : 0FE016) ← 1101xx002
BRG
(Address : 0FE216) ← 12 – 1
INTEDGE (Address : 0FF316), bit2 ← 0
IREQ2 (Address:3D16), bit0?
0
• Detection of INT1 falling edge
1
IREQ2 (Address : 3D16), bit0 ← 0
TB/RB (Address : 2616)
The first byte of a
transmission data
SIOSTS (Address : 2716), bit0?
0
1
TB/RB (Address : 2616)
The second byte of a
transmission data
SIOSTS (Address : 2716), bit0?
0
1
SIOSTS (Address : 2716), bit2?
0
1
Fig. 2.4.17 Control procedure of transmitting side
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 51 of 111
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
APPLICATION
38K0 Group
2.4 Serial I/O
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIOCON (Address : 0FE016)
1111x11x2
N
Pass 2 ms?
• An interval of 2 ms generated by Timer
Y
TB/RB (Address : 2616)
Dummy data
SIOSTS (Address : 2716), bit1?
• SRDY output
SRDY signal is output by writing data to the TB/RB.
Using the SRDY, set Transmit enable bit
(bit4) of the SIOCON to “1.”
0
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set to “0” by reading data.
Read out reception data from
TB/RB (Address : 2616)
0
SIOSTS (Address : 2716), bit1?
• Judgment of completion of receiving
(Receive buffer full flag)
1
Read out reception data from
TB/RB (Address : 2616)
Fig. 2.4.18 Control procedure of receiving side
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 52 of 111
• Reception of the second byte data.
Receive buffer full flag is set to “0” by reading data.
APPLICATION
38K0 Group
2.4 Serial I/O
(2) Output of serial data (control of peripheral IC)
Outline : 4-byte data is transmitted and received, using the clock synchronous serial I/O.
The CS signal is output to a peripheral IC through port P53.
The example for using Serial I/O is shown.
Figure 2.4.19 shows a connection diagram, and Figure 2.4.20 shows a timing chart.
CS
P53
SCLK
CLK
TXD
DATA
38K0 group
CS
CLK
DATA
Peripheral IC
Example for using Serial I/O
Fig. 2.4.19 Connection diagram
Specifications : • The Serial I/O is used (clock synchronous serial I/O is selected.)
• Synchronous clock frequency : 125 kHz (f(X IN) = 6 MHz is divided by 48)
• Transfer direction : LSB first
• The Serial I/O interrupt is not used.
• Port P53 is connected to the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port P5 3 is controlled by software.
CS
CLK
DO0
DATA
Fig. 2.4.20 Timing chart
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 53 of 111
DO1
DO2
DO3
APPLICATION
38K0 Group
2.4 Serial I/O
Figure 2.4.21 shows registers setting related to Serial I/O, and Figure 2.4.22 shows a setting of serial
I/O transmission data.
Serial I/O control register (Address : 0FE016)
b7
SIOCON
b0
1 1 0 1 1 0 0 0
BRG count source selection bit : f(XIN)
Serial I/O synchronous clock selection bit : BRG/4
SRDY output enable bit : SRDY output disabled
Transmit interrupt source selection bit : Transmit shift operating
completion
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O mode selection bit : Clock synchronous serial I/O
Serial I/O enable bit : Serial I/O enabled
Baud rate generator (Address : 0FE216)
b7
b0
11
BRG
Set “division ratio – 1”.
Interrupt control register 2 (Address : 3F16)
b7
b0
ICON2
0
Serial I/O transmit interrupt enable bit : Interrupt disabled
Interrupt request register 2 (Address : 3D16)
b7
b0
IREQ2
0
Serial I/O transmit interrupt request bit
Confirm completion of transmitting
1-byte data by one unit.
“1” : Transmit shift completion
Fig. 2.4.21 Registers setting related to Serial I/O
Transmit/Receive buffer register (Address : 2616)
b7
TB/RB
b0
Set a transmission data.
Confirm that transmission of the previous data is
completed (bit 3 of the Interrupt request register 2
is “1”) before writing data.
Fig. 2.4.22 Setting of serial I/O transmission data
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 54 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
When the registers are set as shown in Fig. 2.4.21, the Serial I/O can transmit 1-byte data by writing
data to the transmit buffer register.
Thus, after setting the CS signal to “L”, write the transmission data to the transmit buffer register by
each 1 byte, and return the CS signal to “H” when the target number of bytes has been transmitted.
Figure 2.4.23 shows a control procedure of Serial I/O.
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
....
Initialization
•Serial I/O set
SIOCON (Address : 0FE016)← 110110002
UARTCON (Address : 0FE116), bit4 ← 0
BRG
(Address : 0FE216)
← 12–1
ICON2
(Address : 3F16), bit3
←0
P5
(Address : 0A16), bit3
←1
P5D
(Address : 0B16)← xxxx1xxx2
•Serial I/O transmit interrupt : Disabled
....
•CS signal output port set
(“H” level output)
P5 (Address : 0A16), bit3
←
•CS signal output level to “L” set
0
•Serial I/O transmit interrupt
request bit set to “0”
IREQ2 (Address : 3D16), bit3 ← 0
TB/RB (Address : 2616)
•Transmission
data write
(Start of transmit 1-byte data)
a transmission
data
IREQ2 (Address : 3D16), bit3?
0
•Judgment of completion of transmitting
1-byte data
1
N
Complete to transmit data?
•Use any of RAM area as a counter for counting
the number of transmitted bytes
•Judgment of completion of transmitting the target
number of bytes
Y
P5 (Address : 0A16), bit3
← 1
Fig. 2.4.23 Control procedure of Serial I/O
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 55 of 111
•Return the CS signal output level to “H”
when transmission of the target number
of bytes is completed
APPLICATION
38K0 Group
2.4 Serial I/O
(3) Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example.
Figure 2.4.24 shows a connection diagram.
SCLK
SCLK
RXD
TXD
TXD
RXD
Master unit
Slave
Fig. 2.4.24 Connection diagram
Specifications :
•
•
•
•
•
•
•
•
The serial I/O is used (clock synchronous serial I/O is selected).
Synchronous clock frequency : 125 kHz (f(XIN) = 6 MHz is divided by 48)
Byte cycle: 488 µs
Number of bytes for transmission or reception : 8 byte/block
Block transfer cycle : 16 ms
Block transfer term : 3.5 ms
Interval between blocks : 12.5 ms
Heading adjustment time : 8 ms
Limitations of specifications :
• Reading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O receive
interrupt request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 56 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
The communication is performed according to the timing shown in Figure 2.4.25. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjustment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.4.26 shows related registers setting.
D0
D1
D2
D7
D0
Byte cycle
Interval between blocks
Block transfer term
Block transfer cycle
Heading adjustment time
Processing for heading adjustment
Fig. 2.4.25 Timing chart
Master unit
Slave unit
Serial I/O control register (Address : 0FE016)
b7
b0
SIOCON
Serial I/O control register (Address : 0FE016)
b7
b0
1 1 1 1 1 0 0 0
SIOCON
1 1 1 1
0 1
BRG count source : f(XIN)
Synchronous clock : BRG/4
SRDY output disabled
Transmit interrupt source :
Transmit shift operating completion
Transmit enabled
Receive enabled
Not affected by external clock
Synchronous clock : External clock
Clock synchronous serial I/O
Clock synchronous serial I/O
Serial I/O enabled
Serial I/O enabled
SRDY output disabled
Not use the serial I/O transmit interrupt
Transmit enabled
Receive enabled
Both of units
Baud rate generator (Address : 0FE216)
b7
b0
BRG
Fig. 2.4.26 Related registers setting
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 57 of 111
11
Set “division ratio – 1”.
APPLICATION
38K0 Group
2.4 Serial I/O
Control procedure :
● Control in the master unit
After setting the related registers shown in Figure 2.4.26, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the transmit buffer register.
To perform the communication in the timing shown in Figure 2.4.25, take the timing into account
and write transmission data. Additionally, read out the reception data when the serial I/O transmit
interrupt request bit is set to “1,” or before the next transmission data is written to the transmit
buffer register.
Figure 2.4.27 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 488 µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
Within a block
transfer term?
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
•Push the register used in the interrupt
processing routine into the stack
N
•Generation of a certain block interval
by using a timer or other functions
Y
Complete to transfer a
block?
Y
Start a block transfer?
N
Y
N
Write a transmission data
Pop registers
Write the first transmission data
(first byte) in a block
•Pop registers which is pushed to stack
RTI
Fig. 2.4.27 Control procedure of master unit
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
•Check the block interval counter and
determine to start a block transfer
Count a block interval counter
Read a reception data
page 58 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
● Control in the slave unit
After setting the related registers as shown in Figure 2.4.26, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O receive interrupt
request bit is set to “1” each time an 8-bit synchronous clock is received.
In the serial I/O receive interrupt processing routine, the data to be transmitted next is written to
the transmit buffer register after the received data is read out.
However, if no serial I/O receive interrupt occurs for a certain time (heading adjustment time or
more), the following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.4.28 shows a control procedure of the slave unit using the serial I/O receive interrupt and
any timer interrupt (for heading adjustment).
Timer interrupt processing
routine
Serial I/O receive interrupt
processing routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
Within a block
transfer term?
N
CLT (Note 1)
•Push the register used in the
CLD (Note 2)
interrupt processing routine into
Push register to stack
the stack
•Confirmation of the received
byte counter to judge the
Heading adjustment counter – 1
block transfer term
Y
N
Heading adjustment
counter = 0?
Read a reception data
•Push the register used in
the interrupt processing
routine into the stack
Y
Write the first transmission
data (first byte) in a block
A received byte counter +1
A received byte
counter ≥ 8?
A received byte counter
Y
0
N
Pop registers
Write dummy data (FF16)
Write a transmission data
•Pop registers which is
pushed to stack
RTI
Initial
value
(Note 3)
Heading
adjustment
counter
Pop registers
•Pop registers which is pushed to stack
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set 8
as the initial value.
RTI
Fig. 2.4.28 Control procedure of slave unit
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 59 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
(4) Communication (transmit/receive) using asynchronous serial I/O (UART)
Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O.
Port P2 0 is used for communication control.
Figure 2.4.29 shows a connection diagram, and Figure 2.4.30 shows a timing chart.
Receiving side
Transmitting side
P20
P20
TXD
RXD
38K0 group
38K0 group
Fig. 2.4.29 Connection diagram (Communication using UART)
Specifications : • The Serial I/O is used (UART is selected).
• Transfer bit rate : 9600 bps (f(X IN) = 6 MHz is divided by 624)
• Communication control using port P2 0
(The output level of port P2 0 is controlled by software.)
• 2-byte data is transferred from the transmitting side to the receiving side at intervals
of 10 ms generated by the timer.
ST D0 D1 D2 D3
D4 D5 D6 D7 SP(2) ST D0
10 ms
Fig. 2.4.30 Timing chart (using UART)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 60 of 111
D1 D2 D3 D4 D5 D6
D7 SP(2)
~
~
TXD
~
~
P20
.
ST D0
.
.....
.....
APPLICATION
38K0 Group
2.4 Serial I/O
Table 2.4.1 shows setting examples of the baud rate generator (BRG) values and transfer bit rate
values; Figure 2.4.31 shows registers setting related to the transmitting side; Figure 2.4.32 shows
registers setting related to the receiving side.
Table 2.4.1 Setting examples of Baud rate generator values and transfer bit rate values
Transfer bit rate
(bps) (Note 3)
600
1200
2400
4800
9600
14400
19200
38400
57600
BRG count source
(Note 1)
f(X IN)/4
f(X IN)/4
f(X IN)
f(X IN)
f(X IN)
f(X IN)
f(X IN)
f(X IN)
f(X IN)
At f(XIN ) = 6 MH Z
BRG setting value (Note
155
77
155
77
38
25
19
9
–
2)
At f(X IN ) = 8 MH Z
BRG setting value (Note
207
103
207
103
51
34
25
12
8
2)
Notes 1: Select the BRG count source with bit 0 of the serial I/O control register (Address : 0FE016 ).
2: These are setting values with small errors.
3: Equation of transfer bit rate:
Transfer bit rate (bps) =
f(X IN)
(BRG setting value + 1) ✕ 16 ✕ m✽
✽m: When bit 0 of the serial I/O control register (Address : 0FE016) is set to “0”, a value of m
is 1.
When bit 0 of the serial I/O control register (Address : 0FE0 16) is set to “1”, a value of
m is 4.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 61 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
Transmitting side
AA
A
AA A
Serial I/O status register (Address : 2716)
b7
b0
SIOSTS
AA
A
AA A
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O control register (Address : 0FE016)
b7
SIOCON 1 0 0 1
b0
0 0 0
BRG count source selection bit : f(XIN)
Serial I/O synchronous clock selection bit : BRG/16
SRDY output enable bit :SRDY out disabled
Transmit enable bit : Transmit enabled
Receive enable bit : Receive disabled
Serial I/O mode selection bit : Asynchronous serial I/O(UART)
Serial I/O enable bit : Serial I/O enabled
AA A
AA A
UART control register (Address : 0FE116)
b7
UARTCON
1
b0
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 0FE216)
b7
BRG
b0
38
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m
✽
–1
✽ When bit 0 of the Serial I/O control register (Address : 0FE016) is set to “0,”
a value of m is 1.
When bit 0 of the Serial I/O control register (Address : 0FE016) is set to “1,”
a value of m is 4.
Fig. 2.4.31 Registers setting related to transmitting side
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 62 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
Receiving side
AA
A
AA A
Serial I/O status register (Address : 2716)
b7
b0
SIOSTS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : At completing reception
“0” : At reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing.
AA
A
AA A
Summing error flag
“1” : When any one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O control register (Address : 0FE016)
b7
SIOCON
1 0 1 0
b0
0 0 0
BRG count source selection bit : f(XIN)
Serial I/O synchronous clock selection bit : BRG/16
SRDY output enable bit : SRDY out disabled
Transmit enable bit : Transmit disabled
Receive enable bit : Receive enabled
Serial I/O mode selection bit : Asynchronous serial I/O(UART)
Serial I/O enable bit : Serial I/O enabled
AA
A
AA A
UART control register (Address : 0FE116)
b7
UARTCON
1
b0
0 0
Character length selection bit : 8 bits
Parity enable bit : Parity checking disabled
Stop bit length selection bit : 2 stop bits
Baud rate generator (Address : 0FE216)
b7
BRG
b0
38
f(XIN)
–1
Transfer bit rate ✕ 16 ✕ m ✽
✽ When bit 0 of the Serial I/O control register (Address : 0FE016) is set to “0,”
a value of m is 1.
When bit 0 of the Serial I/O control register (Address : 0FE016) is set to “1,”
a value of m is 4.
Set
Fig. 2.4.32 Registers setting related to receiving side
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 63 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
Figure 2.4.33 shows a control procedure of the transmitting side, and Figure 2.4.34 shows a control
procedure of the receiving side.
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
.....
Initialization
SIOCON (Address : 0FE016)←1001x0002
UARTCON (Address : 0FE116)← 000010002
BRG
(Address : 0FE216)← 39–1
P2
(Address : 0416), bit0← 0
P2D
(Address : 0516) ← xxxxxxx12
Pass 10 ms?
N
• Port P20 set for communication control
• An interval of 10 ms generated by Timer
Y
P2 (Address : 0416), bit0 ← 1
TB/RB (Address : 2616)
• Communication start
The first byte of a
transmission data
0
SIOSTS (Address : 2716), bit0?
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
1
TB/RB (Address : 2616)
The second byte of
a transmission data
SIOSTS (Address : 2716), bit0?
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
0
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
1
SIOSTS (Address : 2716), bit2?
1
P2 (Address : 0416), bit0 ← 0
Fig. 2.4.33 Control procedure of transmitting side
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 64 of 111
• Communication completion
APPLICATION
38K0 Group
2.4 Serial I/O
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIOCON (Address : 0FE016) ← 1010x0002
UARTCON (Address : 0FE116)← 000010002
BRG
(Address : 0FE216) ← 39–1
P2D
(Address : 0516) ← xxxxxxx02
SIOSTS (Address : 2716), bit1?
0
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 2616)
SIOSTS (Address : 2716), bit6?
1
• Judgment of an error flag
0
• Judgment of completion of
receiving
(Receive buffer full flag)
0
SIOSTS (Address : 2716), bit1?
1
• Reception of the second byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from RB (Address : 2616)
SIOSTS (Address : 2716), bit6?
0
1
P2 (Address : 0416), bit0?
0
Fig. 2.4.34 Control procedure of receiving side
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 65 of 111
1
• Judgment of an error flag
Processing for error
APPLICATION
38K0 Group
2.4 Serial I/O
2.4.6 Notes on serial I/O
(1) Notes when selecting clock synchronous serial I/O (Serial I/O)
➀ Stop of transmission operation
Clear the serial I/O enable bit and the transmit enable bit to “0” (Serial I/O and transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (Serial
I/O disabled).
➂ Stop of transmit/receive operation
Clear the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive
disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O enable bit to “0”
(Serial I/O disabled) (refer to (1) ➀).
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 66 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
(2) Notes when selecting clock asynchronous serial I/O (Serial I/O)
➀ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3) SRDY output of reception side (Serial I/O)
When signals are output from the S RDY pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O control register again (Serial I/O)
Set the serial I/O control register again after the transmission and the reception circuits are reset by
clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
↓
Set both the transmit enable bit (TE) and
the receive enable bit (RE), or one of
them to “1”
Can be set with the LDM instruction at the same time
Fig. 2.4.35 Sequence of setting serial I/O control register again
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 67 of 111
APPLICATION
38K0 Group
2.4 Serial I/O
(5) Data transmission control with referring to transmit shift register completion flag (Serial I/O)
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected (Serial I/O)
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the S CLK input level. Also, write the transmit data to the transmit buffer
register (serial I/O shift register) at “H” of the S CLK input level.
(7) Transmit interrupt request when transmit enable bit is set (Serial I/O)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown
in the following sequence.
➀ Set the interrupt enable bit to “0” (disabled) with CLB instruction.
➁ Prepare serial I/O for transmission/reception.
➂ Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been
executed.
➃ Set the interrupt enable bit to “1” (enabled).
● Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”. The interrupt request is generated and the transmission
interrupt bit is set regardless of which of the two timings listed below is selected as the timing for
the transmission interrupt to be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 68 of 111
APPLICATION
38K0 Group
2.5 USB function
2.5 USB function
Some application notes are available on the Web site: “Renesas Technology Corp.” Homepage
USB Device
(http://www.renesas.com/en/usb)
Please refer to them for explanation and application of USB function.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 69 of 111
APPLICATION
38K0 Group
2.6 External bus interface(EXB)
2.6 External bus interface(EXB)
Some application notes are available on the Web site: “Renesas Technology Corp.” Homepage
USB Device
(http://www.renesas.com/en/usb)
Please refer to them for explanation and application of external bus interface.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 70 of 111
APPLICATION
38K0 Group
2.7 A/D converter
2.7 A/D converter
This paragraph explains the registers setting method and the notes related to the A/D converter.
2.7.1 Memory map
003616
AD control register (ADCON)
003716
AD conversion register 1 (AD1)
003816
AD conversion register 2 (AD2)
003D16 Interrupt request register 2 (IREQ2)
003F16 Interrupt control register 2 (ICON2)
Fig. 2.7.1 Memory map of registers related to A/D converter
2.7.2 Related registers
AA
AA
AD control register
b7 b6 b5 b4 b3 b2 b1 b0
AD control register (ADCON) [Address : 3616 ]
B
0
Name
Analog input pin selection bits
1
2
Function
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : P10/DQ0/AN0
1 : P11/DQ1/AN1
0 : P12/DQ2/AN2
1 : P13/DQ3/AN3
0 : P14/DQ4/AN4
1 : P15/DQ5/AN5
0 : P16/DQ6/AN6
1 : P17/DQ7/AN7
AD conversion completion bit 0 : Conversion in progress
1 : Conversion completed
3
4 Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are indefinite.
0
1
?
5
?
6
?
7
?
Fig. 2.7.2 Structure of AD control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset
page 71 of 111
R W
APPLICATION
38K0 Group
2.7 A/D converter
AD conversion register 1
b7 b6 b5 b4 b3 b2 b1 b0
AD conversion register 1 (AD1) [Address : 3716]
B
Function
At reset
R W
?
✕
?
✕
b0
?
✕
b9 b8 b7 b6 b5 b4 b3 b2
?
✕
?
✕
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A/D conversion’s results are
1
stored.
2
b7
3
4
b7
5
< 8-bit read>
< 10-bit read>
b0
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 2.7.3 Structure of AD conversion register 1
A
A
AD conversion register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
AD conversion register 2 (AD2) [Address : 38
16]
B
Function
Name
R W
?
✕
?
✕
0
✕
0
✕
4
0
✕
5
0
✕
6
0
✕
7 Fix this bit to “0”.
0
✕
0 The read-only register in which the A/D conversion’s results are
stored.
AA
AA
b7
1
0
< 10-bit read>
b0
b9 b8
2 Nothing is allocated for these bits. These are write disabled bits.
3
When these bits are read out, the contents are “0”.
Fig. 2.7.4 Structure of AD conversion register 2
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset
page 72 of 111
APPLICATION
38K0 Group
2.7 A/D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2)
[Address : 3D16]
B
Name
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
INT1 interrupt
0 request bit
1
RW
✽
I/O receive
2 Serial
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
I/O transmit
3 Serial
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
4 request bit
CNTR0 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
wake-up
5 Key-on
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
✽
6
A/D conversion
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
7
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
✽ “0” can be set by software, but “1” cannot be set.
Fig. 2.7.5 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2)
[Address : 3F16]
0
B
Name
INT1 interrupt
0 enable bit
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0
1 Fix this bit to “0”.
I/O receive
2 Serial
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
I/O transmit
3 Serial
interrupt enable bit
wake-up
5 Key-on
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
A/D conversion
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
CNTR0 interrupt
4 enable bit
6
7 Fix this bit to “0”.
Fig. 2.7.6 Structure of Interrupt control register 2
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 73 of 111
0
0
0
0
0
0
0
RW
APPLICATION
38K0 Group
2.7 A/D converter
2.7.3 A/D converter application examples
(1) Conversion of analog input voltage
Outline : The analog input voltage input from a sensor is converted to digital values.
Figure 2.7.7 shows a connection diagram, and Figure 2.7.8 shows the related registers setting.
P10/DQ0/AN0
Sensor
38K0 Group
Fig. 2.7.7 Connection diagram
Specifications : •The analog input voltage input from a sensor is converted to digital values.
•P10/DQ 0/AN 0 pin is used as an analog input pin.
AD control register (address 3616)
b7
b0
0 0 0 0
ADCON
Analog input pin : P10/DQ0/AN0 selected
A/D conversion start
AA A
AA A
AD conversion register 2 (address 3816)
b7
AD2
b0
(Read-only)
0
AD conversion register 1 (address 3716)
b7
b0
(Read-only)
AD1
A result of A/D conversion is stored (Note).
Note: After bit 3 of ADCON is set to “1”, read out that contents.
When reading 10-bit data, read address 003816 before address 003716;
when reading 8-bit data, read address 003716 only.
When reading 10-bit data, bits 2 to 6 of address 003816 are “0”.
Fig. 2.7.8 Related registers setting
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 74 of 111
APPLICATION
38K0 Group
2.7 A/D converter
An analog input signal from a sensor is converted to the digital value according to the related
registers setting shown by Figure 2.7.8. Figure 2.7.9 shows the control procedure for 8-bit read, and
Figure 2.7.10 shows the control procedure for 10-bit read.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
ADCON (address 3616) ← XXXX00002
ADCON (address 3616), bit3 ?
•P10/DQ0/AN0 pin selected as analog input pin
•A/D conversion start
0
•Judgment of A/D conversion completion
1
•Read out of conversion result
Read out AD1 (address 3716)
Fig. 2.7.9 Control procedure for 8-bit read
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
•P10/DQ0/AN0 pin selected as analog input pin
•A/D conversion start
ADCON (address 3616) ← XXXX00002
ADCON (address 3616), bit3 ?
0
•Judgment of A/D conversion completion
1
Read out AD2 (address 3816)
•Read out of high-order digit (b9, b8) of conversion result
Read out AD1 (address 3716)
•Read out of low-order digit (b7 – b0) of conversion result
Fig. 2.7.10 Control procedure for 10-bit read
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 75 of 111
APPLICATION
38K0 Group
2.7 A/D converter
2.7.4 Notes on A/D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion precision to be worse.
(2) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A/D conversion.
• f(X IN ) is 500 kHz or more
• Do not execute the STP instruction
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 76 of 111
APPLICATION
38K0 Group
2.8 Watchdog timer
2.8 Watchdog timer
This paragraph explains the registers setting method and the notes related to the watchdog timer.
2.8.1 Memory map
003916
Watchdog timer control register (WDTCON)
003B16
CPU mode register (CPUM)
Fig. 2.8.1 Memory map of registers related to watchdog timer
2.8.2 Related registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register (WDTCON) [Address : 3916]
Function
B
Name
0 Watchdog timer H (for read-out of high-order 6 bits)
R W
1
✕
1
1
✕
2
1
✕
3
1
✕
4
1
✕
5
1
✕
6 STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
0
7 Watchdog timer H count
0 : Watchdog timer L underflow
1 : System clock/16
0
source selection bit
Fig. 2.8.2 Structure of Watchdog timer control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset
page 77 of 111
APPLICATION
38K0 Group
2.8 Watchdog timer
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 1
CPU mode register
(CPUM: address 3B16)
B
0
Function
Name
Processor mode bits
1
b1 b0
0 0 : Single-chip mode
0 1 : Not available
1 0 : Not available
1 1 : Not available
0 : 0 page
1 : 1 page
0
*
2
Stack page selection bit
3
Fix this bit to “1”.
1
4
Fix this bit to “0”.
0
5
System clock selection bit
0 : Main clock f(XIN)
1 : fSYN
6
System clock division ratio
selection bits
b7 b6
7
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
*: The initial value of bit 1 depends on the CNVss level.
Fig. 2.8.3 Structure of CPU mode register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset R W
page 78 of 111
0
0
0
APPLICATION
38K0 Group
2.8 Watchdog timer
2.8.3 Watchdog timer application examples
(1) Detection of program runaway
Outline: If program runaway occurs, let the microcomputer reset, using the internal timer for detection
of program runaway.
Specifications: •An underflow of watchdog timer H is judged to be program runaway, and the
microcomputer is returned to the reset status.
•Before the watchdog timer H underflows, “0” is set into bit 7 of the watchdog timer
control register at every cycle in a main routine.
•Through mode is used as a system clock division ratio.
•An underflow signal of the watchdog timer L is supplied as the count source of
watchdog timer H.
Figure 2.8.4 shows a watchdog timer connection and division ratio setting; Figure 2.8.5 shows the
related registers setting; Figure 2.8.6 shows the control procedure.
Fixed
f(XIN) = 6 MHz
Watchdog timer L Watchdog timer H
1/16
1/256
RESET
STP instruction disable bit
STP instruction
1/256
A
AA
A
A
AA
AA
AA
Fig. 2.8.4 Watchdog timer connection and division ratio setting
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 79 of 111
Reset
circuit
Internal reset
APPLICATION
38K0 Group
2.8 Watchdog timer
CPU mode register (address 3B16)
b7
CPUM
b0
1 1 0 0 1
0 0
Processor mode: Single-chip mode
System clock: Main clock
System clock division ratio: f(system clock) (Through mode)
Watchdog timer control register (address 3916)
WDTCON
b7
b0
0 0
1
Watchdog timer H (for read-out of high-order 6 bits)
Enable STP instruction
Watchdog timer H count source: Watchdog timer L underflow
Fig. 2.8.5 Related registers setting
RESET
Initialization
SEI
CLT
CLD
CPUM (address 3B16) ← 11001X002
:
:
CLI
WDTCON (address 3916), bit7,bit6
•All interrupts disabled
•Processor mode: Single-chip mode
•Main clock f(XIN): Operating
•Through mode selected as main clock division ratio
•Interrupts enabled
002
•Watchdog timer L underflow selected as Watchdog
timer H count source
•STP instruction enabled
Main processing
:
:
Fig. 2.8.6 Control procedure
2.8.4 Notes on watchdog timer
●Make sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog
timer keeps counting during that term.
●When the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 80 of 111
APPLICATION
38K0 Group
2.9 Reset
2.9 Reset
2.9.1 Connection example of reset IC
VCC
1
Power source
General-purpose
reset IC
5 Output
RESET
4 Delay capacity
0.1 µF
GND
VSS
3
38K0 Group
Fig. 2.9.1 Example of poweron reset circuit
Figure 2.9.2 shows the system example which switches to the RAM backup mode by detecting a drop of
the system power source voltage with the INT interrupt.
System power
source voltage
+5 V
VCC
+
7
VCC1
RESET
2
VCC2
5
RESET
3
INT
INT
VSS
1
V1 GND Cd
4
6
M62009L, M62009P, M62009FP
Fig. 2.9.2 RAM backup system
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 81 of 111
38K0 Group
APPLICATION
38K0 Group
2.9 Reset
____________
2.9.2 Notes on RESET pin
Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 82 of 111
APPLICATION
38K0 Group
2.10 Frequency synthesizer (PLL)
2.10 Frequency synthesizer (PLL)
This paragraph explains the registers setting method and the notes related to the frequency synthesizer
(PLL circuit).
2.10.1 Memory map
001016
USB control register (USBCON)
003B16
CPU mode register (CPUM)
0FF816
PLL control register (PLLCON)
Fig. 2.10.1 Memory map of registers related to PLL
2.10.2 Related registers
USB control register
USB control register (USBCON)
[Address 1016]
b7 b6 b5 b4 b3 b2 b1 b0
Name
B
At reset
0
Remote wakeup bit
1
TrON output control bit
0 : “L” output mode (valid in TRONE = “1”)
1 : “H” output mode (valid in TRONE = “1”)
0
2
TrON output enable bit
0 : TrON port output disabled (Hi-Z state)
1 : TrON port output enabled
0
3
USB reference voltage
control bit
0 : Normal mode (valid in VREFE = “1”)
1 : Low current mode (valid in VREFE = “1”)
0
4
USB reference voltage
enable bit
0 : USB reference voltage circuit operation disabled
1 : USB reference voltage circuit operation enabled
0
5
USB difference input
enable bit
0 : Upstream-port difference input circuit operation disabled
1 : Upstream--port difference input circuit operation enabled
0
6
USB clock select bit
0 : External oscillating clock f(XIN)
1 : PLL circuit output clock fVCO
0
7
USB module operation
enable bit
0 : USB module reset
1 : USB module operation enabled
0
Fig. 2.10.2 Structure of USB control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Function
0 : Returning to BUS idle state by writing “1” first
and then “0”. (Remote wakeup signal)
1 : K-state output
page 83 of 111
0
RW
APPLICATION
38K0 Group
2.10 Frequency synthesizer (PLL)
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 1
CPU mode register
(CPUM: address 3B16)
B
0
Processor mode bits
1
At reset R W
Function
Name
b1 b0
0
0 0 : Single-chip mode
0 1 : Not available
1 0 : Not available
1 1 : Not available
0 : 0 page
1 : 1 page
*
2
Stack page selection bit
3
Fix this bit to “1”.
1
4
Fix this bit to “0”.
0
5
System clock selection bit
0 : Main clock f(XIN)
1 : fSYN
6
System clock division ratio
selection bits
b7 b6
7
0
0
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
0
*: The initial value of bit 1 depends on the CNVss level.
Fig. 2.10.3 Structure of CPU mode register
PLL control register
b7 b6 b5 b4 b3 b2 b1 b0
PLL control register (PLLCON)
[Address : 0FF816]
Name
B
Function
0 Nothing is arranged for these bit. These are write disabled bits.
1 When these bits are read out, the contents are “0”.
2
3 USB clock division b4 b3
ratio selection bits 0 0 : Divided by 8 (fSYN = fUSB/8)
0 1 : Divided by 6 (fSYN = fUSB/6)
4
1 0 : Divided by 4 (fSYN = fUSB/4)
1 1 : Not selected
5
6
7
PLL operation mode b6 b5
0 0 : Not multiplied (fVCO = fXIN)
selection bits
0 1 : Double (fVCO = fXIN ✕ 2)
1 0 : Quadruple (fVCO = fXIN ✕ 4)
1 1 : Multiplied by 8 (fVCO = fXIN ✕ 8)
PLL enable bit
0 : Disabled
1 : Enabled
Fig. 2.10.4 Structure of PLL control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 84 of 111
At reset
0
0
0
0
RW
APPLICATION
38K0 Group
2.10 Frequency synthesizer (PLL)
2.10.3 Functional description
The frequency synthesizer generates the 48 MHz clock which is multiples of the external input reference
f(X IN) and is needed for operating USB function. When using the USB function, set PLL enable bit of PLL
control register (PLLCON: address 0FF816) to “1” (enabled) to send the 48 MHz PLL output clock (fVCO) into
USB function control unit. Figure 2.10.5 shows the block diagram for the frequency synthesizer circuit.
fUSB
f(XIN)
PLL
fVCO
PLLCON
(address 0FF816)
Division circuit
fSYN
USBCON
(address 001016)
Fig. 2.10.5 Block diagram for frequency synthesizer circuit
● f VCO (PLL output clock)
f VCO is generated by multiplying PLL input clock according to the contents of PLL operation mode
selection bits (bits 6, 5 of PLLCON), where
f VCO =f(X IN) ✕ n, n:value selected by PLL operation mode selection bits
Set PLL operation mode selection bits so that f VCO may be set to 48 MHz.
While the PLL enable bit is “0” (disabled), f VCO retains “L” level (except when PLL operation mode
selection bits are set to “002”).
Table 2.10.1 shows the example of PLL operation mode selection bits setting.
Table 2.10.1 PLL operation mode selection bits setting example
f(X IN)
PLL operation mode
selection bits *
11
10
6 MH Z
12 MH Z
*: PLL control register (bits 6,5)
fVCO
48 MH Z
48 MH Z
Furthermore, when PLL operation mode selection bits are set to “00 2”, the clock input into PLL is
used as fVCO, which is not multiplied, regardless of PLL operation enabled or disabled.
● f USB (USB clock)
Either f(XIN) (main clock) or fVCO (PLL output clock) can be selected for f USB by USB clock select bit
of USB control register (bit6 of USBCON: address 0010 16), and it is supplied to the USB function
control circuit. When supplying f VCO to the USB function control circuit, after setting PLL enable bit
to “1” (enabled) and then set USB clock select bit to “1” (USB clock).
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 85 of 111
APPLICATION
38K0 Group
2.10 Frequency synthesizer (PLL)
● f SYN (f USB division clock)
According to the setting of the USB clock division ratio selection bits (bits 4, 3 of PLLCON), the
division clock of f USB is supplied to f SYN.
fSYN =f USB / m, m:value selected by USB clock division ratio selection bits
Set the USB clock division ratio selection bits so that fSYN may be set to 6 MHz, 8 MHz or 12 MHz.
When using f SYN as internal system clock, set the system clock selection bit of CPU mode register
(bit 5 of CPUM: address 003B 16) to “1” (f SYN).
Table 2.10.2 shows the example of USB clock division ratio selection bits setting.
Table 2.10.2 USB clock division ratio selection bits setting example
f USB
48 MH Z
USB clock division
ratio selection bits *
00
01
10
fSYN
6 MH Z
8 MH Z
12 MH Z
*: PLL control register (bit4,3)
● Setting for starting up PLL circuit when hardware reset
Figure 2.10.6 shows the example of related registers setting.
● X: This bit is not used here.
Set it to “0” or “1” arbitrarily.
CPUM (address: 3B16) ← 11001X002
•Select main clock f(XIN) as a system clock
USBCON (address: 1016) ← X0XXXXXX2
•Select main clock f(XIN) as a USB clock
PLLCON (address: 0FF816) ← 111010002
•PLL operation mode (bit6,5): Multiplied by 8
•USB division mode (bit4,3): Divided by 6
•Enable PLL operation (bit7)
Wait (approximately 1 ms)
USBCON (address: 1016) ← X1XXXXXX2
CPUM (address: 3B16) ← 11101X002
•Wait for oscillation stabilization
When multiplying oscillation by PLL, wait for oscillation
stabilization.
•Select PLL circuit output clock fVCO as a USB clock
•Select fSYN as a system clock
Note: The above setting example assumes the operation when the external oscillating clock is 6 MHZ and
the internal system clock is fSYN.
Fig. 2.10.6 Related registers setting when hardware reset
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 86 of 111
APPLICATION
38K0 Group
2.10 Frequency synthesizer (PLL)
● Procedure for stop and return of PLL circuit when stop mode
Figure 2.10.7 shows the stop procedure of PLL circuit, and figure 2.10.8 shows the return procedure
of PLL circuit.
PLL circuit operation enabled
(Supply PLL circuit output clock fVCO as USB clock)
● X: This bit is not used here.
Set it to “0” or “1” arbitrarily.
CPUM (address: 3B16) ← 11001X002
•Select main clock f(XIN) as a system clock
USBCON (address: 1016) ← X1XXXXXX2
•Select PLL circuit output clock fVCO as a USB clock
and does not change this setting
PLLCON (address: 0FF816) ← 0XXXX0002
•Disable PLL operation (bit7)
(fVCO is fixed to “L”.)
STP instruction (stop mode)
•Stop mode
Note: The above setting example assumes the operation when the external oscillating clock is 6 MHZ and
the internal system clock is fSYN.
Fig. 2.10.7 Related registers setting when stop mode
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 87 of 111
APPLICATION
38K0 Group
2.10 Frequency synthesizer (PLL)
After recovery from stop mode
● X: This bit is not used here.
Set it to “0” or “1” arbitrarily.
PLLCON (address: 0FF816) bit6,5 ← 002
•PLL operation mode (bit6,5): Not multiplied
(Change PLL circuit output clock fVCO to f(XIN))
USBCON (address: 1016) ← X0XXXXXX2
•Select main clock f(XIN) as a USB clock
PLLCON (address: 0FF816) ← 111010002
•PLL operation mode (bit6,5): Multiplied by 8
•USB division mode (bit4,3): Divided by 6
•Enable PLL operation (bit7)
Wait (approximately 1 ms)
USBCON (address: 1016) ← X1XXXXXX2
CPUM (address: 3B16) ← 11101X002
•Wait for oscillation stabilization
When multiplying oscillation by PLL, wait for oscillation
stabilization.
•Select PLL circuit output clock fVCO as a USB clock
•Select fSYN (8MHZ) as a system clock
Same setting procedure when hardware reset
Note: The above setting example assumes the operation when the external oscillating clock is 6 MHZ and
the internal system clock is fSYN.
Fig. 2.10.8 Related registers setting when recovery from stop mode
2.10.4 Notes on PLL
●6 MH Z or 12 MH Z external oscillator can be connected as an input reference clock (f(X IN)). When using
the frequency synthesized clock function, we recommend using the fastest frequency possible of f(X IN)
as an input clock reference for the PLL.
●When enabling PLL operation from PLL disabled status (disabled when reset), set the USB clock select
bit of USBCON to “0” (f(XIN)) to operate with the main clock (f(X IN)).
●When supplying fVCO to the USB block after setting PLL operation enable bit to “1” (PLL enabled), wait
for the oscillation stable time (1 ms or less) of PLL to avoid any instability caused by the clock, then set
USB clock select bit to “1” (USB clock).
●When selecting f SYN as an internal system clock, f USB must be 48 MHz.
●When selecting f SYN as an internal system clock, change the system clock selection bit to main clock
(f(XIN)) before executing STP instruction. It is because the following are needed for the low-power consumption:
•f USB must be stopped by disabling PLL operation in Stop mode.
•The taimer 1 for waiting oscillation stabilization when returning from Stop mode will require the input
count source.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 88 of 111
APPLICATION
38K0 Group
2.11 Clock generating circuit
2.11 Clock generating circuit
This paragraph explains the registers setting method and the notes related to the clock generating circuit.
2.11.1 Memory map
001016
USB control register (USBCON)
003B16
CPU mode register (CPUM)
0FF816
PLL control register (PLLCON)
Fig. 2.11.1 Memory map of registers related to clock generating circuit
2.11.2 Related registers
USB control register
USB control register (USBCON)
[Address 1016]
b7 b6 b5 b4 b3 b2 b1 b0
Name
B
At reset
0
Remote wakeup bit
1
TrON output control bit
0 : “L” output mode (valid in TRONE = “1”)
1 : “H” output mode (valid in TRONE = “1”)
0
2
TrON output enable bit
0 : TrON port output disabled (Hi-Z state)
1 : TrON port output enabled
0
3
USB reference voltage
control bit
0 : Normal mode (valid in VREFE = “1”)
1 : Low current mode (valid in VREFE = “1”)
0
4
USB reference voltage
enable bit
0 : USB reference voltage circuit operation disabled
1 : USB reference voltage circuit operation enabled
0
5
USB difference input
enable bit
0 : Upstream-port difference input circuit operation disabled
1 : Upstream--port difference input circuit operation enabled
0
6
USB clock select bit
0 : External oscillating clock f(XIN)
1 : PLL circuit output clock fVCO
0
7
USB module operation
enable bit
0 : USB module reset
1 : USB module operation enabled
0
Fig. 2.11.2 Structure of USB control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Function
0 : Returning to BUS idle state by writing “1” first
and then “0”. (Remote wakeup signal)
1 : K-state output
page 89 of 111
0
RW
APPLICATION
38K0 Group
2.11 Clock generating circuit
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 1
CPU mode register
(CPUM: address 3B16)
B
0
Processor mode bits
1
At reset R W
Function
Name
b1 b0
0
0 0 : Single-chip mode
0 1 : Not available
1 0 : Not available
1 1 : Not available
0 : 0 page
1 : 1 page
*
2
Stack page selection bit
3
Fix this bit to “1”.
1
4
Fix this bit to “0”.
0
5
System clock selection bit
0 : Main clock f(XIN)
1 : fSYN
6
System clock division ratio
selection bits
b7 b6
7
0
0
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
0
*: The initial value of bit 1 depends on the CNVss level.
Fig. 2.11.3 Structure of CPU mode register
PLL control register
b7 b6 b5 b4 b3 b2 b1 b0
PLL control register (PLLCON)
[Address : 0FF816]
Name
B
Function
0 Nothing is arranged for these bit. These are write disabled bits.
1 When these bits are read out, the contents are “0”.
2
3 USB clock division b4 b3
ratio selection bits 0 0 : Divided by 8 (fSYN = fUSB/8)
0 1 : Divided by 6 (fSYN = fUSB/6)
4
1 0 : Divided by 4 (fSYN = fUSB/4)
1 1 : Not selected
5
6
7
PLL operation mode b6 b5
0 0 : Not multiplied (fVCO = fXIN)
selection bits
0 1 : Double (fVCO = fXIN ✕ 2)
1 0 : Quadruple (fVCO = fXIN ✕ 4)
1 1 : Multiplied by 8 (fVCO = fXIN ✕ 8)
PLL enable bit
0 : Disabled
1 : Enabled
Fig. 2.11.4 Structure of PLL control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 90 of 111
At reset
0
0
0
0
RW
APPLICATION
38K0 Group
2.11 Clock generating circuit
2.11.3 Oscillation control
Either can be selected as an internal system clock between the following two by system clock selection
bit.
● Main clock f(X IN)
● fSYN (f USB division clock)
Any one can be selected as an internal clock φ among the following four by system clock division ratio
selection bits.
● f(X IN) or f SYN/8 (8-divide mode)
● f(X IN) or f SYN/4 (4-divide mode)
● f(X IN) or f SYN/2 (2-divide mode)
● f(X IN) or f SYN (Through mode)
(1) Generation of internal clock f(φ
φ ) using main clock f(X IN)
Table 2.11.1 shows the example of internal clock f(φ) generation using main clock f(X IN); Figure
2.11.5 shows the related registers setting.
Table 2.11.1 Example of internal clock f(φ
φ ) generation using main clock f(X IN)
System clock division
ratio selection bits *
0 0
0 1
6 MH Z
1 0
1 1
0 0
0 1
8 MH Z
1 0
1 1
0 0
0 1
12 MH Z
1 0
*: CPU mode register (bits 7,6)
f(φ)
System clock
0.75
1.5
3
6
1
2
4
8
1.5
3
6
Power source voltage
VCC [V]
MH Z
MH Z
MH Z
MH Z
MH Z
MH Z
MH Z
MH Z
MH Z
MH Z
MH Z
3.00 to 5.25
4.00 to 5.25
● Select main clock f(XIN) as system clock and set clock division mode
b7
0 0 1
b0
0 0
CPU mode register
(CPUM: address 3B16)
0 : Main clock f(XIN)
b7 b6
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
Fig. 2.11.5 Related registers setting
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 91 of 111
APPLICATION
38K0 Group
2.11 Clock generating circuit
φ ) using f SYN (fUSB division clock)
(2) Generation of internal clock f(φ
Table 2.11.2 shows the example of internal clock f(φ) generation using fSYN; Figure 2.11.6 shows the
related registers setting.
Table 2.11.2 Example of internal clock f(φ
φ ) generation using f SYN
fUSB
48 MH Z
USB clock division
ratio selection bits * 1
f SYN
0 0
6 MH Z
0 1
8 MH Z
1 1
12 MH Z
*1: PLL control register (bits 4,3)
*2: CPU mode register (bits 7,6)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 92 of 111
System clock division
ratio selection bits * 2
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
f(φ)
0.75
1.5
3
6
1
2
4
8
1.5
3
6
MHZ
MH Z
MH Z
MH Z
MH Z
MH Z
MH Z
MH Z
MH Z
MH Z
MH Z
Power source voltage
VCC [V]
3.00 to 5.25
4.00 to 5.25
APPLICATION
38K0 Group
2.11 Clock generating circuit
1. Select main clock f(XIN) as system clock and set clock division mode.
b7
b0
0 0
0 0 1
CPU mode register
(CPUM: address 3B16)
0 : Main clock f(XIN)
b7 b6
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
2. Select main clock f(XIN) as USB clock.
b7
b0
0
USB control register
(USBCON: address 1016)
0 : Main clock f(XIN)
3. Enable PLL circuit, and generating PLL output clock (fVCO) 48 MHZ and fSYN.
b7
1
b0
0 0 0
PLL control register
(PLLCON: address 0FF816)
b4 b3
0 0 : Divided by 8 (fSYN = fUSB/8)
0 1 : Divided by 6 (fSYN = fUSB/6)
1 0 : Divided by 4 (fSYN = fUSB/4)
1 1 : Not selected
b6 b5
0 0 : Not multiplied (fVCO = fXIN)
0 1 : Double (fVCO = fXIN ✕ 2)
1 0 : Quadruple (fVCO = fXIN ✕ 4)
1 1 : Multiplied by 8 (fVCO = fXIN ✕ 8)
1 : PLL enabled
4. Select PLL output clock (fVCO) as USB clock.
b7
b0
1
USB control register
(USBCON: address 1016)
1 : fVCO
5. Select fSYN as system clock.
b7
b0
1
CPU mode register
(CPUM: address 3B16)
1 : fSYN
Fig. 2.11.6 Related registers setting
Note: When selecting fSYN as an internal system clock, refer to “2.10 Frequency synthesizer (PLL)” for details
concerning how to generate f USB (USB clock) from f(X IN) and the notes on PLL circuit.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 93 of 111
APPLICATION
38K0 Group
2.12 Standby function
2.12 Standby function
The 38K0 group is provided with standby functions to stop the CPU by software and put the CPU into the
low-power operation.
The following two types of standby functions are available.
•Stop mode using STP instruction
•Wait mode using WIT instruction
2.12.1 Memory map
0FFB16
MISRG (MISRG)
Fig. 2.12.1 Memory map of registers related to standby function
2.12.2 Related registers
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG
(MISRG: address 0FFB16)
B
Name
0
Oscillation stabilizing time
set after STP instruction
released bit
1
2
0 : Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1 : Automatically set nothing
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are indefinite.
3
4
5
6
7
Fig. 2.12.2 Structure of MISRG
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Functions
page 94 of 111
At reset R W
0
?
APPLICATION
38K0 Group
2.12 Standby function
2.12.3 Stop mode
The stop mode is set by executing the STP instruction. In the stop mode, the oscillation of clock (XIN–XOUT)
stops and the internal clock φ stops at the “H” level. The CPU stops and peripheral units stop operating.
As a result, power dissipation is reduced.
(1) State in stop mode
Table 2.12.1 shows the state in the stop mode.
Table 2.12.1 State in stop mode
State in stop mode
Item
CPU
Stopped.
Stopped.
Internal clock φ
Stopped at “H” level.
I/O ports P0–P6
Retains the state at the STP instruction execution.
Timer
Stopped. (Timers 1, 2, X)
Oscillation
However, Timers X can be operated in the event counter mode.
Stopped.
Stopped.
Watchdog timer
Serial I/O
However, these can be operated only when an external clock
is selected.
USB function
External BUS interface
Stopped.
A/D converter
Stopped.
Stopped.
Comparator
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 95 of 111
Stopped.
APPLICATION
38K0 Group
2.12 Standby function
(2) Release of stop mode
The stop mode is released by a reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
■Restoration by reset input
The stop mode is released by holding the RESET pin to the “L” input level during the stop mode.
Oscillation is started when all ports are in the input state and the stop mode of the main clock (X INX OUT) is released.
Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation
stabilizing time) is required. The input of the RESET pin should be held at the “L” level until oscillation
stabilizes.
When the RESET pin is held at the “L” level for 16 cycles or more of X IN after the oscillation has
stabilized, the microcomputer will go to the reset state. After the input level of the RESET pin is
returned to “H”, the reset state is released in approximately 10.5 to 18.5 cycles of the X IN input.
Figure 2.12.3 shows the oscillation stabilizing time at restoration by reset input.
At release of the stop mode by reset input, the internal RAM retains its contents previous to the
reset. However, the previous contents of the CPU register and SFR are not retained.
For more details concerning reset, refer to “2.9 Reset”.
Stop mode
Oscillation
16 cycles or
stabilizing time more of XIN
Operating mode
Vcc
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
RESET
XIN
Execute Stop instruction
Fig. 2.12.3 Oscillation stabilizing time at restoration by reset input
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 96 of 111
APPLICATION
38K0 Group
2.12 Standby function
■Restoration by interrupt request
The occurrence of an interrupt request in the stop mode releases the stop mode. As a result,
oscillation is resumed. The interrupts available for restoration are:
•INT0, INT1
•CNTR0
•Serial I/O using an external clock
•Timer X using an external event count
•Key input (key-on wake-up)
•USB function (resume)
However, when using any of these interrupt requests for restoration from the stop mode, in order to
enable the selected interrupt, you must execute the STP instruction after setting the following conditions.
[Necessary register setting]
➀ Interrupt disable flag I = “0” (interrupt enabled)
➁ Timer 1 interrupt enable bit = “0” (interrupt disabled)
➂ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request
issued)
➃ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts”.
Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation
stabilizing time) is required. For restoration by an interrupt request, waiting time prior to supplying
internal clock φ to the CPU is automatically generated✽2 by Prescaler 12 and Timer 1✽1. This waiting
time is reserved as the oscillation stabilizing time on the system clock side. The supply of internal
clock φ to the CPU is started at the Timer 1 underflow.
Figure 2.12.4 shows an execution sequence example at restoration by the occurrence of an INT 0
interrupt request.
✽1: If the STP instruction is executed when the oscillation stabilizing time set after STP instruction
released bit is “0”, “FF16” and “0116” are automatically set in the Prescaler 12 counter/latch and
Timer 1 counter/latch, respectively. When the oscillation stabilizing time set after STP instruction
released bit is “1”, nothing is automatically set to either Prescaler 12 or Timer 1. For this reason,
any suitable value can be set to Prescaler 12 and Timer 1 for the oscillation stabilizing time.
✽2: Immediately after the oscillation is started, the count source is supplied to the prescaler 12 so
that a count operation is started.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 97 of 111
APPLICATION
38K0 Group
2.12 Standby function
●When restoring microcomputer from stop mode by INT0 interrupt (rising edge selected)
Stop mode
XIN
(System clock)
Oscillation stabilizing time
XIN; H
INT0 pin
512 counts
FF16
Prescaler 12 counter
0116
Timer 1 counter
INT0 interrupt request bit
Peripheral device
Operating
CPU
Operating
Operating
Stopped
Execute STP
instruction
Operating
Stopped
INT0 interrupt signal
input (INT0 interrupt
request occurs)
Oscillation start
Prescaler 12 count start
512 counts down by
prescaler 12
Start supplying internal
clock φ to CPU
Accept INT0 interrupt
request
Note: f(XIN)/16 is input as the prescaler 12 count source.
Fig. 2.12.4 Execution sequence example at restoration by occurrence of INT0 interrupt request
(3) Notes on using stop mode
■Register setting
Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the
stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP
instruction released bit is “0”)
■Clock restoration
When the main clock side is set as a system clock, the oscillation stabilizing time for approximately
8,000 cycles of the X IN input is reserved at restoration from the stop mode.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 98 of 111
APPLICATION
38K0 Group
2.12 Standby function
2.12.4 Wait mode
The wait mode is set by execution of the WIT instruction. In the wait mode, oscillation continues, but the
internal clock φ stops at the “H” level.
The CPU stops, but most of the peripheral units continue operating.
(1) State in wait mode
The continuation of oscillation permits clock supply to the peripheral units. Table 2.12.2 shows the
state in the wait mode.
Table 2.12.2 State in wait mode
State in wait mode
Item
Oscillation
Operating.
CPU
Stopped.
Internal clock φ
I/O ports P0–P6
Stopped at “H” level.
Retains the state at the WIT instruction execution.
Watchdog timer
Operating.
Operating.
Serial I/O
Operating.
USB function
Operating.
External BUS interface
A/D converter
Stopped.
Comparator
Operating.
Timer
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 99 of 111
Operating.
APPLICATION
38K0 Group
2.12 Standby function
(2) Release of wait mode
The wait mode is released by reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
In the wait mode, oscillation is continued, so an instruction can be executed immediately after the
wait mode is released.
■Restoration by reset input
The wait mode is released by holding the input level of the RESET pin at “L” in the wait mode.
Upon release of the wait mode, all ports are in the input state, and supply of the internal clock
φ to the CPU is started. To reset the microcomputer, the RESET pin should be held at an “L” level
for 16 cycles or more of XIN. The reset state is released in approximately 10.5 cycles to 18.5 cycles
of the X IN input after the input of the RESET pin is returned to the “H” level.
At release of wait mode, the internal RAM retains its contents previous to the reset. However, the
previous contents of the CPU register and SFR are not retained.
Figure 2.12.5 shows the reset input time.
For more details concerning reset, refer to “2.9 Reset”.
Operating mode
Wait mode
Vcc
16 cycles of XIN
RESET
XIN
Execute WIT instruction
Fig. 2.12.5 Reset input time
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 100 of 111
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
APPLICATION
38K0 Group
2.12 Standby function
■Restoration by interrupt request
In the wait mode, the occurrence of an interrupt request releases the wait mode and supply of the
internal clock φ to the CPU is started. At the same time, the interrupt request used for restoration
is accepted, so the interrupt processing routine is executed.
However, when using an interrupt request for restoration from the wait mode, in order to enable the
selected interrupt, you must execute the STP instruction after setting the following conditions.
[Necessary register setting]
➀ Interrupt disable flag I = “0” (interrupt enabled)
➁ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request issued)
➂ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts”.
2.12.5 Notes on stand-by function
In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O port
“undefined”.
Pull-up (connect the port to V CC) these ports through a resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values.
• When setting as an input port: Fix its input level
• When setting as an output port: Prevent current from flowing out to external
● Reason
The potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of an input port and an I/O port are “undefined”. This may cause power source current.
* 1 stand-by state :
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
page 101 of 111
APPLICATION
38K0 Group
2.13 Flash memory
2.13 Flash memory
This paragraph explains the registers setting method and the notes related to the flash memory version.
2.13.1 Overview
The functions of the flash memory version are similar to those of the mask ROM version except that the
flash memory is built-in and some of the SFR area differ from that of the mask ROM version (refer to
“2.13.2 Memory map”).
In the flash memory version, the built-in flash memory can be programmed or erased by using the following
three modes.
• CPU rewrite mode
• Parallel I/O mode
• Standard serial I/O mode
2.13.2 Memory map
38K0 group flash memory version has 32 Kbytes of built-in flash memory.
Figure 2.13.1 shows the memory map of the flash memory version.
000016
SFR area
004016
Internal RAM
area
(2 Kbyte)
RAM
083F16
084016
User ROM area
Not used
800016
0FE016
SFR area
0FFF16
100016
Not used
800016
32 Kbytes
Reserved ROM area
808016
Built-in flash memory
area
(32 Kbytes)
FFFF16
FFFF16
Boot ROM area
F00016
4 Kbytes
FFFF16
Note: Access to boot ROM area
Pararell I/O mode
CPU rewrite mode
Standard serial mode
Read/Write avilable
Read only available
Read only available
Fig. 2.13.1 Memory map of flash memory version for 38K0 Group
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 102 of 111
APPLICATION
38K0 Group
2.13 Flash memory
2.13.3 Related registers
Address
0FFE16
Flash memory control register (FMCR)
Fig. 2.13.2 Memory map of registers related to flash memory
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register
(FMCR : address 0FFE16) (Note 1)
b
Name
0 RY/BY status flag
Functions
0 : Busy (being written or
erased)
1 : Ready
At reset R W
1
0
0 : Normal mode (Software
commands invalid)
1 : CPU rewrite mode
(Software commands
acceptable)
CPU rewrite mode
0: Normal mode
0
entry flag
1: CPU rewrite mode
Flash memory reset 0: Normal operation
0
bit (Note 3)
1: Reset
User area/Boot area 0: User ROM area
0
selection bit (Note 4) 1: Boot ROM area
Undefined
Nothing is arranged for these bits. If writing,
set “0”. When these bits are read out,
Undefined
the contents are undefined.
Undefined
1 CPU rewrite mode
select bit (Note 2)
2
3
4
5
6
7
Notes 1: The contents of flash memory control register are “XXX00001” just
after reset release.
2: For this bit to be set to “1”, the user needs to write “0” and then “1”
to it in succession. If it is not this procedure, this bit will not be set to
“1”. Additionally, it is required to ensure that no interrupt will be
generated during that interval.
Use the control program in the area except the built-in flash memory
for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”.
Set this bit 3 to “0” subsequently after setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory
for write to this bit.
Fig. 2.13.3 Structure of Flash memory control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 103 of 111
APPLICATION
38K0 Group
2.13 Flash memory
2.13.4 Parallel I/O mode
In the parallel I/O mode, program/erase to the built-in flash memory can be performed by a flash programmer
(MFW-1).
The memory area of program/erase is from 0F000 16 to 0FFFF 16 (boot ROM area) or from 08000 16 to
0FFFF16 (user ROM area). Be especially careful when erasing; if the memory area is not set correctly, the
products will be damaged eternally.
Table 2.13.1 shows the setting of programmers when programming in the parallel I/O mode.
•MFW-1 provided by Sunny Giken Inc. (http://www.sunnygiken.co.jp/english/index.html)
Table 2.13.1 Setting of programmers when parallel programming
Products
Parallel adapter
M38K09F8HP/LHP
MFW-S18
M38K09F8FP/LFP
MFW-S19
Boot ROM area
User ROM area
0F00016 to 0FFFF 16
08000 16 to 0FFFF16
2.13.5 Standard serial I/O mode
Table 2.13.2 shows a pin connection example (4 wires) between the programmer (MFW-1) and the
microcomputer when programming in the standard serial I/O mode.
•MFW-1 provided by Sunny Giken Inc. (http://www.sunnygiken.co.jp/english/index.html)
Table 2.13.2 Connection example to flash programmer when serial programming (4 wires)
Function
38K0 Group flash memory version
MFW-1
MFW-1 side connector
Signal name
Pin name
Pin number
Line number
Transfer clock input
CLK
3
P4 2/E XTC/SCLK
53
Serial data input
RXD
P4 0/E XDREQ/RXD
Serial data output
TXD
10
4
51
52
BUSY
CNVSS
2
P4 3/E XA1/S RDY
54
1
8
CNVSS
____________
RESET
7
RESET
V CC (Note 2)
1
VCC, PVCC, DVCC (Note 2)
GND (Note 1)
7
Transmit/Receive enable output
VPP input
Reset input
Target board power source monitor input
GND
P4 1/E XDACK/TxD
______
8
14, 21, 22
VSS, PVSS (Note 1)
11, 20
Notes 1: When connecting a serial programmer, first connect both GNDs to the same GND level.
2: VCC power of MFW-1 is supplied from a target board. Power consumption of MFW-1 is Max. 200
mA when serial programming. Therefore, when the current capacity of target borad is short,
connect AC adapter and supply power source to MFW-1.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 104 of 111
APPLICATION
38K0 Group
2.13 Flash memory
2.13.6 CPU rewrite mode
In the CPU rewrite mode, issuing software commands through the Central Processing Unit (CPU) can
rewrite the built-in flash memory. Accordingly, the contents of the built-in flash memory can be rewritten
with the microcomputer itself mounted on board, without using the programmer.
Store the rewrite control program to the built-in flash memory in advance. The built-in flash memory cannot
be read in the CPU rewrite mode. Accordingly, after transferring the rewrite control program to the internal
RAM, execute it on the RAM.
The following commands can be used in the CPU rewrite mode: read array, read status register, clear
status register, program, erase all block, and block erase. For details concerning each command, refer to
“CHAPTER 1 Flash memory mode (CPU rewrite mode)”.
(1) CPU rewrite mode beginning/release procedures
Operation procedure in the CPU rewrite mode for the built-in flash memory is described below.
As for the control example, refer to “2.13.7 (2) Control example in the CPU rewrite mode.”
[Beginning procedure]
➀ Apply 4.50 to 5.25 V to the CNV SS/VPP pin (at selecting boot ROM area).
➁ Release reset.
➂ Set bits 6 and 7 (main clock division ratio selection bits) of the CPU mode register.
➃ After CPU rewrite mode control program is transferred to internal RAM, jump to this control
program on RAM. (The following operations are controlled by this control program).
➄ Apply 4.50 to 5.25 to the CNVSS/VPP pin (in single-chip mode).
➅ Set “1” to the CPU rewrite mode select bit (bit 1 of address 0FFE 16).
➆ Read the CPU rewrite mode entry flag (bit 2 of address 0FFE 16) to confirm that the CPU rewrite
mode is set to “1”.
➇ Flash memory operations are executed by using software commands.
Note: The following procedures are also necessary.
• Control for data which is input from the external (serial I/O etc.) and to be programmed
to the flash memory.
• Initial setting for ports, etc.
• Writing to the watchdog timer
[Release procedure]
➀ Execute the read command or set the flash memory reset bit (bit 3 of address 0FFE 16).
➁ Set the CPU rewrite mode select bit (bit 0 of address 0FFE 16) to “0”.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 105 of 111
APPLICATION
38K0 Group
2.13 Flash memory
2.13.7 Flash memory mode application examples
The control pin processing example on the system board in the standard serial I/O mode and the control
example in the CPU rewrite mode are described below.
(1) Control pin connection example on the system board in standard serial I/O mode
As shown in Figure 2.13.4, in the standard serial I/O mode, the built-in flash memory can be rewritten
with the microcomputer mounted on board. ______
Connection examples ____________
of control pins (P4 0/EXDREQ/RXD,
P4 1/EXDACK/TXD, P42/E XTC/SCLK, P43/E XA1/SRDY, P16, CNV SS, and RESET pin) in the standard serial
I/O mode are described below.
RS-232C Serial programmer
M3
M3 8K0
8K 9F8
09
F
F8 P/H
LF
P
P/
LH
P
Fig. 2.13.4 Rewrite example of built-in flash memory in standard serial I/O mode
Table 2.13.3 shows the setting condition in the standard serial I/O mode.
Table 2.13.3 Setting condition in serial I/O mode
38K0 Group flash memory version
Pin name
Pin number
Value
CNVSS/V PP (Note)
P16
7
5
4.50 to 5.25 V
VCC
P4 2/EXTC/SCLK
53
VCC
8
Edge from V SS to V CC
____________
RESET
Note: CNV SS/V PP is not V CC but a voltage when programming.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 106 of 111
APPLICATION
38K0 Group
2.13 Flash memory
➀ When control signals are not affected to user system circuit
When the control signals in the standard serial I/O mode are not used or not affected to the user
system circuit, they can be connected as shown in Figure 2.13.5.
Target board
✽1
Not used or to user system circuit
M38K09F8FP/HP
M38K09F8LFP/LHP
TXD(P41/ExDACK)
SCLK(P42/ExTC)
RXD(P40/ExDREQ)
BUSY(P43/ExA1)
(P16)
VPP(CNVSS)
✽2
RESET
DVCC
PVCC
VCC
PVSS
VSS
XIN XOUT
User reset signal (Low active)
✽1: When not used, set to input mode and pull up or pull down, or set to output mode and open.
✽2: It is necessary to apply Vcc to SCLK (P42/ExTC) pin only when reset is released in the standard serial I/O mode.
Fig. 2.13.5 Connection example in standard serial I/O mode (1)
➁ When control signals are affected to user system circuit-1
Figure 2.13.6 shows an example that the jumper switch cut-off the control signals not to supply
to the user system circuit in the standard serial I/O mode.
Target board
To user system circuit
M38K09F8FP/HP
M38K09F8LFP/LHP
TXD(P41/ExDACK)
SCLK(P42/ExTC)
RXD(P40/ExDREQ)
BUSY(P43/ExA1)
(P16)
VPP(CNVSS)
✽
RESET
DVCC
PVCC
VCC
PVSS
VSS
XIN XOUT
User reset signal (Low active)
✽: It is necessary to apply Vcc to SCLK (P42/ExTC) pin only when reset is released in the standard serial I/O mode.
Fig. 2.13.6 Connection example in standard serial I/O mode (2)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 107 of 111
APPLICATION
38K0 Group
2.13 Flash memory
➂ When control signals are affected to user system circuit-2
Figure 2.13.7 shows an example that the analog switch (74HC4066) cut-off the control signals not
to supply to the user system circuit in the standard serial I/O mode.
Target board
74HC4066
To user system circuit
M38K09F8FP/HP
M38K09F8LFP/LHP
TXD(P41/ExDACK)
SCLK(P42/ExTC)
RXD(P40/ExDREQ)
BUSY(P43/ExA1)
(P16)
✽
VPP(CNVss)
RESET
DVCC
PVCC
VCC
PVSS
VSS
XIN XOUT
User reset signal (Low active)
✽: It is necessary to apply Vcc to SCLK (P42/ExTC) pin only when reset is released in the standard serial I/O mode.
Fig. 2.13.7 Connection example in standard serial I/O mode (3)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 108 of 111
APPLICATION
38K0 Group
2.13 Flash memory
(2) Control example in CPU rewrite mode
In this example, data is received by using serial I/O, and the data is programmed to the built-in flash
memory in the CPU rewrite mode.
Figure 2.13.8 shows an example of the reprogramming system for the built-in flash memory in the
CPU rewrite mode. Figure 2.13.9 shows the CPU rewrite mode beginning/release flowchart.
M38K09F8FP/HP
M38K09F8LFP/LHP
DVCC
PVCC
VCC
P16(CE)
Clock input
BUSY output
Data input
Data output
VPP power source input
SCLK
SRDY(BUSY)
PVSS
VSS
R XD
TXD
RESET
CNVSS
(Note 1)
User reset signal
Note 1: Apply 4.50 to 5.25 V to the VPP power source.
Fig. 2.13.8 Example of rewrite system for built-in flash memory in CPU rewrite mode
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 109 of 111
APPLICATION
38K0 Group
2.13 Flash memory
START
Single-chip mode or boot mode (Note 1)
Set CPU mode register (Note 2)
Transfer CPU rewrite mode control
program to built-in RAM
Jump to transferred control program on RAM
(The following operations are controlled by
the control program on this RAM)
Set “1” to CPU rewrite mode select bit
(by writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read command or set flash
memory reset bit (by writing “0” and then “
1” in succession) (Note 3)
Set “0” to CPU rewrite mode select bit
END
Notes 1: When MCU starts in the single-chip mode, it is necessary to apply
4.50 to 5.25 V to dhe CNVss pin until confirming of the CPU
rewrite mode entry flag.
2: Set bits 6 and 7 (system clock division ratio selection bits) of the
CPU mode register (address 003B16).
3: Before releasing the CPU rewrite mode after completing erase or
program operation, always be sure to execute the read array
command or reset the flash memory.
Fig. 2.13.9 CPU rewrite mode beginning/release flowchart
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 110 of 111
APPLICATION
38K0 Group
2.13 Flash memory
2.13.8 Notes on CPU rewrite mode
(1) Operation speed
During CPU rewrite mode, set the internal clock φ 1.5 MHz or less using the system clock division
ratio selection bits (bits 6 and 7 of address 003B 16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during the CPU
rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data
of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog
timer underflow does not happen, because of watchdog timer is always clearing during program or
erase operation.
(5) Reset
Reset is always valid. In case of CNV SS = “H” when reset is released, boot mode is active. So the
program starts from the address contained in address FFFC16 and FFFD 16 in boot ROM area.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 111 of 111
THIS PAGE IS BLANK FOR REASONS OF LAYOUT.
CHAPTER 3
APPENDIX
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Electrical characteristics
Notes on use
Countermeasures against noise
List of registers
Package outline
List of instruction code
Machine instructions
SFR memory map
Pin configurations
APPENDIX
38K0 Group
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Parameter
Symbol
VCC
Power source voltage
AVCC
Analog power source voltage VCCE, VREF, PVCC, DVCC,
USBVREF
Conditions
All voltages are
based on VSS.
Output transistors
are cut off.
Ratings
Unit
–0.3 to 6.5
V
–0.3 to VCC + 0.3
V
–0.3 to VCC + 0.3
V
VI
Input voltage
P00–P07, P10–P17, P20–P27, P30–
P37, P40–P43, P50–P57, P60–P63
VI
Input voltage
RESET, XIN, CNVSS2
–0.3 to VCC + 0.3
V
VI
Input voltage
CNVSS
–0.3 to VCC + 0.3
V
–0.3 to 6.5
V
–0.5 to 3.8
V
–0.3 to VCC + 0.3
V
Mask ROM version
Flash memory version
VI
Input voltage
D0+, D0-
VO
Output voltage
P00–P07, P10–P17, P20–P27, P30–
P37, P40–P43, P50–P57, P60–P63,
XOUT
VO
Output voltage
D0+, D0-, TrON
Pd
Power dissipation
(Note)
Topr
Operating temperature
Ta = 25°C
MCU operating
In flash memory mode
(For flash memory version)
Tstg
Storage temperature
–0.5 to 3.8
V
500
mW
–20 to 85
°C
25±5
°C
–40 to 125
°C
Note: The maximum rating value depends on not only the MCU’s power dissipation but the heat consumption characteristics of the package.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 2 of 89
APPENDIX
38K0 Group
3.1 Electrical characteristics (L.Ver)
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VCC
Limits
Parameter
Power source voltage
VCC
AVCC
Analog power source voltage
AVCC
Analog power source voltage
VCCE
VREF
Analog reference voltage
VREF
VREF
Analog reference voltage
USBVREF
Unit
Min.
Typ.
Max.
System clock 12 MHz
(2-/4-/8-divide mode)
4.00
5.00
5.25
V
System clock 8 MHz
4.00
5.00
5.25
V
System clock 6 MHz
3.00
5.00
5.25
V
PVCC, DVCC
V
VCC
V
VCC
Vcc = 3.6 to 4.0 V
Vcc = 3.0 to 3.6 V
2.0
VCC
V
3.0
3.6
V
3.0
VCC
V
VSS
Power source voltage
VSS
0
AVSS
Analog power source voltage
PVSS
0
VIH
“H” input voltage
P00–P07, P20–P27, P50–P57,
P60–P63
0.8VCC
VCC
V
V
VIH
“H” input voltage
P10–P17, P30–P37, P40–P43
0.8VCCE
VCCE
V
VIH
“H” input voltage
RESET, XIN, CNVSS, CNVSS2
0.8VCC
VCC
V
VIH
“H” input voltage
D0+, D0-
2.0
3.6
V
VIL
“L” input voltage
P00–P07, P20–P27, P50–P57,
P60–P63
0
0.2VCC
V
VIL
“L” input voltage
P10–P17, P30–P37, P40–P43
0
0.2VCCE
V
VIL
“L” input voltage
RESET, XIN, CNVSS, CNVSS2
0
0.2VCC
V
VIL
“L” input voltage
D0+, D0-
0
0.8
V
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 3 of 89
V
V
APPENDIX
38K0 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.3 Recommended operating conditions (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
Typ.
Max.
Unit
∑IOH(peak)
“H” total peak output current (Note 1)
P00–P07, P20–P27, P50–P57,
P60–P63
–80
mA
∑IOH(peak)
“H” total peak output current (Note 1)
P10–P17, P30–P37, P40–P43
–80
mA
∑IOL(peak)
“L” total peak output current (Note 1)
P00–P07, P20–P27, P50–P57
80
mA
∑IOL(peak)
“L” total peak output current (Note 1)
P60–P63
80
mA
∑IOL(peak)
“L” total peak output current (Note 1)
P10–P17, P30–P37, P40–P43
80
mA
∑IOH(avg)
“H” total average output current (Note 1)
P00–P07, P20–P27, P50–P57,
P60–P63
–40
mA
∑IOH(avg)
“H” total average output current (Note 1)
P10–P17, P30–P37, P40–P43
–40
mA
∑IOL(avg)
“L” total average output current (Note 1)
P00–P07, P20–P27, P50–P57
40
mA
∑IOL(avg)
“L” total average output current (Note 1)
P60–P63
40
mA
mA
∑IOL(avg)
“L” total average output current (Note 1)
P10–P17, P30–P37, P40–P43
40
IOH(peak)
“H” peak output current (Note 2)
P00–P07, P20–P27, P50–P57,
P60–P63
–10
mA
IOH(peak)
“H” peak output current (Note 2)
P10–P17, P30–P37, P40–P43
–10
mA
mA
IOL(peak)
“L” peak output current (Note 2)
P00–P07, P20–P27, P50–P57
10
IOL(peak)
“L” peak output current (Note 2)
P60–P63
20
mA
IOL(peak)
“L” peak output current (Note 2)
P10–P17, P30–P37, P40–P43
10
mA
IOH(avg)
“H” average output current (Note 3)
P00–P07, P20–P27, P50–P57,
P60–P63
–5
mA
IOH(avg)
“H” average output current (Note 3)
P10–P17, P30–P37, P40–P43
–5
mA
IOL(avg)
“L” average output current (Note 3)
P00–P07, P20–P27, P50–P57
5
mA
IOL(avg)
“L” average output current (Note 3)
P60–P63
10
mA
IOL(avg)
“L” average output current (Note 3)
P10–P17, P30–P37, P40–P43
5
mA
f(XIN)
Main clock input oscillation frequency
Vcc = 4.00 to 5.25 V
6
12
MHz
(Note 4)
Vcc = 3.00 to 4.00 V
6
6
MHz
System clock frequency
Vcc = 4.00 to 5.25 V
6
12
MHz
Vcc = 3.00 to 4.00 V
6
6
MHz
Vcc = 4.00 to 5.25 V
8
MHz
Vcc = 3.00 to 4.00 V
6
MHz
f(XIN) or
f(SYN)
f(φ)
φ frequency
Notes 1: The total peak output current is the absolute value of the peak currents flowing through all the applicable ports. The total average output current is
the average value of the absolute value of the currents measured over 100 ms flowing through all the applicable ports.
2: The peak output current is the absolute value of the peak current flowing in each port.
3: The average output current is the average value of the absolute value of the currents measured over 100 ms.
4: The duty of oscillation frequency is 50 %. 6 MHz or 12 MHz is usable.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 4 of 89
APPENDIX
38K0 Group
3.1 Electrical characteristics (L.Ver)
3.1.3 Electrical characteristics
Table 3.1.4 Electrical characteristics (1) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
VOH
“H” output voltage
P00–P07, P20–P27, P50–P57, P60–P63
VOH
“H” output voltage
P10–P17, P30–P37, P40–P43
VOH
“H” output voltage
D0+, D0-
VOL
“L” output voltage
P00–P07, P20–P27, P50–P57
VOL
“L” output voltage
P60–P63
VOL
“L” output voltage
P10–P17, P30–P37, P40–P43
VOL
“L” output voltage
D0+, D0-
VT+–VT-
Hysteresis
CNTR0, INT0, INT1
Hysteresis
P10/DQ0–P17/DQ7, P30–P32, P33/ExINT,
P34/ExCS, P35/ExWR, P36/ExRD, P37/
ExA0, P40/ExDREQ/RxD, P41/ExDACK/
TxD, P42/ExTC/SCLK, P43/ExA1/SRDY
Hysteresis
D0+, D0Hysteresis RESET
“H” input current
P00–P07, P20–P27, P50–P57, P60–P63
“H” input current
P10–P17, P30–P37, P40–P43
“H” input current RESET, CNVSS
“H” input current XIN
“L” input current
P00–P07, P20–P27, P50–P57, P60–P63
“L” input current
P10–P17, P30–P37, P40–P43
“L” input current RESET, CNVSS, CNVSS2
“L” input current XIN
“L” input current P00–P07, P50, P52
(Pull-ups “on”)
VT+–VT-
VT+–VT
VT+–VTIIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
IIL
VRAM
RAM hold voltage
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 5 of 89
Test conditions
IOH = –10 mA
(Vcc = 4.00 to 5.25 V)
IOH = –1 mA
IOH = –10 mA (VCCE =
4.00 to 5.25 V)
IOH = –1 mA
D+ and D- pins pulldown with 0 V via a
resistor of 15 kΩ ± 5 %
IOL = 10 mA
(Vcc = 4.00 to 5.25 V)
IOL = 1 mA
IOL = 20 mA
(Vcc = 4.00 to 5.25 V)
IOL = 1 mA
IOL = 10 mA (VCCE =
4.00 to 5.25 V)
IOL = 1 mA (VCCE =
3.00 to 5.25 V)
D+ and D- pins pull-up
with 3.6 V via a resistor
of 1.5 kΩ ± 5 %
Min.
VCC–2.0
Limits
Typ.
Max.
Unit
V
VCC–1.0
VCCE–2.0
V
V
VCCE–1.0
V
2.8
0
3.6
V
2.0
V
1.0
2.0
V
V
1.0
2.0
V
1.0
V
0.3
V
V
0.6
V
0.6
V
0.25
V
0.5
VI = VCC (Pull-ups “off”)
5.0
V
µA
VI = VCCE
5.0
µA
VI = VCC
VI = VCC
VI = VSS (Pull-ups “off”)
5.0
µA
µA
4.0
–5.0
µA
VI = VSS
–5.0
µA
VI = VSS
VI = VSS
VI = VSS
(Vcc = 4.00 to 5.25 V)
VI = VSS
When clock is stopped
–5.0
µA
–120.0
µA
5.25
µA
V
–20.0
–10.0
2.00
–4.0
–60.0
µA
APPENDIX
38K0 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.5 Electrical characteristics (2) (Vcc = 3.00 to 5.25 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
ICC
Test conditions
Parameter
Power source current
(Output transistor is
isolated.)
Normal
mode
(Note 1)
Vcc = 4.00
to 5.25 V
Vcc = 3.00
to 4.00 V
Wait
mode
(Note 2)
Vcc = 3.00
to 3.60 V
Vcc = 4.00
to 5.25 V
Vcc = 3.00
to 4.00 V
Stop
mode
(Note 3)
Vcc = 4.00
to 5.25 V
Vcc = 3.00
to 5.25 V
<Test conditions>
Notes 1: Operating in single-chip mode
Clock input from XIN pin (XOUT oscillator stopped)
fUSB = 48 MHz
All USB difference-input circuits enabled
Leaving I/O pins open
Operating functions: PLL circuit, CPU, Timers
2: Operating in single-chip mode with Wait mode
Clock input from XIN pin (XOUT oscillator stopped)
fUSB = 48 MHz
All USB difference-input circuits enabled
Leaving I/O pins open
Operating functions: PLL circuit, Timers, USB receiving
Disabled functions: CPU
3: Operating in single-chip mode with Stop mode
Oscillation stopped
All USB difference-input circuits disabled
Leaving I/O pins open
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 6 of 89
f(XIN) = system clock = 12 MHz,
φ = 6 MHz,
USB reference voltage circuit enabled
f(XIN) = 12 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
f(XIN) = 6 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit enabled
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
f(XIN) = 12 MHz,
System clock = φ = 8 MHz,
USB reference voltage circuit enabled
f(XIN) = system clock = φ = 6 MHz,
USB reference voltage circuit disabled
USB reference voltage circuit enabled
Low current mode
USB reference voltage circuit disabled
Ta = 25 °C
USB reference voltage circuit disabled
Ta = 85 °C
Min.
Limits
Typ.
21.0
Max.
60
22.5
60
mA
22.0
60
mA
21.0
60
mA
35
mA
30
mA
9.0
Unit
mA
6.0
mA
2.0
mA
125.0
250
µA
µA
0.1
10
µA
APPENDIX
38K0 Group
3.1 Electrical characteristics (L.Ver)
3.1.4 A/D converter characteristics
Table 3.1.6 A/D Converter characteristics (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
Test conditions
—
Resolution
—
Linearity error
Ta = 25 °C
—
Limits
Min.
Typ.
Max.
10
Unit
Bits
±3
±1.5
LSB
LSB
mV
Differential nonlinear error
Ta = 25 °C
VOT
Zero transition voltage
VCC = VREF = 5.12 V
0
15
35
VFST
Full scale transition voltage
VCC = VREF = 5.12 V
5105
5125
5150
mV
tCONV
Conversion time
122
RLADDER
Ladder resistor
tc(XIN)
or
tc(fSYN)
kΩ
IVREF
Reference power source input current
200
µA
5
5.0
µA
35
A/D converter operating; VREF = 5.0 V
A/D converter not operating; VREF = 5.0 V
II(AD)
A/D port input current
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 7 of 89
50
150
APPENDIX
38K0 Group
3.1 Electrical characteristics (L.Ver)
3.1.5 Timing requirements
Table 3.1.7 Timing requirements (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Typ.
Max.
Unit
tW(RESET)
Reset input “L” pulse width
Min.
2
tC(XIN)
Main clock input cycle time
83
ns
tWH(XIN)
Main clock input “H” pulse width
35
ns
tWL(XIN)
Main clock input “L” pulse width
35
ns
tC(CNTR)
CNTR0 input cycle time
200
ns
tWH(CNTR)
CNTR0 input “H” pulse width
80
ns
tWL(CNTR)
CNTR0 input “L” pulse width
80
ns
tWH(INT)
INT0, INT1 input “H” pulse width
80
ns
tWL(INT)
INT0, INT1 input “L” pulse width
80
ns
tC(SCLK)
Serial I/O clock input cycle time (Note)
800
ns
tWH(SCLK)
Serial I/O clock input “H” pulse width (Note)
370
ns
tWL(SCLK)
Serial I/O clock input “L” pulse width (Note)
370
ns
tsu(RxD–SCLK)
Serial I/O input set up time
220
ns
th(SCLK–RxD)
Serial I/O input hold time
100
ns
µs
Note: These limits are the rating values in the clock synchronous mode, bit 6 of address 0FE016 = “1”. In the UART mode, bit 6 of address 0FE016 = “0”; the
rating values are set to one fourth.
Table 3.1.8 Timing requirements (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
tW(RESET)
Reset input “L” pulse width
Min.
2
tC(XIN)
Main clock input cycle time
166
ns
tWH(XIN)
Main clock input “H” pulse width
70
ns
tWL(XIN)
Main clock input “L” pulse width
70
ns
tC(CNTR)
CNTR0 input cycle time
500
ns
tWH(CNTR)
CNTR0 input “H” pulse width
230
ns
tWL(CNTR)
CNTR0 input “L” pulse width
230
ns
tWH(INT)
INT0, INT1 input “H” pulse width
230
ns
tWL(INT)
INT0, INT1 input “L” pulse width
230
ns
tC(SCLK)
Serial I/O clock input cycle time (Note)
2000
ns
Typ.
Max.
µs
tWH(SCLK)
Serial I/O clock input “H” pulse width (Note)
950
ns
tWL(SCLK)
Serial I/O clock input “L” pulse width (Note)
950
ns
tsu(RxD–SCLK)
Serial I/O input set up time
400
ns
th(SCLK–RxD)
Serial I/O input hold time
200
ns
Note: These limits are the rating values in the clock synchronous mode, bit 6 of address 0FE016 = “1”. In the UART mode, bit 6 of address 0FE016 = “0”; the
rating values are set to one fourth.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 8 of 89
APPENDIX
38K0 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.9 Timing requirements of external bus interface (EXB) (1)
(VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Typ.
Max.
Unit
tsu(S-R)
ExCS setup time for read
Min.
0
tsu(S-W)
ExCS setup time for write
0
ns
th(R-S)
ExCS hold time for read
0
ns
th(W-S)
ExCS hold time for write
0
ns
tsu(A-R)
ExA0, ExA1 setup time for read
10
ns
tsu(A-W)
ExA0, ExA1 setup time for write
10
ns
th(R-A)
ExA0, ExA1 hold time for read
0
ns
th(W-A)
ExA0, ExA1 hold time for write
0
ns
tsu(ACK-R)
ExDACK setup time for read
10
ns
tsu(ACK-W)
ExDACK setup time for write
10
ns
th(R-ACK)
ExDACK hold time for read
0
ns
th(W-ACK)
ExDACK hold time for write
0
ns
tWH(R)
Read “H” pulse width
80
ns
tWL(R)
Read “L” pulse width
80
ns
tWH(W)
Write “H” pulse width
80
ns
tWL(W)
Write “L” pulse width
80
ns
ns
tWH(ACK)
ExDACK “H” pulse width
120
ns
tWL(ACK)
ExDACK “L” pulse width
120
ns
tsu(D-W)
Data input setup time before write
40
ns
th(W-D)
Data input hold time after write
0
ns
tsu(D-ACK)
Data input setup time before ExDACK
60
ns
th(ACK-W)
Data input hold time after ExDACK
5
ns
tC(φ)
CPU clock cycle time
125
ns
tW(cycle)
Burst mode access cycle time
USB function not operating
tC(φ)•3+10
ns
USB function operating
tC(φ)•5+10
ns
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 9 of 89
APPENDIX
38K0 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.10 Timing requirements of external bus interface (EXB) (2)
(VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Typ.
Max.
Unit
tsu(S-R)
ExCS setup time for read
Min.
0
tsu(S-W)
ExCS setup time for write
0
ns
th(R-S)
ExCS hold time for read
0
ns
th(W-S)
ExCS hold time for write
0
ns
tsu(A-R)
ExA0, ExA1 setup time for read
30
ns
tsu(A-W)
ExA0, ExA1 setup time for write
30
ns
th(R-A)
ExA0, ExA1 hold time for read
0
ns
th(W-A)
ExA0, ExA1 hold time for write
0
ns
tsu(ACK-R)
ExDACK setup time for read
30
ns
tsu(ACK-W)
ExDACK setup time for write
30
ns
th(R-ACK)
ExDACK hold time for read
0
ns
th(W-ACK)
ExDACK hold time for write
0
ns
ns
tWH(R)
Read “H” pulse width
120
ns
tWL(R)
Read “L” pulse width
120
ns
tWH(W)
Write “H” pulse width
120
ns
tWL(W)
Write “L” pulse width
120
ns
tWH(ACK)
ExDACK “H” pulse width
160
ns
tWL(ACK)
ExDACK “L” pulse width
160
ns
tsu(D-W)
Data input setup time before write
60
ns
th(W-D)
Data input hold time after write
0
ns
tsu(D-ACK)
Data input setup time before ExDACK
80
ns
th(ACK-W)
Data input hold time after ExDACK
10
ns
tC(φ)
CPU clock cycle time
166
ns
tW(cycle)
Burst mode access cycle time
USB function not operating
tC(φ)•3+30
ns
USB function operating
tC(φ)•5+30
ns
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 10 of 89
APPENDIX
38K0 Group
3.1 Electrical characteristics (L.Ver)
3.1.6 Switching characteristics
Table 3.1.11 Switching characteristics (1) (VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
ns
tWH(SCLK)
Serial I/O clock output “H” pulse width
tC(SCLK)/2–30
tWL(SCLK)
Serial I/O clock output “L” pulse width
tC(SCLK)/2–30
td(SCLK–TxD)
Serial I/O output delay time
tv(SCLK–TxD)
Serial I/O output valid time
tr(SCLK)
Serial I/O clock output rising time
30
ns
tf(SCLK)
Serial I/O clock output falling time
30
ns
tr(CMOS)
CMOS output rising time (Note)
30
ns
tf(CMOS)
CMOS output falling time (Note)
30
ns
ns
140
ns
ns
–30
Notes: Pins XOUT, D0+, D0- are excluded.
Table 3.1.12 Switching characteristics (2) (VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
tWH(SCLK)
Serial I/O clock output “H” pulse width
tC(SCLK)/2–50
tWL(SCLK)
Serial I/O clock output “L” pulse width
tC(SCLK)/2–50
td(SCLK–TxD)
Serial I/O output delay time
Typ.
Max.
Unit
ns
ns
350
ns
ns
–30
tv(SCLK–TxD)
Serial I/O output valid time
tr(SCLK)
Serial I/O clock output rising time
50
ns
tf(SCLK)
Serial I/O clock output falling time
50
ns
tr(CMOS)
CMOS output rising time (Note)
50
ns
tf(CMOS)
CMOS output falling time (Note)
50
ns
Notes: Pins XOUT, D0+, D0- are excluded.
Measured output pin
100 pF
CMOS output
Fig. 3.1.1 Output switching characteristics measurement circuit
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 11 of 89
APPENDIX
38K0 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.13 Switching characteristics of external bus interface (EXB) (1)
(VCC = 4.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
Typ.
Max.
Unit
ta(R-D)
Data output enable time after read
tv(R-D)
Data output disable time after read
ta(ACK-D)
Data output enable time after ExDACK
tv(ACK-D)
Data output disable time after ExDACK
td(R-Mdis)
In cycle mode
Mch_req disable output delay time after read
tC(φ)+10
ns
td(W-Mdis)
In cycle mode
Mch_req disable output delay time after write
tC(φ)+10
ns
td(R-Men)
In cycle mode
Mch_req enable output delay time after read
tC(φ)•3+10
tC(φ)•5+10
ns
ns
td(W-Men)
In cycle mode
Mch_req enable output delay time after write
tC(φ)•3+10
tC(φ)•5+10
ns
ns
60
ns
ns
0
80
ns
ns
0
USB function not operating
USB function operating
USB function not operating
USB function operating
Table 3.1.14 Switching characteristics of external bus interface (EXB) (2)
(VCC = 3.00 to 4.00 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
Typ.
Max.
Unit
ta(R-D)
Data output enable time after read
tv(R-D)
Data output disable time after read
ta(ACK-D)
Data output enable time after ExDACK
tv(ACK-D)
Data output disable time after ExDACK
td(R-Mdis)
In cycle mode
Mch_req disable output delay time after read
tC(φ)+30
ns
td(W-Mdis)
In cycle mode
Mch_req disable output delay time after write
tC(φ)+30
ns
td(R-Men)
In cycle mode
Mch_req enable output delay time after read
tC(φ)•3+30
tC(φ)•5+30
ns
ns
tC(φ)•3+30
tC(φ)•5+30
ns
ns
td(W-Men)
In cycle mode
Mch_req enable output delay time after write
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 12 of 89
80
ns
0
120
USB function operating
USB function not operating
USB function operating
ns
ns
0
USB function not operating
ns
APPENDIX
38K0 Group
3.1 Electrical characteristics (L.Ver)
Table 3.1.15 Switching characteristics (USB ports) (VCC = 3.00 to 5.25 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
Typ.
Max.
Unit
20
ns
4
20
ns
90
111.11
%
2.0
V
tfr(D+/D-)
USB full-speed output rising time
CL = 50 pF
tff(D+/D-)
USB full-speed output rising time
CL = 50 pF
tfrfm(D+/D-)
USB full-speed ports rising/falling ratio
tfr(D+/D-)/tff(D+/D-)
Vcrs(D+/D-)
USB output signal cross-over voltage
1.3
4
TrON
RL = 27 Ω
RL = 1.5 kΩ
Measured output pin
RL = 27 Ω
RL = 15 kΩ
CL
Measured output pin
RL = 15 kΩ
CL
USB port output
USB port output
Fig. 3.1.2 USB output switching characteristics measurement circuit (1) for D0-
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 13 of 89
Fig. 3.1.3 USB output switching characteristics measurement circuit (2) for D0+
APPENDIX
38K0 Group
3.1 Electrical characteristics
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8VCC
CNTR0
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
INT0/INT1
0.2VCC
tW(RESET)
RESET
0.8
VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
[Serial I/O]
tC(SCLK)
tf
SCLK
tWL(SCLK)
tsu(RxD-SCLK)
td(SCLK-TxD)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 14 of 89
th(SCLK-RxD)
0.8VCCE
0.2VCCE
RxD(at receive)
Fig. 3.1.4 Timing chart (1)
tWH(SCLK)
0.8VCCE
0.2VCCE
TxD (at transmit)
tr
tv(SCLK-TxD)
APPENDIX
38K0 Group
3.1 Electrical characteristics
● Timing chart
[ EXB <CPU channel mode> ]
< Read >
tsu(A-R)
ExA0, ExA1
th(R-A)
0.8VCC
0.2VCC
tsu(S-R)
ExCS
th(R-S)
0.2VCC
twL(R)
0.8VCC
0.2VCC
ExRD
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
ta(R-D)
tv(R-D)
< Write >
tsu(A-W)
ExA0, ExA1
th(W-A)
0.8VCC
0.2VCC
tsu(S-W)
ExCS
th(W-S)
0.2VCC
twL(W)
ExWR
0.8VCC
0.2VCC
tsu(D-W)
DQ0 to DQ7
Fig. 3.1.5 Timing chart (2)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 15 of 89
0.8VCC
0.2VCC
th(W-D)
0.8VCC
0.2VCC
APPENDIX
38K0 Group
3.1 Electrical characteristics
● Timing chart
[ EXB <Memory channel mode, Normal port function> ]
< Read >
tsu(A-R)
ExA0, ExA1
th(R-A)
0.8VCC
0.2VCC
tsu(S-R)
ExCS
th(R-S)
0.2VCC
twL(R)
0.8VCC
0.2VCC
ExRD
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
ta(R-D)
tv(R-D)
td(R-Men)
td(R-Mdis)
ExINT(Mch_req)
0.2VCC
0.2VCC
< Write >
tsu(A-W)
ExA0, ExA1
th(W-A)
0.8VCC
0.2VCC
tsu(S-W)
ExCS
th(W-S)
0.2VCC
twL(W)
ExWR
0.8VCC
0.2VCC
tsu(D-W)
DQ0 to DQ7
0.8VCC
0.2VCC
td(W-Mdis)
ExINT(Mch_req)
Fig. 3.1.6 Timing chart (3)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 16 of 89
0.2VCC
th(W-D)
0.8VCC
0.2VCC
td(W-Men)
0.2VCC
APPENDIX
38K0 Group
3.1 Electrical characteristics
● Timing chart
[ EXB <Memory channel mode, DMA interface pin function,
Read and write signals used together mode> ]
< Read >
tsu(ACK-R)
ExDACK
th(R-ACK)
0.2VCC
twL(R)
0.8VCC
0.2VCC
ExRD
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
ta(R-D)
tv(R-D)
td(R-Mdis)
td(R-Men)
ExDREQ(Mch_req)
0.2VCC
0.2VCC
< Write >
tsu(ACK-W)
ExDACK
th(W-ACK)
0.2VCC
twL(W)
ExWR
0.8VCC
0.2VCC
tsu(D-W)
DQ0 to DQ7
0.8VCC
0.2VCC
td(W-Mdis)
ExDREQ(Mch_req)
Fig. 3.1.7 Timing chart (4)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 17 of 89
0.2VCC
th(W-D)
0.8VCC
0.2VCC
td(W-Men)
0.2VCC
APPENDIX
38K0 Group
3.1 Electrical characteristics
● Timing chart
[ EXB <Memory channel mode, DMA interface pin function,
Read and write signals not required mode> ]
< Read >
twL(ACK)
ExDACK
DQ0 to DQ7
0.8VCC
0.2VCC
0.8VCC
0.2VCC
0.8VCC
0.2VCC
ta(ACK-D)
tv(ACK-D)
td(ACK-Mdis)
ExDREQ(Mch_req)
td(ACK-Men)
0.2VCC
0.2VCC
twL(ACK)
< Write >
ExDACK
0.8VCC
0.2VCC
tsu(D-ACK)
DQ0 to DQ7
ExDREQ(Mch_req)
Fig. 3.1.8 Timing chart (5)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 18 of 89
th(ACK-D)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
td(ACK-Mdis)
td(ACK-Men)
0.2VCC
0.2VCC
APPENDIX
38K0 Group
3.1 Electrical characteristics
● Timing chart
[ EXB <Memory channel mode, Burst transfer> ]
< Read >
ExDACK
twL(R) twH(R)
ExRD
0.8VCC
0.2VCC
tw(cycle)
DQ0 to DQ7
ta(R-D)
tv(R-D)
td(R-Mdis)
ExDREQ(Mch_req)
0.2VCC
< Write >
ExDACK
twL(W) twH(W)
ExWR
0.8VCC
0.2VCC
tw(cycle)
DQ0 to DQ7
tsu(D-W)
th(W-D)
td(W-Mdis)
ExDREQ(Mch_req)
Fig. 3.1.9 Timing chart (6)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 19 of 89
0.2VCC
APPENDIX
38K0 Group
3.2 Notes on use
3.2 Notes on use
3.2.1 Notes on input and output ports
(1) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction ✽1, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
•As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after bit managing.
•As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
✽1
Bit managing instructions: SEB and CLB instructions
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 20 of 89
APPENDIX
38K0 Group
3.2 Notes on use
3.2.2 Termination of unused pins
(1) Terminate unused pins
➀ I/O ports :
• Set the I/O ports for the input mode and connect them to V CC or VSS through each resistor of
1 kΩ to 10 kΩ.
Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination shown
on the above.
➁ I/O ports :
When setting for the input mode, do not connect to V CC or V SS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or V SS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to V CC or V SS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 21 of 89
APPENDIX
38K0 Group
3.2 Notes on use
3.2.3 Notes on interrupts
(1) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
•Interrupt edge selection register (address 0FF3 16)
•Timer X mode register (address 23 16)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit (active edge switch
bit) or the interrupt (source) select bit to “1”.
↓
NOP (one or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1”
(enabled).
Fig. 3.2.1 Sequence of changing relevant register
■ Reason
When setting the following, the interrupt request bit may be set to “1”.
•When setting external interrupt active edge
Concerned register: Interrupt edge selection register (address 0FF3 16)
Timer X mode register (address 2316)
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 22 of 89
APPENDIX
38K0 Group
3.2 Notes on use
(2) Check of interrupt request bit
● When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one
or more instructions before executing the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.2.2 Sequence of check of interrupt request bit
■ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
3.2.4 Notes on timer
● If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
● When switching the count source by the timer 12 and X count source selection bits, the value of
timer count is altered in unconsiderable amount owing to generating of thin pulses in the count
input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 23 of 89
APPENDIX
38K0 Group
3.2 Notes on use
3.2.5 Notes on serial I/O
(1) Notes when selecting clock synchronous serial I/O (Serial I/O)
➀ Stop of transmission operation
Clear the serial I/O enable bit and the transmit enable bit to “0” (Serial I/O and transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (Serial
I/O disabled).
➂ Stop of transmit/receive operation
Clear the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive
disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O enable bit to “0”
(Serial I/O disabled) (refer to (1) ➀).
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 24 of 89
APPENDIX
38K0 Group
3.2 Notes on use
(2) Notes when selecting clock asynchronous serial I/O (Serial I/O)
➀ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in
this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not
output). When data is written to the transmit buffer register in this state, data starts to be shifted
to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during
internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3) SRDY output of reception side (Serial I/O)
When signals are output from the S RDY pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/O control register again (Serial I/O)
Set the serial I/O control register again after the transmission and the reception circuits are reset by
clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
↓
Set both the transmit enable bit (TE) and
the receive enable bit (RE), or one of
them to “1”
Can be set with the LDM instruction at the same time
Fig. 3.2.3 Sequence of setting serial I/O control register again
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 25 of 89
APPENDIX
38K0 Group
3.2 Notes on use
(5) Data transmission control with referring to transmit shift register completion flag (Serial I/O)
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected (Serial I/O)
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the S CLK input level. Also, write the transmit data to the transmit buffer
register (serial I/O shift register) at “H” of the S CLK input level.
(7) Transmit interrupt request when transmit enable bit is set (Serial I/O)
When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown
in the following sequence.
➀ Set the interrupt enable bit to “0” (disabled) with CLB instruction.
➁ Prepare serial I/O for transmission/reception.
➂ Set the interrupt request bit to “0” with CLB instruction after 1 or more instruction has been
executed.
➃ Set the interrupt enable bit to “1” (enabled).
● Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”. The interrupt request is generated and the transmission
interrupt bit is set regardless of which of the two timings listed below is selected as the timing for
the transmission interrupt to be generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
3.2.6 Notes on USB function
(1) Port pins (D0+, D0-) treatment
•The USB specification requires a driver-impedance 28 to 44 Ω. In order to meet the USB specification
impedance requirements, connect a resistor (27 W recommended) in series to the USB port pins.
In addition, in order to reduce the ringing and control the falling/rising timing and a crossover point,
connect a capacitor between the USB port pins and the Vss pin if necessary.
The values and structure of those peripheral elements depend on the impedance characteristics
and the layout of the printed circuit board. Accordingly, evaluate your system and observe waveforms
before actual use and decide use of elements and the values of resistors and capacitors.
•Make sure the USB D+/D- lines do not cross any other wires. Keep a large GND area to protect the
USB lines. Also, make sure you use a USB specification compliant connecter for the connection.
(2) USBV REF pin treatment (Noise Elimination)
•Connect a capacitor between the USBVREF pin and the Vss pin. The capacitor should have a 2.2 µF
capacitor (electrolytic capacitor) and a 0.1 µF capacitor (ceramic type capacitor) connected in parallel.
•In Vcc = 3.0 to 3.6 V operation, connect the USBV REF pin directly to the Vcc pin in order to supply
power to the USB port circuit. In addition, you will need to disable the built-in USB reference voltage
circuit in this operation (set bit 4 of the USB control register to “0”.) If you are using the bus powered
supply in this condition, the DC-DC converter must be placed outside the MCU.
•In Vcc = 4.00 to 5.25 V operation, do not connect the external DC-DC converter to the USBVREF pin.
Use the built-in USB reference voltage circuit.
(3) USB Communication
•In applications requiring high-reliability, we recommend providing the system with protective measures
such as USB function initialization by software or USB reset by the host to prevent USB communication
from being terminated unexpectedly, for example due to external causes such as noise.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 26 of 89
APPENDIX
38K0 Group
3.2 Notes on use
3.2.7 Notes on A/D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion precision to be worse.
(2) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A/D conversion.
• f(X IN ) is 500 kHz or more
• Do not execute the STP instruction
3.2.8 Notes on watchdog timer
●Make sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog
timer keeps counting during that term.
●When the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program
____________
3.2.9 Notes on RESET pin
Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
3.2.10 Notes on PLL
●6 MH Z or 12 MH Z external oscillator can be connected as an input reference clock (f(X IN)). When using
the frequency synthesized clock function, we recommend using the fastest frequency possible of f(X IN)
as an input clock reference for the PLL.
●When enabling PLL operation from PLL disabled status (disabled when reset), set the USB clock select
bit of USBCON to “0” (f(XIN)) to operate with the main clock (f(X IN)).
●When supplying f VCO to the USB block after setting PLL operation enable bit to “1” (PLL enabled), wait
for the oscillation stable time (1 ms or less) of PLL to avoid any instability caused by the clock, then set
USB clock select bit to “1” (USB clock).
●When selecting f SYN as an internal system clock, f USB must be 48 MHz.
●When selecting f SYN as an internal system clock, change the system clock selection bit to main clock
(f(XIN)) before executing STP instruction. It is because the following are needed for the low-power consumption:
•f USB must be stopped by disabling PLL operation in Stop mode.
•The taimer 1 for waiting oscillation stabilization when returning from Stop mode will require the input
count source.
.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 27 of 89
APPENDIX
38K0 Group
3.2 Notes on use
3.2.11 Notes on stand-by function
(1) Notes on using stop mode
■Register setting
Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the
stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP
instruction released bit is “0”)
■Clock restoration
When the main clock side is set as a system clock, the oscillation stabilizing time for approximately
8,000 cycles of the X IN input is reserved at restoration from the stop mode.
(2) Notes on stand-by function
In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”.
Pull-up (connect the port to V CC) these ports through a resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values.
• When setting as an input port: Fix its input level
• When setting as an output port: Prevent current from flowing out to external
● Reason
The potential which is input to the input buffer in a microcomputer is unstable in the state that input
levels of an input port and an I/O port are “undefined”. This may cause power source current.
* 1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
3.2.12 Notes on CPU rewrite mode
(1) Operation speed
During CPU rewrite mode, set the internal clock φ 1.5 MHz or less using the system clock division
ratio selection bits (bits 6 and 7 of address 003B 16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during the CPU
rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data
of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog
timer underflow does not happen, because of watchdog timer is always clearing during program or
erase operation.
(5) Reset
Reset is always valid. In case of CNV SS = “H” when reset is released, boot mode is active. So the
program starts from the address contained in address FFFC16 and FFFD 16 in boot ROM area.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 28 of 89
APPENDIX
38K0 Group
3.2 Notes on use
3.2.13 Notes on programming
(1) Processor status register
➀ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
● Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.2.4 Initialization of processor status register
➁ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
↓
NOP
Fig. 3.2.5 Sequence of PLP instruction execution
(S)
(S)+1
Stored PS
Fig. 3.2.6 Stack memory contents after PHP
instruction execution
(2) BRK instruction
➀ Interrupt priority level
When the BRK instruction is executed with the following conditions satisfied, the interrupt execution
is started from the address of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 29 of 89
APPENDIX
38K0 Group
3.2 Notes on use
(3) Decimal calculations
➀ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
➁ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.2.7 Status flag at decimal calculations
(4) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a page
as an indirect address.
(5) Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
(6) Ports
The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
(7) Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock f by the number
of cycles needed to execute an instruction.
The number of cycles required to execute an instruction is shown in the list of machine instructions.
The frequency of the internal clock f is half of the X IN frequency in high-speed mode.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 30 of 89
APPENDIX
38K0 Group
3.2 Notes on use
3.2.14 Notes on flash memory version
The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has
the multiplexed function to be a programmable power source pin (V PP pin) as well.
To improve the noise reduction, connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10
kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss
pin or Vcc pin via a resistor.
3.2.15 Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation
between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes.
When manufacturing an application system with the Flash Memory version and then switching to use of the
Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM
version.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 31 of 89
APPENDIX
38K0 Group
3.3 Countermeasures against noise
3.3 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.3.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Package
Select the smallest possible package to make the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
DIP
SDIP
SOP
QFP
Fig. 3.3.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
Reset
circuit
VSS
N.G.
O.K.
Fig. 3.3.2 Wiring for the RESET pin
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 32 of 89
RESET
VSS
APPENDIX
38K0 Group
3.3 Countermeasures against noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is
connected to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the V SS
level of a microcomputer and the V SS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
XIN
XOUT
VSS
XIN
XOUT
VSS
O.K.
N.G.
Fig. 3.3.3 Wiring for clock I/O pins
(4) Wiring to CNVSS pin
Connect the CNV SS pin to the V SS pin with the shortest possible wiring.
● Reason
The processor mode of a microcomputer is influenced by a potential at the CNV SS pin. If a
potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may
become unstable. This may cause a microcomputer malfunction or a program runaway.
Noise
CNVSS
CNVSS
VSS
VSS
N.G.
Fig. 3.3.4 Wiring for CNV SS pin
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 33 of 89
O.K.
APPENDIX
38K0 Group
3.3 Countermeasures against noise
(5) Wiring to VPP pin of Flash memory version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the
VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the
VSS pin the shortest possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The V PP pin of the flash memory version is the power source input pin for the built-in flash
memory. When programming in the built-in flash memory, the impedance of the V PP pin is low to
allow the electric current for writing flow into the flash memory. Because of this, noise can enter
easily. If noise enters the V PP pin, abnormal instruction codes or data are read from the built-in
flash memory, which may cause a program runaway.
Approximately
5kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig. 3.3.5 Wiring for the VPP pin of the flash memory version
3.3.2 Connection of bypass capacitor across V SS line and V CC line
Connect an approximately 0.1 µ F bypass capacitor across the V SS line and the V CC line as follows:
• Connect a bypass capacitor across the V SS pin and the V CC pin at equal length.
• Connect a bypass capacitor across the V SS pin and the V CC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for V SS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the V SS pin and the V CC pin.
VCC
VCC
VSS
VSS
N.G.
O.K.
Fig. 3.3.6 Bypass capacitor across the V SS line and the VCC line
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 34 of 89
APPENDIX
38K0 Group
3.3 Countermeasures against noise
3.3.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the V SS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from
the V SS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.3.7 Analog signal line and a resistor and a capacitor
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 35 of 89
APPENDIX
38K0 Group
3.3 Countermeasures against noise
3.3.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig. 3.3.8 Wiring for a large current signal line
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
Do not cross
CNTR
XIN
XOUT
VSS
Fig. 3.3.9 Wiring of RESET pin
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 36 of 89
APPENDIX
38K0 Group
3.3 Countermeasures against noise
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the V SS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides,
separate this V SS pattern from other V SS patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.3.10 V SS pattern on the underside of an oscillator
3.3.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
O.K.
Noise
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.3.11 Setup for I/O ports
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 37 of 89
APPENDIX
38K0 Group
3.3 Countermeasures against noise
3.3.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
≤0
(SWDT)
=N?
N
Interrupt processing
routine errors
>0
RTI
Return
Main routine
errors
Fig. 3.3.12 Watchdog timer by software
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 38 of 89
APPENDIX
38K0 Group
3.4 List of registers
3.4 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6) (Note)
[Address : 0016, 0216, 0416, 0616, 0816, 0A16, 0C16]
B
0 Port Pi0
Function
Name
●
1 Port Pi1
●
2 Port Pi2
3 Port Pi3
In output mode
Write Port latch
Read
In input mode
Write : Port latch
Read : Value of pins
At reset
R W
?
?
?
?
4 Port Pi4
?
5 Port Pi5
?
6 Port Pi6
?
7 Port Pi7
?
Note: Since the following ports are not allocated, the corrrsponding bits can not be used.
• P44 to P47
• P64 to P67
Fig. 3.4.1 Structure of Port Pi
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6) (Note)
[Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16]
B
Name
0 Port Pi direction register
1
2
3
4
5
6
7
Function
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
Note: Since the following ports are not allocated, the corrrsponding bits can not be used.
• P44 to P47
• P64 to P67
Fig. 3.4.2 Structure of Port Pi direction register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 39 of 89
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
USB control register (USBCON) [address 001016]
Bit symbol
WKUP
TRONCON
TRONE
VREFCON
VREFE
USBDIFE
UCLKCON
USBE
At reset
R W
H/W S/W
0 : Returning to BUS idle state by writing “1” first and 0
Remote wakeup bit
– O O
then “0”. (Remote wakeup signal)
1 : K-state output
0 : “L” output mode (valid in TRONE = “1”)
TrON output control bit
0
– O O
1 : “H” output mode (valid in TRONE = “1”)
0 : TrON port output disabled (Hi-Z state)
TrON output enable bit
0
– O O
1 : TrON port output enabled
USB reference voltage control bit 0 : Normal mode (valid in VREFE = “1”)
0
– O O
1 : Low current mode (valid in VREFE = “1”)
USB reference voltage enable bit 0 : USB reference voltage circuit operation disabled
0
– O O
1 : USB reference voltage circuit operation enabled
USB difference input enable bit 0 : Upstream-port difference input circuit operation disabled
0
– O O
1 : Upstream--port difference input circuit operation enabled
0 : External oscillating clock f(XIN)
USB clock select bit
0
– O O
1 : PLL circuit output clock fVCO
USB module operation enable bit 0 : USB module reset
0
– O O
1 : USB module operation enabled
Bit name
Function
–: State remaining
Fig. 3.4.3 Structure of USB control register
b0
b7
0
0 0
0 0 0
USB function enable register (USBAE) [address 001116]
0
Bit symbol
Function
Bit name
AD0E
USB function enable bit
b7:b1
Not used
0: USB function address register invalidated
1: USB function address register validated
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.4 Structure of USB function enable register
b7
0
b0
USB function address register (USBA0) [address 001216]
Bit symbol
Function
Bit name
USBADD0
[6:0]
USB function address bit
b7
Not used
In AD0E = “0”, this value changes after writing.
In AD0E = “1”, this value changes after completion of
SET_ADDRESS control transferring.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
0 O O
–
–
O O
–: State remaining
Fig. 3.4.5 Structure of USB function address register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 40 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
Frame number register Low (FNUML) [address 001416]
Bit symbol
FNUM
[7:0]
Function
Bit name
Frame number low bit
The frame number is updated at SOF reception.
At reset
R W
H/W S/W
InIn- O ✕
definite definite
Fig. 3.4.6 Structure of Frame number register Low
b0
b7
0
0 0
Frame number register High (FNUMH) [address 001516]
0 0
Bit symbol
FNUM
[10:8]
b7:b3
Function
Bit name
Frame number high bit
The frame number is updated at SOF reception.
Not used
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
InIn- O ✕
definite definite
–
–
O O
–: State remaining
Fig. 3.4.7 Structure of Frame number register High
b0
b7
0
0
USB interrupt source enable register (USBICON) [address 001616]
Bit symbol
b5:b4
USB function/Endpoint 0 interrupt
enable bit
USB function/Endpoint 1 interrupt
enable bit
USB function/Endpoint 2 interrupt
enable bit
USB function/Endpoint 3 interrupt
enable bit
Not used
SUSE
Suspend interrupt enable bit
RSME
Resume interrupt enable bit
EP00E
EP01E
EP02E
EP03E
Function
Bit name
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Write “0” when writing.
“0” is read when reading.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
0
0
O O
–
–
O O
0
0
O O
0
0
O O
–: State remaining
Fig. 3.4.8 Structure of USB interrupt source enable register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 41 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0
USB interrupt source register (USBIREQ) [address 001716]
0
Bit symbol
Bit name
EP00
USB function/Endpoint 0
interrupt bit
EP01
USB function/Endpoint 1
interrupt bit
EP02
USB function/Endpoint 2
interrupt bit
EP03
USB function/Endpoint 3
interrupt bit
b5:b4
Not used
SUS
Suspend interrupt bit
RSM
Resume interrupt bit
At reset
R W
H/W S/W
This bit is set to “1” when any one of EP00 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP00 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP01 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP01 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP02 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP02 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP03 interrupt 0
0 O ✕
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP03 interrupt
source register to “0016”.
Writing to this bit causes no state change.
Write “0” when writing.
–
– O O
“0” is read when reading.
0 : No interrupt request issued
0
0 O O
1 : Interrupt request issued
This bit is set to “1” when detecting 3 ms or more of Jstate, using USB clock (fUSB) at 48 MHz.
“0” can be set by software, but “1” cannot be set.
This bit is set to “1” when the USB bus state changes 0
0 O ✕
from J-state to K-state or SE0 in the resume interrupt
enable bit = “1”. It is also “1” in the condition of internal
clock stopped.
This bit is cleared to “0” by clearing the resume
interrupt enable bit.
Writing to this bit causes no state change.
Function
–: State remaining
Fig. 3.4.9 Structure of USB interrupt source register
b0
b7
0
0 0
0 0
0
Endpoint index register (USBINDEX) [address 001816]
Bit symbol
Bit name
EPIDX [1:0] Endpoint index bit
b7:b3
Not used
Function
b1 b0
0 0 : Endpoint 0
0 1 : Endpoint 1
1 0 : Endpoint 2
1 1 : Endpoint 3
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.10 Structure of Endpoint index register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 42 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0
0
0
0 0
EP00 stage register (EP00STG) [address 001916]
0 0
Bit symbol
Function
Bit name
SETUP00
SETUP packet detection bit
b7:b1
Not used
This bit is set to “1” at reception of SETUP packet.
Writing “0” to this bit clears this bit if the next SETUP
token does not occur.
Writing “1” to this bit causes no state change of the
status flags.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
1
1 O O
–
–
O O
–: State remaining
Fig. 3.4.11 Structure of EP00 stage register
b7
b0
EP01 set register (EP01CFG) [address 001916]
Bit symbol
BSIZ01
[1:0]
DBLB01
SQCL01
ITMD01
DIR01
TYP01
[1:0]
At reset
R W
H/W S/W
Double buffer beginning address set In double buffer mode set the beginning address of 0
– O O
buffer 1 area, using a relative value for the beginning
bit
address of buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
0 : Single buffer mode
Buffer mode select bit
0
– O O
1 : Double buffer mode
0 : Toggle bit clear disabled
Sequence toggle bit clear bit
0
– O O
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Interrupt toggle mode select bit 0 : Normal mode
0
– O O
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0 : OUT (Data is received from the host.)
Transfer direction bit
0
– O O
1 : IN (Data is transmitted to the host.)
b7b6
Transfer type bite
0
– O O
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
Bit name
Function
–: State remaining
Fig. 3.4.12 Structure of EP01 set register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 43 of 89
APPENDIX
38K0 Group
b7
3.4 List of registers
b0
EP02 set register (EP02CFG) [address 001916]
Bit symbol
BSIZ02
[1:0]
DBLB02
SQCL02
ITMD02
DIR02
TYP02
[1:0]
At reset
R W
H/W S/W
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1 0
– O O
area, using a relative value for the beginning address of
bit
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
0 : Single buffer mode
Buffer mode select bit
0
– O O
1 : Double buffer mode
0 : Toggle bit clear disabled
Sequence toggle bit clear bit
0
– O O
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Interrupt toggle mode select bit 0 : Normal mode
0
– O O
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0 : OUT (Data is received from the host.)
Transfer direction bit
0
– O O
1 : IN (Data is transmitted to the host.)
b7b6
Transfer type bite
0
– O O
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
Bit name
Function
–: State remaining
Fig. 3.4.13 Structure of EP02 set register
b7
b0
EP03 set register (EP03CFG) [address 001916]
Bit symbol
BSIZ03
[1:0]
DBLB03
SQCL03
ITMD03
DIR03
TYP03
[1:0]
At reset
R W
H/W S/W
Double buffer beginning address set In double buffer mode set the beginning address of buffer 1 0
– O O
area, using a relative value for the beginning address of
bit
buffer 0.
b1b0
0 0 = 8 bytes
0 1 = 16 bytes
1 0 = 64 bytes
1 1 = 128 bytes
0 : Single buffer mode
Buffer mode select bit
0
– O O
1 : Double buffer mode
0 : Toggle bit clear disabled
Sequence toggle bit clear bit
0
– O O
1 : Writing “1” clears the toggle bit and DATA0 is used
as the next data PID.
“0” is always read when reading.
Interrupt toggle mode select bit 0 : Normal mode
0
– O O
1 : Continuous toggle mode (valid at Interrupt IN transfer)
0 : OUT (Data is received from the host.)
Transfer direction bit
0
– O O
1 : IN (Data is transmitted to the host.)
b7b6
Transfer type bit
0
– O O
0 0 : Transfer disabled
0 1 : Bulk transfer
1 0 : Interrupt transfer
1 1 : Isochronous transfer
Bit name
Function
–: State remaining
Fig. 3.4.14 Structure of EP03 set register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 44 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0
0
0
0 0
EP00 control register 1 (EP00CON1) [address 001A16]
0
Bit symbol
Function
Bit name
PID00 [1:0]
Response PID bit
b7:b2
Not used
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of control transfer error:
B1 is set to “1” by the hardware.
At reception of SETUP token:
B1 and b0 are cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.15 Structure of EP00 control register 1
b0
b7
0 0 0
0
0
EP01 control register 1 (EP01CON1) [address 001A16]
0
Bit symbol
Function
Bit name
PID01
[1:0]
Response PID bit
b7:b2
Not used
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.16 Structure of EP01 control register 1
b0
b7
0 0
0
0
0 0
EP02 control register 1 (EP02CON1) [address 001A16]
Bit symbol
Bit name
PID02
[1: 0]
Response PID bit
b7:b2
Not used
Function
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.17 Structure of EP02 control register 1
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 45 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0 0 0
0
0
EP03 control register 1 (EP03CON1) [address 001A16]
0
Bit symbol
Function
Bit name
PID03
[1:0]
Response PID bit
b7:b2
Not used
b1 b0
0 0 : NAK
0 1 : Automatic response (ACK, NAK, DATA0, DATA1)
1 X : STALL
At occurrence of over-max. packet size :
B1 is set to “1” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.18 Structure of EP03 control register 1
b0
b7
0
0
0 0
0 0
0
EP00 control register 2 (EP00CON2) [address 001B16]
Bit symbol
Function
Bit name
BVAL00
Buffer enable bit
b7:b1
Not used
0 : NAK transmission (SIE is disabled to read a buffer.)
1 : Transmitting/receiving data set state (SIE is possible
to read from/write to a buffer.)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.19 Structure of EP00 control register 2
b0
b7
0
0
0 0
0
0
0
EP01 control register 2 (EP01CON2) [address 001B16]
Bit symbol
Bit name
B0VAL01
Buffer 0 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
O
O
0
–
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
–
– O O
Write “0” when writing.
“0” is read when reading.
Function
–: State remaining
Fig. 3.4.20 Structure of EP01 control register 2
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 46 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0
0
0
0 0
0
EP02 control register 2 (EP02CON2) [address 001B16]
0
Bit symbol
Bit name
B0VAL02
Buffer 0 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
O
O
0
–
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
–
– O O
Write “0” when writing.
“0” is read when reading.
Function
–: State remaining
Fig. 3.4.21 Structure of EP02 control register 2
b0
b7
0
0
0
0 0
0
0
EP03 control register 2 (EP03CON2) [address 001B16]
Bit symbol
Bit name
B0VAL03
Buffer 0 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
O
O
0
–
When the selected endpoint is IN, writing “1” to this bit
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 3.4.22 Structure of EP03 control register 2
b0
b7
0
0
0 0
0 0
0
EP00 control register 3 (EP00CON3) [address 001C16]
Bit symbol
Bit name
CTENDE00 Control transfer completion
enable bit
b7:b1
Not used
Function
0 : NAK transmission in the status stage
1 : Control transfer completion enabled (SIE transmits
NULL/ACK.) (valid in PID00 = “012”)
At reception of SETUP token:
This bit is cleared to “0” by the hardware.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.23 Structure of EP00 control register 3
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 47 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0 0 0 0
EP01 control register 3 (EP01CON3) [address 001C16]
0 0 0
Bit symbol
Bit name
B1VAL01
Buffer 1 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
–
– O O
Write “0” when writing.
“0” is read when reading.
Function
–: State remaining
Fig. 3.4.24 Structure of EP01 control register 3
b0
b7
0
0
0
0 0
0
0
EP02 control register 3 (EP02CON3) [address 001C16]
Bit symbol
Bit name
B1VAL02
Buffer 1 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 3.4.25 Structure of EP02 control register 3
b0
b7
0 0 0 0
0 0 0
EP03 control register 3 (EP03CON3) [address 001C16]
Bit symbol
Bit name
B1VAL03
Buffer 1 enable bit
b7:b1
Not used
At reset
R W
H/W S/W
– O O
When the selected endpoint is IN, writing “1” to this bit 0
makes the transmitting data a set state (SIE is possible
to read).
When the selected endpoint is OUT, writing “1” to this
bit makes data reception possible (SIE is possible to
write).
In double buffer mode this bit is valid.
–
– O O
Write “0” when writing.
Function
“0” is read when reading.
–: State remaining
Fig. 3.4.26 Structure of EP03 control register 3
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 48 of 89
APPENDIX
38K0 Group
b7
0 0 0
3.4 List of registers
b0
EP00 interrupt source register (EP00REQ) [address 001D16]
Bit symbol
BRDY00
CTEND00
CTSTS00
BSRDY00
ERR00
b7:b5
Bit name
Function
0: No interrupt request issued
1: Interrupt request issued
This bit is set to “1” when the buffer is ready state
(enabled to be read/written) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 0 control 0: No interrupt request issued
transfer completion interrupt bit 1: Interrupt request issued
This bit is set to “1” when control transfer is completed
(NULL/ACK transmission in the status stage) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 0 status 0: No interrupt request issued
1: Interrupt request issued
stage transition interrupt bit
This bit is set to “1” when transition to status stage
occurs in CTENDE00 = “0” (control transfer completion
disabled) on USB function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
<Transition to status stage occurrence factor>
At transfer of control write:
When receiving IN-token in data stage (OUT)
At transfer of control read:
When receiving OUT-token in data stage (IN)
At no data transfer:
Nothing occurs.
USB function/Endpoint 0 SETUP 0: No interrupt request issued
1: Interrupt request issued
buffer ready interrupt bit
This bit is set to “1” when the exclusive buffer for
SETUP is ready state (enabled to be read) on USB
function/Endpoint 0.
“0” can be set by software, but “1” cannot be set.
0: No interrupt request issued
USB function/Endpoint 0 error
1: Interrupt request issued
interrupt bit
This bit is set to “1” when control transfer error occurs
on USB function/Endpoint 0.
This bit is cleared to “0” by the hardware when
receiving SETUP token.
“0” can be set by software, but “1” cannot be set.
Write “0” when writing.
Not used
“0” is read when reading.
USB function/Endpoint 0 buffer
ready interrupt bit
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
0
0
O O
0
0
O O
–
–
O O
–: State remaining
Fig. 3.4.27 Structure of EP00 interrupt source register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 49 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0 0 0 0
EP01 interrupt source register (EP01REQ) [address 001D16]
0
Bit symbol
B0RDY01
B1RDY01
ERR01
b7:b3
Bit name
Function
USB function/Endpoint 1 buffer 0 0: No interrupt request issued
ready interrupt bit
1: Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 1 buffer 1 0: No interrupt request issued
ready interrupt bit
1: Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 1
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 1 error
0: No interrupt request issued
interrupt bit
1: Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 1.
“0” can be set by software, but “1” cannot be set.
Not used
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
–
–
O O
Fig. 3.4.28 Structure of EP01 interrupt source register
b0
b7
0
0
0
0
0
EP02 interrupt source register (EP02REQ) [address 001D16]
Bit symbol
B0RDY02
B1RDY02
ERR02
b7 to b3
Bit name
USB function/Endpoint 2 buffer 0 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 2 buffer 1 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 2
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 2 error
0 : No interrupt request issued
interrupt bit
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 2.
“0” can be set by software, but “1” cannot be set.
Not used
Write “0” when writing.
“0” is read when reading.
Fig. 3.4.29 Structure of EP02 interrupt source register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Function
page 50 of 89
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
–
–
O O
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0 0 0 0
EP03 interrupt source register (EP03REQ) [address 001D16]
0
Bit symbol
B0RDY03
B1RDY03
ERR03
b7:b3
Function
Bit name
USB function/Endpoint 3 buffer 0 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
This bit is set to “1” when the buffer 0 is ready state
(enabled to be read/written) on USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 3 buffer 1 0 : No interrupt request issued
ready interrupt bit
1 : Interrupt request issued
In single buffer mode this bit is invalid.
This bit is set to “1” when the buffer 1 is ready state
(enabled to be read/written) on USB function/Endpoint 3
in double buffer mode.
“0” can be set by software, but “1” cannot be set.
USB function/Endpoint 3 error
0 : No interrupt request issued
interrupt bit
1 : Interrupt request issued
This bit is set to “1” when STALL response occurs on
USB function/Endpoint 3.
“0” can be set by software, but “1” cannot be set.
Not used
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
0 O O
0
0
O O
0
0
O O
–
–
O O
Fig. 3.4.30 Structure of EP03 interrupt source register
b0
b7
0
0 0
EP00 byte number register (EP00BYT) [address 001E16]
0
Bit symbol
BBYT00
[3:0]
b7:b4
At reset
R W
H/W S/W
0
— O O
Function
Bit name
Transmit/receive byte number bit OUT : The received byte number is automatically set.
IN : Set the transmitting byte number.
Write 0 when writing.
Not used
0 is read when reading.
—
—
O O
—: State remaining
Fig. 3.4.31 Structure of EP00 byte number register
b7
0
b0
EP01 byte number register 0 (EP01BYT0) [address 001E16]
Bit symbol
B0BYT01
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
Single buffer mode : The received byte number is
automatically set.
Double buffer mode : The received byte number of buffer 0
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 3.4.32 Structure of EP01 byte number register 0
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 51 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
EP02 byte number register 0 (EP02BYT0) [address 001E16]
0
Bit symbol
IN : Transmit byte number bit
B0BYT02
[6:0]
OUT : Receive byte number bit
Not used
b7
Function
Bit name
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
Single buffer mode: The received byte number is
automatically set.
Double buffer mode : The received byte number of buffer 0
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 3.4.33 Structure of EP02 byte number register 0
b7
b0
EP03 byte number register 0 (EP03BYT0) [address 001E16]
0
Bit symbol
Function
Bit name
IN : Transmit byte number bit
B0BYT03
[6:0]
OUT : Receive byte number bit
Not used
b7
Single buffer mode: Set the transmitting byte number.
Double buffer mode : Set the transmitting byte number
of buffer 0.
Single buffer mode: The received byte number is
automatically set.
Double buffer mode : The received byte number of buffer 0
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 3.4.34 Structure of EP03 byte number register 0
b7
0
b0
EP01 byte number register 1 (EP01BYT1) [address 001F16]
Bit symbol
B1BYT01
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
b7
Function
Bit name
Not used
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
Single buffer mode: These bits are invalid.
Double buffer mode : The received byte number of buffer 1
is automatically set.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O ✕
–
–
O O
–: State remaining
Fig. 3.4.35 Structure of EP01 byte number register 1
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 52 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
EP02 byte number register 1 (EP02BYT1) [address 001F16]
0
Bit symbol
IN : Transmit byte number bit
B1BYT02
[6:0]
OUT : Receive byte number bit
Not used
b7
At reset
R W
H/W S/W
0
– O O
Function
Bit name
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
Single buffer mode: These bits are invalid.
Double buffer mode : The received byte number of buffer 1
is automatically set.
Write “0” when writing.
“0” is read when reading.
0
–
O ✕
–
–
O O
–: State remaining
Fig. 3.4.36 Structure of EP02 byte number register 1
b0
b7
EP03 byte number register 1 (EP03BYT1) [address 001F16]
0
Bit symbol
B1BYT03
[6:0]
IN : Transmit byte number bit
OUT : Receive byte number bit
Not used
b7
At reset
R W
H/W S/W
0
– O O
Function
Bit name
Single buffer mode: These bits are invalid.
Double buffer mode : Set the transmitting byte number
of buffer 1.
Single buffer mode: These bits are invalid.
Double buffer mode : The received byte number of buffer 1
is automatically set.
Write “0” when writing.
“0” is read when reading.
0
–
O ✕
–
–
O O
–: State remaining
Fig. 3.4.37 Structure of EP03 byte number register 1
Prescaler 12, Prescaler X
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12) [Address : 2016]
Prescaler X (PREX) [Address : 2416]
B
Name
Function
0 •Set a count value of each prescaler.
•The value set in this register is written to both each prescaler
1 and the corresponding prescaler latch at the same time.
•When this register is read out, the count value of the corres2 ponding prescaler is read out.
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.4.38 Structure of Prescaler12, Prescaler X
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset
page 53 of 89
R W
APPENDIX
38K0 Group
3.4 List of registers
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 2116]
B
Name
Function
0 •Set a count value of timer 1.
At reset
R W
1
•The value set in this register is written to both timer 1 and timer 1
latch at the same time.
•When this register is read out, the timer 1’s count value is read
2 out.
1
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 3.4.39 Structure of Timer 1
Timer 2, Timer X
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2) [Address : 2216]
Timer X (TX) [Address : 2516]
Name
B
0 •Set a count value of each timer.
Function
•The value set in this register is written to both each timer and
each timer latch at the same time.
•When this register is read out, each timer’s count value is read
2
out.
1
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.4.40 Structure of Timer 2, Timer X
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset
page 54 of 89
R W
APPENDIX
38K0 Group
3.4 List of registers
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register (TM) [Address : 2316]
B
Function
Name
At reset
0 Timer X operating mode bits
b1 b0
0
1
0
0
1
1
0
2 CNTR0 active edge selection
bit
3 Timer X count stop bit
4
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
The function depends on the
operating mode of Timer X.
(Refer to Table 2.3.1)
0
0 : Count start
1 : Count stop
0
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are “0”.
R W
0
5
0
6
0
7
0
Fig. 3.4.41 Structure of Timer X mode register
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 2616]
B
Name
Function
0 The transmission data is written to or the receive data is read out
from this buffer register.
1 • At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read
2
out.
?
?
?
3
?
4
?
5
?
6
?
7
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 3.4.42 Structure of Transmit/Receive buffer register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset
page 55 of 89
R W
APPENDIX
38K0 Group
3.4 List of registers
Serial I/O status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O status register (SIOSTS) [Address : 2716]
B
Name
Transmit
buffer
empty flag
0
Function
At reset
R W
0 : Buffer full
1 : Buffer empty
0
✕
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
0
✕
0
✕
3 Overrun error flag (OE)
0 : No error
1 : Overrun error
0
✕
4 Parity error flag (PE)
0 : No error
1 : Parity error
0
✕
5 Framing error flag (FE)
0 : No error
1 : Framing error
0
✕
6 Summing error flag (SE)
0 : (OE) U (PE) U (FE) = 0
1 : (OE) U (PE) U (FE) = 1
0
✕
1
✕
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the contents are “1”.
Fig. 3.4.43 Structure of Serial I/O status register
b0
b7
0 0
0
0
0
EXB interrupt source enable register (EXBICON) [address 003016]
(Note)
Bit symbol
RXB_ENB
TXB_ENB
MC_ENB
b7:b3
Bit name
Function
CPU channel receive enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Receive buffer full interrupt enabled)
CPU channel transmit enable bit 0 : Operation disabled (Interrupt disabled)
1 : Operation enabled (Transmit buffer empty interrupt enabled)
0 : Operation disabled (Memory channel operation end
Memory channel operation
interrupt disabled)
enable bit
1 : Operation enabled (Memory channel operation end
interrupt disabled)
Write “0” when writing.
Not used
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
0
–
O O
–
–
O O
–: State remaining
Note: Do not set each bit simultaneously.
Fig. 3.4.44 Structure of EXB interrupt source enable register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 56 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0
0
0
0
EXB interrupt source register (EXBIREQ) [address 003116] (Note 1)
Bit symbol
Bit name
RXB_FULL
Receive buffer full bit
TXB_EMPTY Transmit buffer empty bit
MC_STS
[1:0]
(Note 2)
Memory channel status bits
b7:b4
Not used
Function
0 : Receive buffer empty
1 : Receive buffer full
0 : Transmit buffer full
1 : Transmit buffer empty
b3b2
0 0 : Memory channel operation stopped
0 1 : Memory channel being operating;
No external access
1 0 : Memory channel being operating;
External accessing
1 1 : Memory channel operation end; Memory
channel operation end interrupt generated
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
0 O –
(Note 3)
0
0
O –
(Note 4)
0
0
O –
–
–
O O
–: State remaining
Notes 1: When the the ExA1 pin control bit of external I/O configuration register is “1”, the external MCU bus can read this
register contents by setting the ExA1 pin to “H”.
2: The memory channel status bits indicate the status of memory channel. In MC_ENB = “0” these bits are always
“002”. When the memory channel operation ends, these bits are set to “112” and the memory channel operation
end interrupt is generated.
These bits can be read out during operation, so that it will show that whether the external MCU bus is accessing
or not.
3: This bit is cleared to “0” when reading the transmit/receive buffer register in the CPU channel receive enable bit =
“1” or when the CPU channel receive enable bit is “0”.
4: This bit is cleared to “0” when writing to the transmit/receive buffer register in the CPU channel transmit enable bit
= “1” or when the CPU channel transmit enable bit is “0”.
Fig. 3.4.45 Structure of EXB interrupt source register
b0
b7
0
0
0
0 0
EXB index register (EXBINDEX) [address 003316]
Bit symbol
Bit name
INDEX
[2:0]
Index bits
b7:b3
Not used
At reset
R W
H/W S/W
– O O
The accessible register, using the register window, 0
depends on these index bits contents as follows:
b2b1b0
0 0 0 : External I/O configuration register
0 0 1 : Transmit/Receive buffer register
0 1 0 : Memory channel operation mode register
0 1 1 : Memory address counter
1 0 0 : End address register
1 0 1 : Do not set.
1 1 0 : Do not set.
1 1 1 : Do not set.
–
– O O
Write “0” when writing.
“0” is read when reading.
Function
–: State remaining
Fig. 3.4.46 Structure of EXB index register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 57 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
Register window 1 (EXBREG1) [address 003416]
Bit symbol
LOW_WIN
[7:0]
Bit name
–
At reset
R W
H/W S/W
In- O O
The accessible register, using this register window, Independs on the EXB index register contents as definite definite
follows:
Index value
: External I/O configuration register
“0016”
“0116”
: Transmit/Receive buffer register
“0216”
: Memory channel operation mode register
“0316”
: Memory address counter
“0416”
: End address register
Function
Fig. 3.4.47 Structure of Register window 1
b0
b7
0
0
0
Index = 0016 : External I/O configuration register (EXBCFGL) [address 003416]
Bit symbol
EXB_CTR
INT_CTR
[2:0]
Bit name
EXB pin control bit
(Pins P10 to P17, P30 to P34)
P33/ExINT pin control bit
A1_CTR
P43/ExA1 pin control bit
b7:b5
Not used
Function
0 : Port
1 : EXB function pin
Selects a signal of P33/ExINT pin.
ON/OFF is programmed by each bit. An output logical
sum of P33/ExINT pins set for ON are performed and it
is output as an “L” active signal.
b3b2b1
0 0 1 : RxB_RDY (RxBuf ready) output
0 1 0 : TxB_RDY (TxBuf ready) output
1 0 0 : Mch_req (Memory channel request) output
Others : Do not set.
0 : Port
1 : A1 input (used to read status)
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
0
–
O O
–
–
O O
–: State remaining
Fig. 3.4.48 Index00[low]; Structure of External I/O configuration register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 58 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
Index =0116 : Transmit/Receive buffer register (RXBUF/TXBUF) [address 003416]
Bit symbol
RXBUF/
TXBUF
Bit name
–
At reset
R W
H/W S/W
– O O
The data received from an external bus is written here 0
at the rise timing of external write signal.
The data transmitted to an external bus is written here
at the timing of internal CPU write or memory write.
Function
The receive buffer register (RXBUF) contents can be read out by reading to this address with the CPU. The data which the
CPU has written to this address is stored in the transmit buffer register (TXBUF).
However, do not perform write operation with the CPU to this address if the memory channel direction control bits of
memory channel operation mode register is “102” (transmit mode) and the memory channel status bits of EXB interrupt
source register are “012” or “102” (memory channel being operating).
Fig. 3.4.49 Index01[low]; Structure of Transmit/Receive buffer register
b0
b7
0
0
0
0
Index =0216 : Memory channel operation mode register (MCHMOD) [address 003416]
0
Bit symbol
Function
Bit name
MC_DIR
[1:0]
Memory channel direction
control bit
BURST
Burst bit
b7:b3
Not used
b1b0
0 0 : Operation disabled
0 1 : Receive mode
1 0 : Transmit mode
1 1 : Do not set.
0 : Cycle mode (each byte transfer according to
assertion or negation)
1 : Burst mode (continuous transfer till the terminal
count)
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
–
–
O O
–: State remaining
Fig. 3.4.50 Index02[low]; Structure of Memory channel operation mode register
b7
b0
Index = 0316 : Memory address counter (MEMADL) [address 003416]
Bit symbol
IM_A
[7:0]
Bit name
–
At reset
R W
H/W S/W
Register to set the low-order address of memory 0
– O O
channel operation beginning.
This contents are increased each time one memory
access ends.
Fig. 3.4.51 Index03[low]; Structure of Memory address counter
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 59 of 89
Function
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
Index = 0416 : End address register (ENDADL) [address 003416]
Bit symbol
END_A
[7:0]
Bit name
–
At reset
R W
H/W S/W
O
O
Register to set the low-order address of memory 0
–
channel operation end.
Function
–: State remaining
Fig. 3.4.52 Index04[low]; Structure of End address register
b0
b7
Register window 2 (EXBREG2) [address 003516]
Bit symbol
HIGH_WIN
[7:0]
Bit name
–
At reset
R W
H/W S/W
In- O O
The accessible register, using this register window, Independs on the EXB index register contents as definite definite
follows:
Index value
: External I/O configuration register
“0016”
: Transmit/Receive buffer register
“0116”
: Memory channel operation mode register
“0216”
“0316”
: Memory address counter
: End address register
“0416”
Function
Fig. 3.4.53 Structure of Register window 2
b0
b7
0
0
0
Index = 0016 : External I/O configuration register (EXBCFGH) [address 003516]
Bit symbol
Bit name
DRQ_CTR
[1:0]
P40/ExDREQ/RxD pin control
bit
DAK_CTR
[1:0]
P41/ExDACK/TxD pin control
bit
TC_CTR
P42/ExTC/SCLK pin control bit
b7:b5
Not used
Function
b1b0
0 0 : Port
0 1 : Do not set.
1 0 : ExDREQ function; RxB_RDY (RxBuf ready) output
1 1 : ExDREQ function; Mch_req (Memory channel
request) output
Specifies P41/ExDACK/TxD pin function.
Selects which mode; requiring read or write signal, or
not requiring it for use of DMA acknowledge function.
b3b2
0 0 : Port
0 1 : Do not set.
1 0 : ExDACK function; DMA acknowledge input
(Mode for read and write signals used together)
1 1 :ExDACK function; DMA acknowledge input
(Mode for read and write signals not required)
0 : Port
1 : ExTC (terminal count) input
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
0
–
O O
0
–
O O
–
–
O O
–: State remaining
Fig. 3.4.54 Index00[high]; Structure of External I/O configuration register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 60 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0
0
0
0
Index = 0316 : Memory address counter (MEMADH) [address 003516]
0
Bit symbol
Bit name
IM_A
[10:8]
–
b7:b3
Not used
At reset
R W
H/W S/W
Register to set the high-order address of memory 0
– O O
channel operation start.
This contents are increased each time one memory
access ends.
Write “0” when writing.
–
– O O
“0” is read when reading.
Function
–: State remaining
Fig. 3.4.55 Index03[high]; Structure of Memory address counter
b0
b7
0
0
0
0
Index = 0416 : End address register (ENDADH) [address 003516]
0
Bit symbol
Bit name
END_A
[10:8]
b7:b3
–
Not used
At reset
R W
H/W S/W
Register to set the high-order address of memory 0
– O O
channel operation end.
Write “0” when writing.
–
– O O
“0” is read when reading.
Function
–: State remaining
Fig. 3.4.56 Index04[high]; Structure of End address register
AA
AA
AD control register
b7 b6 b5 b4 b3 b2 b1 b0
AD control register (ADCON) [Address : 3616 ]
B
Name
0
Analog input pin selection bits
1
2
Function
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : P10/DQ0/AN0
1 : P11/DQ1/AN1
0 : P12/DQ2/AN2
1 : P13/DQ3/AN3
0 : P14/DQ4/AN4
1 : P15/DQ5/AN5
0 : P16/DQ6/AN6
1 : P17/DQ7/AN7
At reset
R W
0
AAAAAAAAAAAAAA
AA
AA
AA
AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAA
A
AA
A
AA
AA
AA
AA
AAAAAAAAAAAAAA
AA
AA
AA
AAAAAAAAAAAAAAAA
AA
AA
3
AD conversion completion bit 0 : Conversion in progress
1 : Conversion completed
4 Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are indefinite.
?
5
?
6
?
7
?
Fig. 3.4.57 Structure of AD control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
1
page 61 of 89
APPENDIX
38K0 Group
3.4 List of registers
AD conversion register 1
b7 b6 b5 b4 b3 b2 b1 b0
AD conversion register 1 (AD1) [Address : 3716]
B
Function
0 The read-only register in which the A/D conversion’s results are
At reset
R W
?
✕
?
✕
b0
?
✕
b9 b8 b7 b6 b5 b4 b3 b2
?
✕
?
✕
?
✕
6
?
✕
7
?
✕
1
stored.
2
b7
3
4
b7
5
< 8-bit read>
< 10-bit read>
b0
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 3.4.58 Structure of AD conversion register 1
A
A
AD conversion register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
AD conversion register 2 (AD2) [Address : 38
16]
B
Function
Name
A
A
R W
?
✕
?
✕
0
✕
0
✕
4
0
✕
5
0
✕
6
0
✕
7 Fix this bit to “0”.
0
✕
0 The read-only register in which the A/D conversion’s results are
stored.
b7
1
0
< 10-bit read>
b0
b9 b8
2 Nothing is allocated for these bits. These are write disabled bits.
3
When these bits are read out, the contents are “0”.
Fig. 3.4.59 Structure of AD conversion register 2
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset
page 62 of 89
APPENDIX
38K0 Group
3.4 List of registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register (WDTCON) [Address : 3916]
Function
B
Name
0 Watchdog timer H (for read-out of high-order 6 bits)
At reset
R W
1
✕
1
1
✕
2
1
✕
3
1
✕
4
1
✕
5
1
✕
6 STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
0
7 Watchdog timer H count
0 : Watchdog timer L underflow
1 : System clock/16
0
source selection bit
Fig. 3.4.60 Structure of Watchdog timer control register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 1
CPU mode register
(CPUM: address 3B16)
B
0
Function
Name
Processor mode bits
1
b1 b0
0 0 : Single-chip mode
0 1 : Not available
1 0 : Not available
1 1 : Not available
0 : 0 page
1 : 1 page
0
*
2
Stack page selection bit
3
Fix this bit to “1”.
1
4
Fix this bit to “0”.
0
5
System clock selection bit
0 : Main clock f(XIN)
1 : fSYN
6
System clock division ratio
selection bits
b7 b6
7
0 0 : φ = f(system clock)/8 (8-divide mode)
0 1 : φ = f(system clock)/4 (4-divide mode)
1 0 : φ = f(system clock)/2 (2-divide mode)
1 1 : φ = f(system clock) (Through mode)
*: The initial value of bit 1 depends on the CNVss level.
Fig. 3.4.61 Structure of CPU mode register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
At reset R W
page 63 of 89
0
0
0
APPENDIX
38K0 Group
3.4 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1)
[Address : 3C16]
Name
B
RW
Function
At reset
USB bus reset
0 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
SOF interrupt
1 USB
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
device interrupt
2 USB
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
interrupt
3 EXB
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
4 request bit
INT0 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
X interrupt
5 Timer
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
Timer 1 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
6 request bit
Timer 2 interrupt
0 : No interrupt request issued
7 request bit
1 : Interrupt request issued
✽ “0” can be set by software, but “1” cannot be set.
Fig. 3.4.62 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2)
[Address : 3D16]
B
Name
Function
At reset
0 : No interrupt request issued
1 : Interrupt request issued
0
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
INT1 interrupt
0 request bit
1
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
I/O transmit
3 Serial
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
4 request bit
CNTR0 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
wake-up
5 Key-on
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
✽
6
A/D conversion
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
7
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
Fig. 3.4.63 Structure of Interrupt request register 2
page 64 of 89
✽
I/O receive
2 Serial
interrupt request bit
✽ “0” can be set by software, but “1” cannot be set.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
RW
APPENDIX
38K0 Group
3.4 List of registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1)
[Address : 3E16]
Name
B
USB bus reset
0 interrupt enable bit
SOF interrupt
1 USB
enable bit
device interrupt
2 USB
enable bit
interrupt
3 EXB
enable bit
INT0 interrupt
4 enable bit
X interrupt
5 Timer
enable bit
Timer 1 interrupt
6 enable bit
Timer 2 interrupt
7 enable bit
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
RW
0
0
0
0
0
Fig. 3.4.64 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2 (ICON2)
[Address : 3F16]
0
B
Name
INT1 interrupt
0 enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
1 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
I/O transmit
3 Serial
interrupt enable bit
wake-up
5 Key-on
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
A/D conversion
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
CNTR0 interrupt
6
7 Fix this bit to “0”.
Fig. 3.4.65 Structure of Interrupt control register 2
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 65 of 89
0
0
I/O receive
2 Serial
interrupt enable bit
4 enable bit
At reset
0
0
0
0
0
0
RW
APPENDIX
38K0 Group
3.4 List of registers
AA
Serial I/O control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register (SIOCON) [Address : 0FE016]
Name
B
Function
At reset
0 BRG count source
selection bit (CSS)
1 Serial I/O synchronous
clock selection bit (SCS)
0 : System clock
1 : System clock/4
• In clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
• In UART
0 : BRG output divided by 16
1 : External clock input divided by 16
2 SRDY output enable bit
0 : P43 pin operates as ordinary I/O pin
1 : P43 pin operates as SRDY output pin
0
0 : Interrupt when transmit buffer has emptied
1 : Interrupt when transmit shift operation is
completed
0
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0
0 : Clock asynchronous(UART) serial I/O
1 : Clock synchronous serial I/O
0
0 : Serial I/O disabled
(pins P40 to P43 operate as ordinary I/O pins)
1 : Serial I/O enabled
(pins P40 to P43 operate as serial I/O pins)
0
(SRDY)
3 Transmit interrupt
source selection bit (TIC)
4 Transmit enable bit (TE)
5 Receive enable bit (RE)
6 Serial I/O mode selection bit
(SIOM)
7 Serial I/O enable bit
(SIOE)
R W
0
0
0
Fig. 3.4.66 Structure of Serial I/O control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 0FE116]
Name
B
Character
length
selection bit
0
(CHAS)
1 Parity enable bit
(PARE)
2 Parity selection bit
(PARS)
3 Stop bit length selection bit
(STPS)
Function
At reset
0 : 8 bits
1 : 7 bits
0
0 : Parity checking disabled
1 : Parity checking enabled
0
0 : Even parity
1 : Odd parity
0
0 : 1 stop bit
1 : 2 stop bits
0
4 Nothing is allocated for this bit. This is a write disabled bit.
R W
0
✕
1
✕
6
1
✕
7
1
✕
When this bit is read out, the contents are “0”.
5 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the contents are “1”.
Fig. 3.4.67 Structure of UART control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 66 of 89
APPENDIX
38K0 Group
3.4 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 0FE216]
Function
B
Set
a
count
value
of
baud
rate
generator.
0
At reset
R W
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
Fig. 3.4.68 Structure of Baud rate generator
b7
b0
0
EP01 MAX. packet size register (EP01MAX) [address 0FEC16]
Bit symbol
MXPS01
[6:0]
b7
Function
Bit name
Max. packet size bit
Not used
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.69 Structure of EP01 MAX. packet size register
b7
0
b0
EP02 MAX. packet size register (EP02MAX) [address 0FEC16]
Bit symbol
MXPS02
[6:0]
b7
Function
Bit name
Max. packet size bit
Not used
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.70 Structure of EP02 MAX. packet size register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 67 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0
EP03 MAX. packet size register (EP03MAX) [address 0FEC16]
Bit symbol
MXPS03
[6:0]
b7
At reset
R W
H/W S/W
0
– O O
Function
Bit name
IN : These bits are invalid.
OUT : Set the maximum packet size.
Write “0” when writing.
“0” is read when reading.
Max. packet size bit
Not used
–
–
O O
–: State remaining
Fig. 3.4.71 Structure of EP03 MAX. packet size register
b0
b7
0
EP00 buffer area set register (EP00BUF) [address 0FED16]
0 0
Bit symbol
At reset
R W
H/W S/W
0
– O O
Function
Bit name
BADD00
[4:0]
EP00 beginning address set bit
b7:b5
Not used
Set the beginning address of EP00’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
–
–
O O
–: State remaining
Fig. 3.4.72 Structure of EP00 buffer area set register
b0
b7
0 0
0
EP01 buffer area set register (EP01BUF) [address 0FED16]
Bit symbol
Function
Bit name
BADD01
[4:0]
EP01 beginning address set bit
b7:b5
Not used
Set the beginning address of EP01’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.73 Structure of EP01 buffer area set register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 68 of 89
APPENDIX
38K0 Group
3.4 List of registers
b0
b7
0 0
EP02 buffer area set register (EP02BUF) [address 0FED16]
0
Bit symbol
Function
Bit name
BADD02
[4:0]
EP02 beginning address set bit
b7:b5
Not used
Set the beginning address of EP02’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.74 Structure of EP02 buffer area set register
b0
b7
0 0
0
EP03 buffer area set register (EP03BUF) [address 0FED16]
Bit symbol
Function
Bit name
BADD03
[4:0]
EP03 beginning address set bit
b7:b5
Not used
Set the beginning address of EP03’s buffer area.
(32-byte unit)
b4b3b2b1b0
0 0 0 1 0 : 004016
0 0 0 1 1 : 006016
..............
1 1 1 1 0 : 03C016
1 1 1 1 1 : 03E016
Write “0” when writing.
“0” is read when reading.
At reset
R W
H/W S/W
0
– O O
–
–
O O
–: State remaining
Fig. 3.4.75 Structure of EP03 buffer area set register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 69 of 89
APPENDIX
38K0 Group
3.4 List of registers
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 pull-up control register (PULL0)
[Address : 0FF016]
Name
B
0
P00 pul l-up control bit
1
P00 pul l-up control bit
2
P00 pul l-up control bit
3
P00 pul l-up control bit
4
P00 pul l-up control bit
5
P00 pul l-up control bit
6 P00 pul l-up control bit
7
P00 pul l-up control bit
Function
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
0 : No pull-up
1 : Pull-up
At reset
RW
0
0
0
0
0
0
0
0
Fig. 3.4.76 Structure of Port P0 pull-up control register
Port P5 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P5 pull-up control register (PULL5)
[Address : 0FF216]
B
Name
0 P50 pul l-up control bit
1
Nothing is arranged for this bit. This is a write disabled bit.
When this bit is read out, the contents are “0”.
2 P52 pul l-up control bit
3
page 70 of 89
0 : No pull-up
1 : Pull-up
Nothing is arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0”.
At reset
0
0
0
0
4
0
5
0
6
0
7
0
Fig. 3.4.77 Structure of Port P5 pull-up control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
Function
0 : No pull-up
1 : Pull-up
RW
APPENDIX
38K0 Group
3.4 List of registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE)
[Address : 0FF316]
B
Function
Name
At reset
0
INT0 interrupt edge
selection bit
1
Nothing is arranged for this bits. This is a write disabled bit.
When this bit is read out, the contents are “0”.
0
2
INT1 interrupt edge
selection bit
0
3
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are “0”.
0 : Falling edge active
1 : Rising edge active
R W
0
0 : Falling edge active
1 : Rising edge active
0
4
0
5
0
6
0
7
0
Fig. 3.4.78 Structure of Interrupt edge selection register
PLL control register
b7 b6 b5 b4 b3 b2 b1 b0
PLL control register (PLLCON)
[Address : 0FF816]
Name
B
Function
0 Nothing is arranged for these bit. These are write disabled bits.
1 When these bits are read out, the contents are “0”.
2
3 USB clock division b4 b3
ratio selection bits 0 0 : Divided by 8 (fSYN = fUSB/8)
0 1 : Divided by 6 (fSYN = fUSB/6)
4
1 0 : Divided by 4 (fSYN = fUSB/4)
1 1 : Not selected
5
6
7
PLL operation mode b6 b5
0 0 : Not multiplied (fVCO = fXIN)
selection bits
0 1 : Double (fVCO = fXIN ✕ 2)
1 0 : Quadruple (fVCO = fXIN ✕ 4)
1 1 : Multiplied by 8 (fVCO = fXIN ✕ 8)
PLL enable bit
0 : Disabled
1 : Enabled
Fig. 3.4.79 Structure of PLL control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 71 of 89
At reset
0
0
0
0
RW
APPENDIX
38K0 Group
3.4 List of registers
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG
(MISRG: address 0FFB16)
B
Name
0
Oscillation stabilizing time
set after STP instruction
released bit
1
2
At reset R W
Functions
0 : Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1 : Automatically set nothing
Nothing is arranged for these bits. These are write disabled bits.
When these bits are read out, the contents are indefinite.
0
?
3
4
5
6
7
Fig. 3.4.80 Structure of MISRG
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register
(FMCR : address 0FFE16) (Note 1)
b
Name
0 RY/BY status flag
Functions
0 : Busy (being written or
erased)
1 : Ready
At reset R W
1
0
0 : Normal mode (Software
commands invalid)
1 : CPU rewrite mode
(Software commands
acceptable)
CPU rewrite mode
0: Normal mode
0
entry flag
1: CPU rewrite mode
Flash memory reset 0: Normal operation
0
bit (Note 3)
1: Reset
User area/Boot area 0: User ROM area
0
selection bit (Note 4) 1: Boot ROM area
Undefined
Nothing is arranged for these bits. If writing,
set “0”. When these bits are read out,
Undefined
the contents are undefined.
Undefined
1 CPU rewrite mode
select bit (Note 2)
2
3
4
5
6
7
Notes 1: The contents of flash memory control register are “XXX00001” just
after reset release.
2: For this bit to be set to “1”, the user needs to write “0” and then “1”
to it in succession. If it is not this procedure, this bit will not be set to
“1”. Additionally, it is required to ensure that no interrupt will be
generated during that interval.
Use the control program in the area except the built-in flash memory
for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”.
Set this bit 3 to “0” subsequently after setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory
for write to this bit.
Fig. 3.4.81 Structure of Flash memory control register
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 72 of 89
APPENDIX
38K0 Group
3.5 Package outline
3.5 Package outline
PLQP0064GA-A
JEITA Package Code
P-LQFP64-14x14-0.80
RENESAS Code
PLQP0064GA-A
Previous Code
64P6U-A
MASS[Typ.]
0.7g
HD
*1
D
33
48
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
c
Reference Dimension in Millimeters
Symbol
*2
E
HE
c1
b1
ZE
Terminal cross section
64
17
c
Index mark
A2
16
ZD
A
1
A1
F
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y
e
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 73 of 89
*3
Detail F
bp
x
e
x
y
ZD
ZE
L
L1
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
1.0
1.0
0.3 0.5 0.7
1.0
APPENDIX
38K0 Group
3.5 Package outline
PLQP0064KB-A
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
MASS[Typ.]
0.3g
HD
*1
D
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
64
1
c1
Terminal cross section
ZE
17
Reference Dimension in Millimeters
Symbol
c
E
*2
HE
b1
16
Index mark
ZD
c
A
*3
A1
y
e
A2
F
bp
L
x
L1
Detail F
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 74 of 89
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Min Nom Max
9.9 10.0 10.1
9.9 10.0 10.1
1.4
11.8 12.0 12.2
11.8 12.0 12.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.25
1.25
0.35 0.5 0.65
1.0
THIS PAGE IS BLANK FOR REASONS OF LAYOUT.
APPENDIX
38K0 Group
3.6 Machine instructions
APPENDIX
38K0 Group
3.6 Machine instructions
3.6 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
ADC
(Note 1)
(Note 5)
When T = 0
A←A+M+C
When T = 1
M(X) ← M(X) + M + C
AND
(Note 1)
When TV= 0
A←A M
When T = 1 V
M(X) ← M(X) M
7
ASL
C←
0
←0
IMM
# OP n
A
# OP n
Addressing mode
BIT,A,AR
BIT,
# OP n
ZP
# OP n
BIT,ZP,
ZPR
BIT,
# OP n
#
ZP, X
ZP, Y
OP n
# OP n
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory
where is indicated by X.
69 2
2
65 3
2
75 4
2
6D 4
3 7D 5
3 79 5
3
61 6
2 71 6
2
N
V
•
•
•
•
Z
C
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1 the contents of A remain unchanged, but status flags are
changed.
M(X) represents the contents of memory
where is indicated by X.
29 2
2
25 3
2
35 4
2
2D 4
3 3D 5
3 39 5
3
21 6
2 31 6
2
N
•
•
•
•
•
Z
•
06 5
2
16 6
2
0E 6
3 1E 7
3
N
•
•
•
•
•
Z
C
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A 2
1
BBC
(Note 4)
Ai or Mi = 0?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative address. If the bit is 1, next instruction is
executed.
13 4
+
20i
2
17 5
+
20i
3
•
•
•
•
•
•
•
•
BBS
(Note 4)
Ai or Mi = 1?
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative address. If the bit is 0, next instruction is
executed.
03 4
+
20i
2
07 5
+
20i
3
•
•
•
•
•
•
•
•
BCC
(Note 4)
C = 0?
This instruction takes a branch to the appointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
90 2
2
•
•
•
•
•
•
•
•
BCS
(Note 4)
C = 1?
This instruction takes a branch to the appointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
B0 2
2
•
•
•
•
•
•
•
•
BEQ
(Note 4)
Z = 1?
This instruction takes a branch to the appointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
F0 2
2
•
•
•
•
•
•
•
•
BIT
A
M7 M6 •
•
•
•
Z
•
BMI
(Note 4)
N = 1?
This instruction takes a branch to the appointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
30 2
2
•
•
•
•
•
•
•
•
BNE
(Note 4)
Z = 0?
This instruction takes a branch to the appointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
D0 2
2
•
•
•
•
•
•
•
•
V
M
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
page 76 of 89
24 3
2
2C 4
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
3
page 77 of 89
APPENDIX
38K0 Group
3.6 Machine instructions
APPENDIX
38K0 Group
3.6 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
A
# OP n
Addressing mode
BIT, A
# OP n
ZP
# OP n
BIT, ZP
# OP n
#
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
BPL
(Note 4)
N = 0?
This instruction takes a branch to the appointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
10 2
2
•
•
•
•
•
•
•
•
BRA
PC ← PC ± offset
This instruction branches to the appointed address. The branch address is specified by a
relative address.
80 4
2
•
•
•
•
•
•
•
•
BRK
B←1
(PC) ← (PC) + 2
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
M(S) ← PS
S←S–1
I← 1
PCL ← ADL
PCH ← ADH
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
•
•
•
1
•
1
•
•
BVC
(Note 4)
V = 0?
This instruction takes a branch to the appointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
50 2
2
•
•
•
•
•
•
•
•
BVS
(Note 4)
V = 1?
This instruction takes a branch to the appointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
70 2
2
•
•
•
•
•
•
•
•
CLB
Ai or Mi ← 0
This instruction clears the designated bit i of A
or M.
•
•
•
•
•
•
•
•
CLC
C←0
This instruction clears C.
18 2
1
•
•
•
•
•
•
•
0
CLD
D←0
This instruction clears D.
D8 2
1
•
•
•
•
0
•
•
•
CLI
I←0
This instruction clears I.
58 2
1
•
•
•
•
•
0
•
•
CLT
T←0
This instruction clears T.
12 2
1
•
•
0
•
•
•
•
•
CLV
V←0
This instruction clears V.
B8 2
1
•
0
•
•
•
•
•
•
CMP
(Note 3)
When T = 0
A–M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the contents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
N
•
•
•
•
•
Z
C
COM
M←M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
N
•
•
•
•
•
Z
•
CPX
X–M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
E0 2
CPY
Y–M
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
C0 2
DEC
A ← A – 1 or
M←M–1
This instruction subtracts 1 from the contents
of A or M.
__
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 78 of 89
00 7
1
1B 2
+
20i
C9 2
1
1F 5
+
20i
2
C5 3
2
44 5
2
2
E4 3
2
EC 4
3
N
•
•
•
•
•
Z
C
2
C4 3
2
CC 4
3
N
•
•
•
•
•
Z
C
C6 5
2
CE 6
3 DE 7
N
•
•
•
•
•
Z
•
2
1A 2
1
D5 4
D6 6
2
2
CD 4
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
3 DD 5
3 D9 5
3
page 79 of 89
3
C1 6
2 D1 6
2
APPENDIX
38K0 Group
3.6 Machine instructions
APPENDIX
38K0 Group
3.6 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
A
# OP n
BIT, A
# OP n
Addressing mode
ZP
# OP n
BIT, ZP
# OP n
#
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
DEX
X←X–1
This instruction subtracts one from the current CA 2
contents of X.
1
N
•
•
•
•
•
Z
•
DEY
Y←Y–1
This instruction subtracts one from the current
contents of Y.
88 2
1
N
•
•
•
•
•
Z
•
DIV
A ← (M(zz + X + 1),
M(zz + X )) / A
M(S) ← one's complement of Remainder
S←S–1
Divides the 16-bit data in M(zz+(X)) (low-order
byte) and M(zz+(X)+1) (high-order byte) by the
contents of A. The quotient is stored in A and
the one's complement of the remainder is
pushed onto the stack.
•
•
•
•
•
•
•
•
EOR
(Note 1)
When T = 0
–M
A←AV
When T = 0, this instruction transfers the contents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
When T = 1
–M
M(X) ← M(X) V
E2 16 2
49 2
2
45 3
2
55 4
2
4D 4
3 5D 5
3 59 5
E6 5
2
F6 6
2
EE 6
3 FE 7
3
3
41 6
2 51 6
2
INC
A ← A + 1 or
M←M+1
This instruction adds one to the contents of A
or M.
INX
X←X+1
This instruction adds one to the contents of X.
E8 2
1
N
•
•
•
•
•
Z
•
INY
Y←Y+1
This instruction adds one to the contents of Y.
C8 2
1
N
•
•
•
•
•
Z
•
JMP
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (ADH, ADL)
PCH ← M (ADH, ADL + 1)
If addressing mode is ZP, IND
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction jumps to the address designated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
4C 3
3
•
•
•
•
•
•
•
•
JSR
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction stores the contents of the PC
in the stack, then jumps to the address designated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
20 6
3
•
•
•
•
•
•
•
•
LDA
(Note 2)
When T = 0
A←M
When T = 1
M(X) ← M
When T = 0, this instruction transfers the contents of M to A.
When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
AD 4
3 BD 5
N
•
•
•
•
•
Z
•
LDM
M ← nn
This instruction loads the immediate value in
M.
•
•
•
•
•
•
•
•
LDX
X←M
This instruction loads the contents of M in X.
A2 2
N
•
•
•
•
•
Z
•
LDY
Y←M
This instruction loads the contents of M in Y.
A0 2
N
•
•
•
•
•
Z
•
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 80 of 89
3A 2
A9 2
2
1
A5 3
2
3C 4
3
2
A6 3
2
2
A4 3
2
B5 4
2
B6 4
B4 4
2
2 AE 4
AC 4
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
6C 5
3 B9 5
3
3 BC 5
BE 5
3
page 81 of 89
3
3
3 B2 4
2
02 7
2
22 5
A1 6
2 B1 6
2
2
APPENDIX
38K0 Group
3.6 Machine instructions
APPENDIX
38K0 Group
3.6 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
LSR
7
0→
Multiplies Accumulator with the memory specified by the Zero Page X address mode and
stores the high-order byte of the result on the
Stack and the low-order byte in A.
NOP
PC ← PC + 1
This instruction adds one to the PC but does EA 2
no otheroperation.
ORA
(Note 1)
When T = 0
A←AVM
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
When T = 1
M(X) ← M(X) V M
PLA
PLP
ROL
S←S–1
# OP n
1
ZP
# OP n
46 5
BIT, ZP
# OP n
2
#
ZP, X
ZP, Y
OP n
# OP n
56 6
2
ABS
ABS, X
ABS, Y
# OP n
# OP n
# OP n
4E 6
3 5E 7
3
IND
# OP n
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
# OP n
62 15 2
1
09 2
2
05 3
2
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
REL
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
0
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
48 3
1
M(S) ← PS
S←S–1
This instruction pushes the contents of PS to
the memory location designated by S and decrements the contents of S by one.
08 3
1
S←S+1
A ← M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
68 4
1
S←S+1
PS ← M(S)
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
28 4
1
7
←
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
2A 2
1
26 5
2
36 6
2
2E 6
3 3E 7
3
N
•
•
•
•
•
Z
C
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
6A 2
1
66 5
2
76 6
2
6E 6
3 7E 7
3
N
•
•
•
•
•
Z
C
82 8
2
•
•
•
•
•
•
•
•
0
←C ←
7
C→
RRF
7
→
RTS
BIT, A
Processor status register
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
ROR
RTI
# OP n
4A 2
M(S) • A ← A ✽ M(zz + X)
S←S–1
PHP
# OP n
A
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
0
→C
MUL
PHA
IMM
Addressing mode
0
→
0
→
This instruction rotates 4 bits of the M content
to the right.
S←S+1
PS ← M(S)
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PC L . S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
(PC) ← (PC) + 1
This instruction increments S by one and
stores the contents of the memory location
d e s i g n a t e d b y S i n P C L. S i s a g a i n
incremented by one and the contents of the
memory location is stored in PC H . PC is
incremented by 1.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 82 of 89
(Value saved in stack)
(Value saved in stack)
40 6
1
60 6
1
•
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 83 of 89
•
•
•
•
•
•
•
APPENDIX
38K0 Group
3.6 Machine instructions
APPENDIX
38K0 Group
3.6 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
SBC
(Note 1)
(Note 5)
When T = 0 _
A←A–M–C
When T = 1
_
M(X) ← M(X) – M – C
IMM
# OP n
E9 2
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the contents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
A
# OP n
Addressing mode
BIT, A
# OP n
ZP
# OP n
2
E5 3
BIT, ZP
# OP n
#
2
ZP, X
ZP, Y
OP n
# OP n
F5 4
2
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
ED 4
3 FD 5
3 F9 5
3
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
E1 6
2 F1 6
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
N
V
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
SEB
Ai or Mi ← 1
This instruction sets the designated bit i of A
or M.
SEC
C←1
This instruction sets C.
38 2
1
•
•
•
•
•
•
•
1
SED
D←1
This instruction set D.
F8 2
1
•
•
•
•
1
•
•
•
SEI
I←1
This instruction set I.
78 2
1
•
•
•
•
•
1
•
•
SET
T←1
This instruction set T.
32 2
1
•
•
1
•
•
•
•
•
STA
M←A
This instruction stores the contents of A in M.
The contents of A does not change.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
This instruction resets the oscillation control F/
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
STP
0B 2
+
20i
1
0F 5
+
20i
85 4
42 2
2
M←X
This instruction stores the contents of X in M.
The contents of X does not change.
86 4
2
STY
M←Y
This instruction stores the contents of Y in M.
The contents of Y does not change.
84 4
2
TAX
X←A
This instruction stores the contents of A in X. AA 2
The contents of A does not change.
TAY
Y←A
This instruction stores the contents of A in Y.
The contents of A does not change.
TST
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
TSX
X←S
This instruction transfers the contents of S in BA 2
X.
TXA
A←X
This instruction stores the contents of X in A.
TXS
S←X
TYA
A←Y
Notes 1
2
3
4
5
:
:
:
:
:
95 5
2
8D 5
3 9D 6
3 99 6
1
STX
WIT
2
2 91 7
2
3
•
•
•
•
•
•
•
•
8C 5
3
•
•
•
•
•
•
•
•
1
N
•
•
•
•
•
Z
•
1
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
1
N
•
•
•
•
•
Z
•
8A 2
1
N
•
•
•
•
•
Z
•
This instruction stores the contents of X in S.
9A 2
1
•
•
•
•
•
•
•
•
This instruction stores the contents of Y in A.
98 2
1
N
•
•
•
•
•
Z
•
The WIT instruction stops the internal clock
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All registers or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
C2 2
1
•
•
•
•
•
•
•
•
64 3
94 5
2
2
The number of cycles “n” is increased by 3 when T is 1.
The number of cycles “n” is increased by 2 when T is 1.
The number of cycles “n” is increased by 1 when T is 1.
The number of cycles “n” is increased by 2 when branching has occurred.
N, V, and Z flags are invalid in decimal operation mode.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
81 7
2 8E 5
A8 2
96 5
3
page 84 of 89
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 85 of 89
APPENDIX
38K0 Group
3.6 Machine instructions
Symbol
Contents
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
Symbol
+
–
✽
/
V
V
–
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
zz
M
M(X)
M(S)
M(ADH, ADL)
M(00, ADL)
Ai
Mi
OP
n
#
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 86 of 89
Contents
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any addressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits.
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
Number of bytes
APPENDIX
38K0 Group
3.7 List of instruction code
3.7 List of instruction code
D7 – D4
D3 – D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
ABS
ASL
ABS
SEB
0, ZP
0000
0
BRK
BBS
ORA
JSR
IND, X ZP, IND 0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
ORA
IMM
ASL
A
SEB
0, A
—
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
ORA
ABS, Y
DEC
A
CLB
0, A
—
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
ROL
CLB
LDM
AND
ZP ABS, X ABS, X 1, ZP
0100
4
RTI
EOR
IND, X
STP
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
MUL
ADC
IND, X ZP, X
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
JMP
BBC
LDA
IND, Y ZP, IND 5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
DIV
SBC
IND, X ZP, X
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
—
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 87 of 89
ASL
CLB
ORA
ABS, X ABS, X 0, ZP
AND
ABS
EOR
ABS
ROL
ABS
LSR
ABS
SEB
1, ZP
SEB
2, ZP
LSR
CLB
EOR
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
ROR
CLB
ADC
ABS, X ABS, X 3, ZP
LDX
CLB
LDY
LDA
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
DEC
CLB
CMP
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
INC
CLB
SBC
ABS, X ABS, X 7, ZP
APPENDIX
38K0 Group
3.8 SFR memory map
3.8 SFR memory map
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
000216 Port P1 (P1)
000316 Port P1 direction register (P1D)
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
000616 Port P3 (P3)
000716 Port P3 direction register (P3D)
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
000A16 Port P5 (P5)
000B16 Port P5 direction register (P5D)
000C16 Port P6 (P6)
000D16 Port P6 direction register (P6D)
000E16 Reserved (Note)
000F16 Reserved (Note)
001016 USB control register (USBCON)
001116 USB function enable register (USBAE)
001216 USB function address register (USBA0)
001316 Reserved (Note)
001416 Frame number register Low (FNUML)
001516 Frame number register High (FNUMH)
001616 USB interrupt source enable register (USBICON)
001716 USB interrupt source register (USBIREQ)
001816 Endpoint index register (USBINDEX)
001916 Endpoint field register 1 (EPXXREG1)
002016 Prescaler 12 (PRE12)
002116 Timer 1 (T1)
002216 Timer 2 (T2)
002316 Timer X mode register (TM)
002416 Prescaler X (PREX)
002516 Timer X (TX)
002616 Transmit/Receive buffer register (TB/RB)
002716 Serial I/O status register (SIOSTS)
002816 Reserved (Note)
002916 Reserved (Note)
002A16 Reserved (Note)
002B16 Reserved (Note)
002C16 Reserved (Note)
002D16 Reserved (Note)
002E16 Reserved (Note)
002F16 Reserved (Note)
003016 EXB interrupt source enable register (EXBICON)
003116 EXB interrupt source register (EXBIREQ)
003216 Reserved (Note)
003316 EXB index register (EXBINDEX)
003416 EXB field register 1 (EXBREG1)
003516 EXB field register 2 (EXBREG2)
003616 AD control register (ADCON)
003716 AD conversion register 1 (AD1)
003816 AD conversion register 2 (AD2)
003916 Watchdog timer control register (WDTCON)
001A16 Endpoint field register 2 (EPXXREG2)
001B16 Endpoint field register 3 (EPXXREG3)
001C16 Endpoint field register 4 (EPXXREG4)
001D16 Endpoint field register 5 (EPXXREG5)
001E16 Endpoint field register 6 (EPXXREG6)
003A16 Reserved (Note)
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1(IREQ1)
001F16 Endpoint field register 7 (EPXXREG7)
003F16 Interrupt control register 2(ICON2)
0F E016 Serial I/O control register (SIOCON)
0F E116 UART control register (UARTCON)
0F E216 Baud rate generator (BRG)
0FF016 Port P0 pull-up control register (PULL0)
0FF116 Reserved (Note)
0FF216 Port P5 pull-up control register (PULL5)
0FE316 Reserved (Note)
0FE416 Reserved (Note)
0FF316
0FF416
0FF516
0FF616
0F E516 Reserved
0FE616 Reserved
0F E716 Reserved
0FE816 Reserved
0FE916 Reserved
0FEA16 Reserved
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
0FEB16 Reserved (Note)
0FEC16 Endpoint field register 8 (EPXXREG8)
0FED16 Endpoint field register 9 (EPXXREG9)
0FEE16 Reserved (Note)
0FEF16 Reserved (Note)
003D16 Interrupt request register 2(IREQ2)
003E16 Interrupt control register 1(ICON1)
Interrupt edge selection register (INTEDGE)
Reserved (Note)
Reserved (Note)
Reserved (Note)
0FF716 Reserved (Note)
0FF816 PLL control register (PLLCON)
0FF916 Reserved (Note)
0FFA16 Reserved (Note)
0FFB16 MISRG
0FF C16 Reserved (Note)
0FF D16 Reserved (Note)
0FFE16 Flash memory control register (FMCR)
0FFF16 Reserved (Note)
Note: Do not write any data to these addresses, because these areas are reserved.
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
page 88 of 89
APPENDIX
38K0 Group
3.9 Pin configurations
33
34
35
36
37
38
39
41
40
42
43
44
45
46
47
48
P05
P04
P03
P02
P01
P00
P57
P56
P55
P54
P53
P52/INT1
P51/CNTR0
P50/INT0
P27
P26
3.9 Pin configurations
P06
P07
P40/EXDREQ/RXD
P41/EXDACK/TXD
49
32
50
31
51
30
52
29
P42/EXTC/SCLK
P43/EXA1/SRDY
P30
P31
P32
P33/EXINT
P34/EXCS
P35/EXWR
P36/EXRD
P37/EXA0
P10/DQ0/AN0
P11/DQ1/AN1
53
28
54
27
55
56
M38K07M4L-XXXFP/HP
26
M38K09F8LFP/HP
24
57
58
23
page 89 of 89
11
13
14
15
16
XIN
XOUT
VCC
CNVSS2
P60(LED0)
10
9
12
17
VCCE
VREF
VSS
64
7
18
8
19
63
6
62
5
20
3
21
61
4
60
2
22
1
59
P12/DQ2/AN2
P13/DQ3/AN3
P14/DQ4/AN4
P15/DQ5/AN5
P16/DQ6/AN6
P17/DQ7/AN7
CNVSS
RESET
Rev.2.00 Oct 05, 2006
REJ09B0337-0200
25
P25
P24
P23
P22
P21
P20
D0D0+
TrON
USBVREF
DVCC
PVCC
PVSS
P63(LED3)
P62(LED2)
P61(LED1)
REVISION HISTORY
Rev.
38K0 GROUP USER’S MANUAL
Date
Description
Summary
Page
1.0
01/17/03
2.0
10/05/06
First Edition
All pages Package names “64P6U-A” → “PLQP0064GA-A” revised
Package names “64P6Q-A” → “PLQP0064KB-A” revised
38K0 group (Standard) deleted
Chapter 1
2
• Power source voltage (L version) “At 12 MHz/Through mode .... 4.50 to 5.25 V”
deleted
76
Fig. 108 revised
79
CLOCK GENERATING CIRCUIT; “No external resistor is needed .... resistor
exists on-chip.” → “No external resistor is needed .... depending on conditions.)
80
Fig. 111; Pulled up added, NOTE added
Fig. 114 revised
110
NOTES ON USAGE; Power Source Voltage, USB Communication added
Chapter 2
35
3.3.6 (3) USB Communication added
91
Table 2.11.1 revised
92
Table 2.11.2 revised
Chapter 3
20
3.2 deleted
82
3.6 Package outline revised
(1/1)
RENESAS 8-BIT SINGLE-CHIP MICROCOMPUTER
USER’S MANUAL
38K0 Group
Publication Data :
Published by :
Rev.1.00 Jan 17, 2003
Rev.2.00 Oct 05, 2006
Sales Strategic Planning Div.
Renesas Technology Corp.
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
38K0 Group
User's Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan