AD AD9650-EP Dual 16-bit, 105 msps, 1.8 v analog-to-digital converter Datasheet

Dual 16-Bit, 105 MSPS, 1.8 V
Analog-to-Digital Converter
AD9650-EP
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
SDIO/ SCLK/
DCS
DFS
AVDD
OR+
PROGRAMMING DATA
VIN+A
16
CMOS/LVDS
OUTPUT BUFFER
ADC
VIN–A
D15+ (MSB)
TO
D0+ (LSB)
CLK+
DIVIDE 1
TO 8
VREF
CLK–
SENSE
VCM
DUTY CYCLE
STABILIZER
REF
SELECT
DCO
GENERATION
RBIAS
DCO+
DCO–
OR–
CMOS/LVDS
OUTPUT BUFFER
ADC
VIN+B
Radar
Electronic warfare (EW) systems
Joint tactical radio system (JTRS) and other COMSEC
Industrial instrumentation
X-ray, MRI, and ultrasound equipment
High speed pulse acquisition
Chemical and spectrum analysis
General-purpose software radios
DRVDD
SPI
AD9650-EP
VIN–B
APPLICATIONS
CSB
16
D15– (MSB)
TO
D0– (LSB)
MULTICHIP
SYNC
AGND
SYNC
PDWN
OEB
NOTES
1. PIN NAMES ARE FOR THE LVDS PIN CONFIGURATION ONLY.
Figure 1.
GENERAL DESCRIPTION
The AD9650-EP is a dual 16-bit, 105 MSPS analog-to-digital
converter (ADC) designed for digitizing high frequency, wide
dynamic range signals with input frequencies of up to 300 MHz.
Additional application and technical information can be found
in the AD9650 data sheet.
The dual ADC core features a multistage differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth, differential sample-and-hold analog
input amplifiers, and a shared integrated voltage reference, which
eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
1.
The ADC output data can be routed directly to the two external
16-bit output ports or multiplexed on a single 16-bit bus. These
outputs can be set to either 1.8 V CMOS or LVDS.
Flexible power-down options allow significant power savings,
when desired. Programming for setup and control is accomplished
using a 3-wire, SPI-compatible serial interface.
PRODUCT HIGHLIGHTS
2.
3.
4.
5.
On-chip dither option for improved SFDR performance
with low power analog input.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
Operation from a single 1.8 V supply with a separate digital
output driver supply that accommodates 1.8 V CMOS or
LVDS outputs.
Standard serial port interface (SPI) that supports various
product features and functions such as data formatting
(offset binary, twos complement, or Gray coding), enabling
the clock DCS, power-down, and test modes.
12 mm × 12 mm, 80-lead TQFP with an exposed pad
(7.5 mm × 7.5 mm).
The AD9650-EP is available in an 80-lead TQFP and is specified
over the extended temperature range of −55°C to +85°C.
Rev. 0
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Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
11312-001
Dual 16-bit ADC in enhanced package for extended
temperature range of −55°C to +85°C
1.8 V analog supply operation
LVDS output
SNR: 80.5 dBFS at 30 MHz input and 105 MSPS data rate
SFDR: 93 dBc at 30 MHz input and 105 MSPS data rate
Low power: 328 mW per channel at 105 MSPS
Integer 1-to-8 input clock divider
IF sampling frequencies up to 300 MHz
Analog input range of 2.7 V p-p
Optional on-chip dither
Integrated ADC sample-and-hold inputs
Differential analog inputs with 500 MHz bandwidth
ADC clock duty cycle stabilizer (DCS)
AD9650-EP
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital Specifications ....................................................................4
Applications ....................................................................................... 1
Switching Specifications ...............................................................6
Functional Block Diagram .............................................................. 1
Timing Specifications ...................................................................6
General Description ......................................................................... 1
Absolute Maximum Ratings ............................................................8
Product Highlights ........................................................................... 1
Thermal Characteristics ...............................................................8
Revision History ............................................................................... 2
ESD Caution...................................................................................8
Specifications..................................................................................... 3
Pin Configuration and Function Descriptions..............................9
ADC DC Specifications ............................................................... 3
Outline Dimensions ....................................................................... 11
ADC AC Specifications ............................................................... 4
Ordering Guide .......................................................................... 11
REVISION HISTORY
5/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Data Sheet
AD9650-EP
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL) 1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1.35 V Mode)
Load Regulation at 1.0 mA
INPUT REFERRED NOISE
VREF = 1.35 V
ANALOG INPUT
Input Span, VREF = 1.35 V
Input Capacitance 2
Input Common-Mode Voltage
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current1
IAVDD
IDRVDD (1.8 V CMOS)
IDRVDD (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input1 (DRVDD = 1.8 V)
CMOS Output Mode
LVDS Output Mode
Standby Power 3
Power-Down Power
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Min
Typ
16
Guaranteed
±0.4
±0.4
−1
Max
Unit
Bits
±0.7
±2.5
+1.3
% FSR
% FSR
LSB
LSB
LSB
LSB
±0.7
±6
±3
Full
Full
±0.1
±0.5
Full
Full
±2
±15
Full
Full
±7
10
25°C
1.5
LSB rms
Full
Full
Full
Full
2.7
11
0.9
6
V p-p
pF
V
kΩ
Full
Full
1.7
1.7
±0.4
±1.3
% FSR
% FSR
ppm/°C
ppm/°C
±14
mV
mV
1.8
1.8
1.9
1.9
V
V
Full
Full
Full
332
36
100
340
mA
mA
mA
Full
656
675
mW
Full
Full
Full
Full
663
778
50
0.25
2.5
mW
mW
mW
mW
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Standby power is measured with a dc input and with the CLK+ and CLK− pins inactive (set to AVDD or AGND).
1
2
Rev. 0 | Page 3 of 12
AD9650-EP
Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled,
unless otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 30 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 30 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
CROSSTALK 2
ANALOG INPUT BANDWIDTH
1
2
Temperature
Min
25°C
Full
78.4
25°C
Full
77.9
Typ
Max
Unit
80.5
dBFS
dBFS
80.2
dBFS
dBFS
25°C
13
Bits
25°C
Full
−93
−87
25°C
Full
93
dBc
dBc
87
25°C
Full
Full
25°C
dBc
dBc
−101
−94
−105
500
dBc
dBc
dBFS
MHz
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured with a 170 MHz tone at −1 dBFS on one channel and no input on the alternate channel.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS enabled,
unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Typ
Max
CMOS/LVDS/LVPECL
0.9
0.3
AGND
0.9
−100
−100
8
3.6
AVDD
1.4
+100
+100
9
10
12
CMOS
0.9
AGND
1.2
AGND
−100
−100
12
Rev. 0 | Page 4 of 12
AVDD
AVDD
0.6
+100
+100
1
16
20
Unit
V
V p-p
V
V
µA
µA
pF
kΩ
V
V
V
V
µA
µA
pF
kΩ
Data Sheet
Parameter
LOGIC INPUT (CSB) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT/OUTPUT (SDIO/DCS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (OEB, PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage
IOH = 50 µA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 µA
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD)
ANSI Mode
Reduced Swing Mode
Output Offset Voltage (VOS)
ANSI Mode
Reduced Swing Mode
1
2
AD9650-EP
Temperature
Min
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
Full
Full
Full
Full
Full
Full
1.22
0
−90
−10
Full
Full
1.79
1.75
Typ
Max
Unit
2.1
0.6
+10
132
V
V
µA
µA
kΩ
pF
2.1
0.6
−135
+10
V
V
µA
µA
kΩ
pF
2.1
0.6
+10
128
V
V
µA
µA
kΩ
pF
2.1
0.6
−134
+10
V
V
µA
µA
kΩ
pF
26
2
26
2
26
5
26
5
V
V
Full
Full
0.2
0.05
V
V
Full
Full
290
160
345
200
400
230
mV
mV
Full
Full
1.15
1.15
1.25
1.25
1.35
1.35
V
V
Pull up.
Pull down.
Rev. 0 | Page 5 of 12
AD9650-EP
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS enabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate 1
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-by-8 Mode
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
CMOS Mode
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO) 2
DCO to Data Skew (tSKEW)
LVDS Mode
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)2
DCO to Data Skew (tSKEW)
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency), Channel A/Channel B
Wake-Up Time 3
Out-of-Range Recovery Time
Temperature
Min
Typ
Max
Unit
640
MHz
105
105
MSPS
MSPS
ns
6.65
5.0
ns
ns
ns
ns
ps rms
3.5
3.1
−0.4
4.2
ns
ns
ns
3.7
3.9
+0.2
12
12/12.5
500
2
4.5
Description
Limit
Unit
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
0.3
0.4
ns typ
ns typ
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to
an output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge
2
2
40
2
2
10
10
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
10
ns min
Full
Full
Full
Full
20
10
9.5
Full
Full
Full
Full
Full
2.85
4.5
0.8
Full
Full
Full
2.8
Full
Full
Full
Full
Full
Full
Full
2.9
4.75
4.75
1.0
0.075
−0.6
−0.1
0
+0.5
Conversion rate is the clock rate after the divider.
Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17.
3
Wake-up time is defined as the time required to return to normal operation from power-down mode.
1
2
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Rev. 0 | Page 6 of 12
ns
ns
ns
Cycles
Cycles
µs
Cycles
Data Sheet
AD9650-EP
Timing Diagrams
N–1
N+4
tA
N+5
N
N+3
VIN
N+1
tCH
N+2
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
CH A/CH B DATA
N – 13
N – 12
N – 11
N – 10
N–9
N–8
tPD
11312-002
tSKEW
Figure 2. CMOS Default Output Mode Data Output Timing
N–1
N+4
tA
N+5
N
N+3
VIN
N+1
tCH
N+2
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
tSKEW
CH A CH B CH A CH B CH A CH B
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10
CH A/CH B DATA
CH A
N–9
CH B
N–9
11312-003
tPD
CH A
N–8
Figure 3. CMOS Interleaved Output Mode Data Output Timing
N–1
N+4
tA
N+5
N
N+3
VIN
N+1
tCH
N+2
tCLK
CLK+
CLK–
tDCO
DCO+/DCO–
CH A CH B CH A CH B CH A CH B
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10
CH A/CH B DATA
CH A
N–9
CH B
N–9
Figure 4. LVDS Mode Data Output Timing
CLK+
tHSYNC
11312-005
tSSYNC
SYNC
Figure 5. SYNC Input Timing Requirements
Rev. 0 | Page 7 of 12
CH A
N–8
11312-004
tSKEW
tPD
AD9650-EP
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
Electrical1
AVDD to AGND
DRVDD to AGND
VIN+A/VIN+B, VIN−A/VIN−B
to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/DCS to AGND
OEB
PDWN
D0+/D0− Through D15+/D15−
to AGND
DCO+/DCO− to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
1
The exposed pad on the underside of the TQFP package must
be soldered to the ground plane for the package. Soldering the
exposed pad to the PCB increases the reliability of the solder
joints and maximizes the thermal capability of the package.
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. Airflow improves heat dissipation, which reduces θJA. In
addition, metal in direct contact with the package leads from metal
traces, through holes, ground, and power planes reduces θJA.
Table 7. Thermal Resistance
Package Type
80-Lead TQFP_EP
Airflow
Velocity (m/sec)
0
θJA1, 2, 4
22.48
θJC1, 3, 4
4.67
Per JEDEC JESD51-7, plus JEDEC JESD25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-STD-883, Method 1012.1.
4
Per JEDEC STD, a 7 × 7 via array should be used to achieve this value.
1
2
3
ESD CAUTION
−0.3 V to DRVDD + 0.2 V
−55°C to +85°C
150°C
−65°C to +150°C
The inputs and outputs are rated to the supply voltage (AVDD + 0.2 V or
DRVDD + 0.2 V), but they should not exceed 2.1 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 8 of 12
Unit
°C/W
Data Sheet
AD9650-EP
DNC
DNC
VIN–A
VIN+A
AVDD
AVDD
AVDD
AVDD
VCM
SENSE
VREF
RBIAS
AVDD
AVDD
VIN–B
AVDD
AVDD
VIN+B
DNC
DNC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DNC 1
DNC 2
CLK+ 3
DNC
DNC
58 PDWN
57 OEB
60
PIN 1
IDENTIFIER
59
CLK– 4
SYNC 5
D0– 6
56
D0+ 7
D1– 8
54
55
CSB
SCLK/DFS
53
SDIO/DCS
OR+
52
OR–
51
D15+
50
D15–
DRVDD 12
49
D14+
D3– 13
48
D14–
D3+ 14
47
DRVDD
D4– 15
46
D13+
D4+ 16
45
D13–
D5– 17
44
D12+
D5+ 18
DNC 19
43
42
D12–
DNC
41
DNC
AD9650-EP
D1+ 9
TOP VIEW
(Not to Scale)
CONNECT EXPOSED PAD TO GROUND
D2– 10
D2+ 11
DNC 20
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
11312-006
DNC
DNC
D11–
D11+
D10–
D10+
D9–
D9+
DRVDD
DCO–
DCO+
D7–
D7+
D8–
D8+
DRVDD
D6–
D6+
DNC
DNC
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 6. Interleaved Parallel LVDS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
ADC Power Supplies
12, 25, 34, 47
63, 64, 67, 68,
73, 74, 77, 78
0
ADC Analog
65
66
76
75
69
70
72
71
3
4
Digital Input
5
Mnemonic
Type
Description
DRVDD
AVDD
Supply
Supply
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
AGND,
Exposed Pad
Ground
The exposed thermal pad on the bottom of the package provides the analog ground
for the part. This exposed pad must be connected to ground for proper operation.
VIN+A
VIN−A
VIN+B
VIN−B
VREF
SENSE
RBIAS
VCM
CLK+
CLK−
Input
Input
Input
Input
Input/output
Input
Input/output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Rev. 0 | Page 9 of 12
AD9650-EP
Pin No.
Digital Outputs
7
6
9
8
11
10
14
13
16
15
18
17
24
23
27
26
29
28
33
32
36
35
38
37
44
43
46
45
49
48
51
50
53
52
31
30
SPI Control
55
54
56
ADC Configuration
57
58
Do Not Connect
1, 2, 19, 20, 21, 22,
39, 40, 41, 42, 59,
60, 61, 62, 79, 80
Data Sheet
Mnemonic
Type
Description
D0+
D0−
D1+
D1−
D2+
D2−
D3+
D3−
D4+
D4−
D5+
D5−
D6+
D6−
D7+
D7−
D8+
D8−
D9+
D9−
D10+
D10−
D11+
D11−
D12+
D12−
D13+
D13−
D14+
D14−
D15+
D15−
OR+
OR−
DCO+
DCO−
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0—True (LSB).
Channel A/Channel B LVDS Output Data 0—Complement (LSB).
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3—True.
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
Channel A/Channel B LVDS Output Data 4—Complement.
Channel A/Channel B LVDS Output Data 5—True.
Channel A/Channel B LVDS Output Data 5—Complement.
Channel A/Channel B LVDS Output Data 6—True.
Channel A/Channel B LVDS Output Data 6—Complement.
Channel A/Channel B LVDS Output Data 7—True.
Channel A/Channel B LVDS Output Data 7—Complement.
Channel A/Channel B LVDS Output Data 8—True.
Channel A/Channel B LVDS Output Data 8—Complement.
Channel A/Channel B LVDS Output Data 9—True.
Channel A/Channel B LVDS Output Data 9—Complement.
Channel A/Channel B LVDS Output Data 10—True.
Channel A/Channel B LVDS Output Data 10—Complement.
Channel A/Channel B LVDS Output Data 11—True.
Channel A/Channel B LVDS Output Data 11—Complement.
Channel A/Channel B LVDS Output Data 12—True.
Channel A/Channel B LVDS Output Data 12—Complement.
Channel A/Channel B LVDS Output Data 13—True.
Channel A/Channel B LVDS Output Data 13—Complement.
Channel A/Channel B LVDS Output Data 14—True.
Channel A/Channel B LVDS Output Data 14—Complement.
Channel A/Channel B LVDS Output Data 15—True (MSB).
Channel A/Channel B LVDS Output Data 15—Complement (MSB).
Channel A/Channel B LVDS Overrange Output—True.
Channel A/Channel B LVDS Overrange Output—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
SCLK/DFS
SDIO/DCS
CSB
Input
Input/output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
OEB
PDWN
Input
Input
Output Enable Input (Active Low) in External Pin Mode.
Power-Down Input in External Pin Mode. In SPI mode, this input can be configured
as power-down or standby.
DNC
N/A
Do Not Connect.
Rev. 0 | Page 10 of 12
Data Sheet
AD9650-EP
OUTLINE DIMENSIONS
0.75
0.60
0.45
1.00 REF
12.10
12.00 SQ
11.90
1.20
MAX
0.15
0.10
0.05
0.20
0.15
0.09
0.08
COPLANARITY
7°
3.5°
0°
80
61
1
60
60
SEATING
PLANE
1.05
1.00
0.95
61
80
1
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
BOTTOM VIEW
(PINS DOWN)
20
21
7.60
7.50 SQ
7.40
EXPOSED
PAD
41
40
(PINS UP)
41
40
VIEW A
0.50
BSC
LEAD PITCH
20
21
0.27
0.22
0.17
VIEW A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
07-09-2012-A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
Figure 7. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
12 mm × 12 mm (SV-80-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9650USVZ-105EP
AD9650USVZR7-105EP
1
Temperature Range
−55°C to +85°C
−55°C to +85°C
Package Description
80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
Z = RoHS Compliant Part.
Rev. 0 | Page 11 of 12
Package Option
SV-80-6
SV-80-6
AD9650-EP
Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11312-0-5/13(0)
Rev. 0 | Page 12 of 12