EUP7998 Sink/Source DDR Termination Regulator FEATURES DESCRIPTION z z z z z z The EUP7998 is a high performance linear regulator designed to provide power for termination of a DDR memory bus. It significantly reduces parts count, board space and overall system cost over previous switching solutions. The EUP7998 maintains a fast transient response using only 20μF or 30μF output capacitance. The EUP7998 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3 and Low Power DDR3/DDR4 VTT bus termination. The EUP7998 provides current and thermal limits to prevent damage to the linear regulator. Additionally, The EUP7998 generates an open-drain PGOOD signal to monitor the output regulation. An active high enable pin EN can pull VTT low, but REFOUT will remain active. A power savings advantage can be obtained in this mode through lower quiescent current. The EUP7998 is available in the 3mm × 3mm TDFN-10 and SOP-8 (EP) packages. z z z z z VLDOIN Input Voltage Range: 1.1V to 3.5V VIN Input Voltage Range: 2.375V to 5.5V Typically 3 × 10μF MLCCs stable for DDR Fast Load-Transient Response ±10mA Buffered Reference (REFOUT) Meet DDR, DDR2 JEDEC Specifications. Supports DDR3 and Low-Power DDR3/DDR4 VTT Applications Power-Good Window Comparator With Soft Start, UVLO and OCP Thermal Shutdown Available in 10-Pin 3mm × 3mm TDFN and SOP-8 (EP) packages RoHS Compliant and 100% Lead(Pb)-Free Halogen-Free APPLICATIONS z z z Notebook/Desktop/Server DDR Memory Termination Telecom/Datacom, GSM Base Station, LCD-TV/PDP-TV, Copier/Printer, Set-Top Box Typical Application Circuit Figure 1. For TDFN-10 package DS7998 Ver1.1 Aug. 2010 1 EUP7998 Typical Application Circuit (continued) Figure 2. For SOP-8(EP) package Pin Configurations Package Type Package Type Pin Configurations Pin Configurations SOP-8 (EP) TDFN-10 Pin Description PIN REFIN TDFN-10 1 SOP-8 (EP) 1 VLDOIN 2 2 VO 3 PGND 4 VOSNS 5 REFOUT 6 EN 7 GND PGOOD 8 9 VIN 10 DESCRIPTION External Reference Input Power Supply of the LDO. Internally connected to the output source MOSFET. Output of the LDO 3 9 Power Ground (Thermal pad) Voltage sense input for the LDO. Connect to positive terminal of the 4 output capacitor. Buffered Reference Output. The output of the unity-gain reference input 5 buffer sources and sinks over 10mA. Bypass REFOUT to GND with a 0.1μF ceramic capacitor. Enable Control Input. Active High Input. For DDR VTT application, 6 connect EN to SLP_S3. 7 Ground Open-Drain Power-Good Output Power Supply Input. Connect to the system supply voltage. Bypass VIN to 8 GND with a 1μF or 4.7μF ceramic capacitor. Note(1):PGND, GND and thermal pad must be connected together outside under thermal pad. DS7998 Ver1.1 Aug. 2010 2