LINER LT1970 500ma power op amp with adjustable precision current limit Datasheet

LT1970
500mA Power Op Amp with
Adjustable Precision Current Limit
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FEATURES
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DESCRIPTIO
The LT®1970 is a ±500mA power op amp with precise
externally controlled current limiting. Separate control
voltages program the sourcing and sinking current limit
sense thresholds with 2% accuracy. Output current may
be boosted by adding external power transistors.
±500mA Minimum Output Current
Independent Adjustment of Source and
Sink Current Limits
2% Current Limit Accuracy
Operates with Single or Split Supplies
Shutdown/Enable Control Input
Open Collector Status Flags:
Sink Current Limit
Source Current Limit
Thermal Shutdown
Fail Safe Current Limit and Thermal Shutdown
1.6V/µs Slew Rate
3.6MHz Gain Bandwidth Product
Fast Current Limit Response: 2MHz Bandwidth
Specified Temperature Range: – 40°C to 85°C
The circuit operates with single or split power supplies from
5V to 36V total supply voltage. In normal operation, the
input stage supplies and the output stage supplies are connected (VCC to V+ and VEE to V–). To reduce power dissipation it is possible to power the output stage (V+, V–) from
independent, lower voltage rails. The amplifier is unity-gain
stable with a 3.6MHz gain bandwidth product and slews at
1.6V/µs. The current limit circuits operate with a 2MHz response between the VCSRC or VCSNK control inputs and
the amplifier output.
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APPLICATIO S
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Open collector status flags signal current limit circuit
activation, as well as thermal shutdown of the amplifier. An
enable logic input puts the amplifier into a low power, high
impedance output state when pulled low. Thermal shutdown and a ±800mA fixed current limit protect the chip
under fault conditions.
Automatic Test Equipment
Laboratory Power Supplies
Motor Drivers
Thermoelectric Cooler Driver
The LT1970 is packaged in a 20-lead TSSOP package with
a thermally conductive copper bottom plate to facilitate
heat sinking.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
AV = 2 Amplifier with Adjustable ±500mA Full-Scale
Current Limit and Fault indication
VLIMIT
0V TO 5V
V
IOUT(LIMIT) = ± LIMIT
10 • RCS
VIN
Current Limited Sinewave Into 10Ω Load
15V
15V
3k
VCC
4V
+
V
VCSRC
+IN
VCSNK
ISNK
ISRC
TSD
OUT
LT1970
SENSE+
SENSE–
V–
–IN
VEE
COMMON
–15V
VLOAD
IOUT
2V
0V
RCS
1Ω
1/4W
– 2V
R1
10k
R2
10k
LOAD
VCSRC = 4V
VCSNK = 2V
RCS = 1Ω
20µs/DIV
1970 TA02
1970 TA01
1970f
1
LT1970
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage (VCC to VEE).................................... 36V
Positive High Current Supply (V+) .................. V– to VCC
Negative High Current Supply(V–) ................... VEE to V+
Amplifier Output (OUT) ..................................... V – to V+
Current Sense Pins
(SENSE+, SENSE–, FILTER) .......................... V – to V+
Logic Outputs (ISRC, ISNK, TSD) ....... COMMON to VCC
Input Voltage (–IN, +IN) .......... VEE – 0.3V to VEE + 36V
Input Current ....................................................... 10mA
Current Control Inputs
(VCSRC, VCSNK) ............. COMMON to COMMON + 7V
Enable Logic Input .............................. COMMON to VCC
COMMON ..................................................... VEE to VCC
Output Short-Circuit Duration ......................... Indefinite
Operating Temperature Range (Note 2) .. – 40°C to 85°C
Specified Temperature Range (Note 3) ... – 40°C to 85°C
Maximum Junction Temperature ......................... 150°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
VEE
1
20 VEE
V–
2
19 V+
OUT
3
18 TSD
SENSE+
4
17 ISNK
FILTER
5
SENSE–
6
VCC
7
14 COMMON
–IN
8
13 VCSRC
+IN
9
12 VCSNK
– +
VEE 10
LT1970CFE
16 ISRC
15 ENABLE
11 VEE
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 40°C/ W (NOTE 6)
UNDERSIDE METAL CONNECTED TO VEE
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. See Test Circuit for standard test conditions.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
200
600
800
1000
µV
µV
µV
–4
10
µV/°C
100
nA
Power Op Amp Characteristics
VOS
Input Offset Voltage
0°C < TA < 70°C
–40°C < TA < 85°C
●
●
Input Offset Voltage Drift (Note 4)
●
–10
VCM = 0V
●
–100
●
–600
IOS
Input Offset Current
IB
Input Bias Current
VCM = 0V
Input Noise Voltage
0.1Hz to 10Hz
3
µVP-P
en
Input Noise Voltage Density
1kHz
15
nV/√Hz
in
Input Noise Current Density
1kHz
3
pA/√Hz
RIN
Input Resistance
Common Mode
Differential Mode
CIN
Input Capacitance
Pin 8 and Pin 9 to Ground
VCM
Input Voltage Range
Typical
Guaranteed by CMRR Test
●
–14.5
–12.0
–12V < VCM < 12V
●
92
105
dB
●
●
●
●
90
110
90
110
100
130
100
130
dB
dB
dB
dB
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
= V– = –5V, V
–160
nA
500
100
= V+ = 3V to 30V
VEE
CC
VEE = V– = –5V, VCC = 30V, V+ = 2.5V to 30V
VEE = V– = –3V to – 30V, VCC = V+ = 5V
VEE = –30V, V– = –2.5V to –30V, VCC = V+ = 5V
kΩ
kΩ
6
pF
13.6
12.0
V
V
1970f
2
LT1970
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. See Test Circuit for standard test conditions.
SYMBOL
PARAMETER
CONDITIONS
AVOL
Large-Signal Voltage Gain
RL = 1k, –12.5V < VOUT < 12.5V
MIN
TYP
100
75
150
●
V/mV
V/mV
80
40
120
●
V/mV
V/mV
20
5
60
●
V/mV
V/mV
RL = 100Ω, –12.5V < VOUT < 12.5V
RL = 10Ω, –5V < VOUT < 5V, V+ = – V– = 8V
VOL
VOH
Output Sat Voltage Low
Output Sat Voltage High
MAX
UNITS
VOL = VOUT – V–
RL = 100, VCC = V+ = 15V, VEE = V– = –15V
RL = 10, VCC = – VEE = 15V, V+ = –V– = 5V
●
1.9
0.8
2.4
V
V
VOH = V+ – VOUT
RL = 100, VCC = V+ = 15V, VEE = V– = –15V
RL = 10, VCC = – VEE = 15V, V+ = –V– = 5V
●
1.7
1.0
2.2
V
V
500
–1000
800
– 800
1200
– 500
1.6
ISC
Output Short-Circuit Current
Output Low, RSENSE = 0Ω
Output High, RSENSE = 0Ω
SR
Slew Rate
–10V < VOUT < 10V, RL = 1k
0.7
FPBW
Full Power Bandwidth
VOUT = 10VPEAK (Note 5)
11
GBW
Gain Bandwidth Product
f = 10kHz
tS
Settling Time
0.01%, VOUT = 0V to 10V, AV = –1, RL = 1k
mA
mA
V/µs
kHz
3.6
MHz
µs
8
Current Sense Characteristics
VSENSE(MIN)
Minimum Current Sense Voltage
VCSRC = VCSNK = 0V
0.1
0.1
4
●
7
10
mV
mV
VSENSE(4%)
Current Sense Voltage 4% of Full Scale
VCSRC = VCSNK = 0.2V
●
15
20
25
mV
VSENSE(10%)
Current Sense Voltage 10% of Full Scale
VCSRC = VCSNK = 0.5V
●
45
50
55
mV
VSENSE(FS)
Current Sense Voltage 100% of Full Scale
VCSRC = VCSNK = 5V
●
490
480
500
500
510
520
mV
mV
–0.2
0.1
µA
IBI
Current Limit Control Input Bias Current
VCSRC, VCSNK Pins
●
–1
ISENSE–
SENSE–
0V < (VCSRC, VCSNK) < 5V
●
– 200
200
nA
Input Current
IFILTER
FILTER Input Current
0V < (VCSRC, VCSNK) < 5V
●
– 200
200
nA
ISENSE+
SENSE+ Input Current
VCSRC= VCSNK = 0V
VCSRC = 5V, VCSNK = 0V
VCSRC= 0V, VCSNK = 5V
VCSRC = VCSNK = 5V
●
●
●
●
–500
200
–300
–25
500
300
–200
25
nA
µA
µA
µA
●
– 0.1
0.1
%
Current Sense Change with Output Voltage VCSRC = VCSNK = 5V, –12.5V < VOUT < 12.5V
Current Sense Change with Supply Voltage
±0.05
±0.01
±0.05
±0.01
VCSRC = VCSNK = 5V, 6V < (VCC, V+) < 18V
2.5V < V+ < 18V, VCC = 18V
–18V < (VEE, V–) < –2.5V
–18V < V– < –2.5V, VEE = –18V
Current Sense Bandwidth
RCSF
250
–250
%
%
%
%
2
Resistance FILTER to SENSE–
●
750
MHz
1000
1250
Ω
1
µA
0.4
V
Logic I/O Characteristics
Logic Output Leakage ISRC, ISNK, TSD
V = 15V
●
Logic Low Output Level
I = 5mA
●
0.2
Logic Output Current Limit
●
25
VENABLE
Enable Logic Threshold
●
0.8
IENABLE
Enable Pin Bias Current
●
–1
1.6
mA
2.4
V
1
µA
1970f
3
LT1970
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. See Test Circuit for standard test conditions.
SYMBOL
PARAMETER
CONDITIONS
ISUPPLY
Total Supply Current
ICC
VCC Supply Current
ICC(STBY)
Supply Current Disabled
VCC, V+
VCC, V+
VCC, V+
MIN
tON
Turn-On Delay
(Note 7)
10
µs
tOFF
Turn-Off Delay
(Note 7)
10
µs
and V–, VEE Connected
and V–, VEE Separate
and V–, VEE Connected, VENABLE
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1970C is guaranteed functional over the operating
temperature range of – 40°C and 85°C.
Note 3: The LT1970C is guaranteed to meet specified performance from
0°C to 70°C. The LT1970C is designed, characterized and expected to
meet specified performance from – 40°C to 85°C but is not tested or QA
sampled at these temperatures.
●
≤ 0.8V
TYP
MAX
7
13
UNITS
mA
●
3
7
mA
●
0.6
1.5
mA
Note 4: This parameter is not 100% tested.
Note 5: Full power bandwidth is calculated from slew rate measurements:
FPBW = SR/(2 • π • VP)
Note 6: Thermal resistance varies depending upon the amount of PC board
metal attached to the device. If the maximum dissipation of the package is
exceeded, the device will go into thermal shutdown and be protected.
Note 7: Turn-on and turn-off delay are measured from VENABLE crossing
1.6V to the OUT pin at 90% of normal output voltage.
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TYPICAL PERFOR A CE CHARACTERISTICS
Warm-Up Drift VIO vs Time
Total Supply Current
vs Supply Voltage
Input Bias Current vs VCM
–100
VS = ±15V
TIME (100ms/DIV)
1970 G04
TOTAL SUPPLY CURRENT (mA)
0V
INPUT BIAS CURRENT (nA)
VOS • 1000 (50mV/DIV)
–120
–140
–IBIAS
–160
+IBIAS
–180
–200
– 220
–240
–260
–15 –12 –9 –6 –3 0 3 6 9 12 15
COMMON MODE INPUT VOLTAGE (V)
1970 G05
14
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
ICC + IV +
125°C
25°C
–55°C
IEE + IV –
–55°C
25°C
125°C
0
2
4
6
8 10 12 14
SUPPLY VOLTAGE (±V)
16
18
1970 G15
1970f
4
LT1970
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TYPICAL PERFOR A CE CHARACTERISTICS
Open-Loop Gain and Phase
vs Frequency
Supply Current vs Supply Voltage
IV+
IV–
IVCC
3.0
2.5
IVEE
2.0
1.5
1.0
TA = 25°C
VCC = V + = –VEE = –V –
0.5
0
2
4
6
8 10 12 14 16
SUPPLY VOLTAGE (±V)
60
60
90
58
80
56
50
OPEN-LOOP GAIN (dB)
3.5
100
18
20
GAIN
PHASE
40
70
30
60
20
50
10
40
0
30
–10
20
–20
10
–30
100
1k
10k 100k
1M
FREQUENCY (Hz)
10M
PHASE MARGIN (DEG)
SUPPLY CURRENT (mA)
4.0
Phase Margin vs Supply Voltage
70
0
100M
PHASE MARGIN (DEG)
4.5
AV = –1
RF = RG = 1k
TA = 25°C
VOUT = VS/2
54
52
50
48
46
44
42
40
0
4
8 12 16 20 24 28 32
TOTAL SUPPLY VOLTAGE (V)
1970 G18
1870 G16
Slew Rate vs Supply Voltage
1970 G21
Slew Rate vs Temperature
2.5
1.8
VS = ±15V
36
Large-Signal Response, AV = 1
FALLING
1.7
FALLING
2.0
10V
RISING
SLEW RATE (V/µs)
SLEW RATE (V/µs)
1.6
1.5
1.4
1.3
1.2
1.0
4
6
1.5
0V
1.0
–10V
0.5
AV = –1
RF = RG = 1k
TA = 25°C
1.1
RISING
RL = 1k
14
12
10
SUPPLY VOLTAGE (±V)
8
16
18
0
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
20µs/DIV
1970 G39
125
1970 G24
1970 G23
Large-Signal Response, AV = – 1
Small-Signal Response, AV = 1
Small-Signal Response, AV = – 1
RL = 1k
CL = 1000pF
RL = 1k
RL = 1k
CL = 1000pF
10V
0V
–10V
20µs/DIV
1970 G40
500ns/DIV
1970 G41
2µs/DIV
1970 G42
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LT1970
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TYPICAL PERFOR A CE CHARACTERISTICS
Undistorted Output Swing
vs Frequency
% Overshoot vs CLOAD
60
Full Range Current Sense
Transfer Curve
30
VS = ±15V
500
400
25
OUTPUT SWING (VP-P)
OVERSHOOT (%)
AV = 1
40
30
AV = –1
20
300
20
15
10
10
100
1k
10k
–500
100k
0
1
10
20
8
OUTPUT STAGE CURRENT (mA)
25
15
SOURCING
CURRENT
10
5
0
–5
SINKING
CURRENT
–10
4
5
1970 G50
Output Stage Quiescent Current
vs Supply Voltage
Low Level Current Sense
Transfer Curve
–15
IV+
6
125°C
25°C
4
–55°C
2
0
IV –
–55°C
–2
–4
25°C
–6
125°C
–8
–20
–10
0
0
25 50 75 100 125 150 175 200 225 250
VCSNK = VCSRR (mV)
2
4
6
8 10 12 14
SUPPLY VOLTAGE (±V)
TOTAL SUPPLY CURRENT, ICC + IV+ (µA)
800
ICC
4
125°C
25°C
–55°C
3
2
1
0
IEE
–1
–55°C
–2
25°C
–3
125°C
–4
2
4
6
8 10 12 14
SUPPLY VOLTAGE (±V)
16
18
1970 G81
VENABLE = 0V
85°C
700
25°C
600
–55°C
500
400
300
200
100
0
–5
0
18
Supply Current vs Supply Voltage
in Shutdown
Control Stage Quiescent Current
vs Supply Voltage
5
16
1970 G80
1970 G51
SUPPLY CURRENT (mA)
3
2
VCSNK = VCSRC (V)
1970 G47
1970 G44
VSENSE (mV)
SINKING
CURRENT
–400
1k
10k
FREQUENCY (Hz)
CLOAD (pF)
–25
0
–100
–300
VS = ±15V
AV = –5
1% THD
0
100
0
100
–200
5
10
SOURCING
CURRENT
200
VSENSE (mV)
50
0
2
4
8 10 12 14
6
SUPPLY VOLTAGE (V)
16
18
1970 G82
1970f
6
LT1970
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PI FU CTIO S
VEE (Pins 1, 10, 11, 20, Package Base): Minus Supply
Voltage. VEE connects to the substrate of the integrated
circuit die, and therefore must always be the most negative
voltage applied to the part. Decouple VEE to ground with a
low ESR capacitor. VEE may be a negative voltage or it may
equal ground potential. Any or all of the VEE pins may be
used. Unused VEE pins must remain open.
V– (Pin 2): Output Stage Negative Supply. V– may equal
VEE or may be smaller in magnitude. Only output stage
current flows out of V–, all other current flows out of VEE.
V– may be used to drive the base/gate of an external power
device to boost the amplifier’s output current to levels
above the rated 500mA of the on-chip output devices.
Unless used to drive boost transistors, V– should be
decoupled to ground with a low ESR capacitor.
OUT (Pin 3): Amplifier Output. The OUT pin provides the
force function as part of a Kelvin sensed load connection.
OUT is normally connected directly to an external load
current sense resistor and the SENSE+ pin. Amplifier
feedback is directly connected to the load and the other
end of the current sense resistor. The load connection is
also wired directly to the SENSE– pin to monitor the load
current.
The OUT pin is current limited to ±800mA typical. This
current limit protects the output transistor in the event
that connections to the external sense resistor are opened
or shorted which disables the precision current limit
function.
SENSE + (Pin 4): Positive Current Sense Pin. This lead is
normally connected to the driven end of the external sense
resistor. Positive current limit operation is activated when
the voltage VSENSE (VSENSE + – VSENSE –) equals 1/10 of
the programming control voltage at VCSRC (Pin 13). Negative current limit operation is activated when the voltage
VSENSE equals –1/10 of the programming control voltage
at VCSNK (Pin 12).
FILTER (Pin 5): Current Sense Filter Pin. This pin is
normally not used and should be left open in most applications. When very large capacitive loads are driven, a
filter capacitor connected between FILTER and SENSE+
will reduce overshoot as the amplifier enters current
limiting mode. The filter time constant is set by an internal
1k resistor and the external filter capacitor. Capacitor
values of 1nF to 100nF are most effective at reducing
overshoot.
SENSE – (Pin 6): Negative Current Sense Pin. This pin is
normally connected to the load end of the external sense
resistor. Positive current limit operation is activated when
the voltage VSENSE (VSENSE + – VSENSE –) equals 1/10 of
the programming control voltage at VCSRC (Pin 13).
Negative current limit operation is activated when the
voltage VSENSE equals –1/10 of the programming control
voltage at VCSNK (Pin 12).
VCC (Pin 7): Positive Supply Voltage. All circuitry except
the output transistors draw power from VCC. Total supply
voltage from VCC to VEE must be between 3.5V and 36V.
VCC must always be greater than or equal to V+. VCC should
always be decoupled to ground with a low ESR capacitor.
– IN (Pin 8): Inverting Input of Amplifier. – IN may be any
voltage from VEE – 0.3V to VEE + 36V. – IN and + IN remain
high impedance at all times to prevent current flow into the
inputs when current limit mode is active. Care must be
taken to insure that – IN or + IN can never go to a voltage
below VEE – 0.3V even during transient conditions or
damage to the circuit may result. A Schottky diode from
VEE to – IN can provide clamping if other elements in the
circuit can allow – IN to go below VEE.
+ IN (Pin 9): Noninverting Input of Amplifier. + IN may be
any voltage from VEE – 0.3V to VEE + 36V. – IN and + IN
remain high impedance at all times to prevent current flow
into the inputs when current limit mode is active. Care
must be taken to insure that – IN or + IN can never go to a
voltage below VEE – 0.3V even during transient conditions
or damage to the circuit may result. A Schottky diode from
VEE to +IN can provide clamping if other elements in the
circuit can allow + IN to go below VEE.
1970f
7
LT1970
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PI FU CTIO S
VCSNK (Pin 12): Sink Current Limit Control Voltage Input.
The current sink limit amplifier will activate when the
sense voltage between SENSE+ and SENSE– equals
–1.0 • VVCSNK/10. VCSNK may be set between VCOMMON
and VCOMMON + 6V. The transfer function between VCSNK
and VSENSE is linear except for very small input voltages at
VCSNK < 60mV. VSENSE limits at a minimum set point of
4mV typical to insure that the sink and source limit
amplifiers do not try to operate simultaneously. To force
zero output current, the ENABLE pin can be taken low.
VCSRC (Pin 13): Source Current Limit Control Voltage
Input. The current source limit amplifier will activate
when the sense voltage between SENSE+ and SENSE–
equals VVCSRC/10. VCSRC may be set between VCOMMON
and VCOMMON + 6V. The transfer function between VCSRC
and VSENSE is linear except for very small input voltages
at VCSRC < 60mV. VSENSE limits at a minimum set point
of 4mV typical to insure that the sink and source limit
amplifiers do not try to operate simultaneously. To force
zero output current, the ENABLE pin can be taken low.
COMMON (Pin 14): Control and ENABLE inputs and flag
outputs are referenced to the COMMON pin. COMMON
may be at any potential between VEE and VCC – 3V. In
typical applications, COMMON is connected to ground.
ENABLE (Pin 15): ENABLE Digital Input Control. When
taken low this TTL-level digital input turns off the amplifier
output and drops supply current to less than 1mA. Use the
ENABLE pin to force zero output current. Setting VCSNK =
VCSRC = 0V allows IOUT = ±4mV/RSENSE to flow in or out
of VOUT.
ISRC (Pin 16): Sourcing Current Limit Digital Output Flag.
ISRC is an open collector digital output. ISRC pulls low
whenever the sourcing current limit amplifier assumes
control of the output. This pin can sink up to 10mA of
current. The current limit flag is off when the source
current limit is not active. ISRC, ISNK and TSD may be
wired “OR” together if desired. ISRC may be left open if
this function is not monitored.
ISNK (Pin 17): Sinking Current Limit Digital Output Flag.
ISNK is an open collector digital output. ISNK pulls low
whenever the sinking current limit amplifier assumes
control of the output. This pin can sink up to 10mA of
current. The current limit flag is off when the source
current limit is not active. ISRC, ISNK and TSD may be
wired “OR” together if desired. ISNK may be left open if
this function is not monitored.
TSD (Pin 18): Thermal Shutdown Digital Output Flag. TSD
is an open collector digital output. TSD pulls low whenever
the internal thermal shutdown circuit activates, typically at
a die temperature of 160°C. This pin can sink up to 10mA
of output current. The TSD flag is off when the die
temperature is within normal operating temperatures.
ISRC, ISNK and TSD may be wired “OR” together if
desired. ISNK may be left open if this function is not
monitored. Thermal shutdown activation should prompt
the user to evaluate electrical loading or thermal environmental conditions.
V+ (Pin 19): Output Stage Positive Supply. V + may equal
VCC or may be smaller in magnitude. Only output stage
current flows through V +, all other current flows into VCC.
V + may be used to drive the base/gate of an external power
device to boost the amplifier’s output current to levels
above the rated 500mA of the on-chip output devices.
Unless used to drive boost transistors, V + should be
decoupled to ground with a low ESR capacitor.
Package Base: The exposed backside of the package is
electrically connected to the VEE pins on the IC die. The
package base should be soldered to a heat spreading pad
on the PC board that is electrically connected to VEE.
1970f
8
LT1970
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BLOCK DIAGRA
A D TEST CIRCUIT
RFB
1k
VCC
7
V+
19
9
+
–
+
VIN
Q1
10k
–IN
OUT
1×
GM1
8
RG
1k
+IN
15V
3
Q2
PS1
–
ISNK
17
15V
18
15
5V
12
D1
ENABLE
VCSNK
+
–
ENABLE
VCSNK
D2
13
+
–
ISINK
TSD
–
10k
ISRC
VSNK
SENSE+
+
16
–
10k
VCSRC
FILTER
VSRC
SENSE –
RFIL
1k
ISRC
VCSRC
5
6
RLOAD
1k
2
VEE
COMMON
4
V–
+
14
RCS
1Ω
2, 10, 11, 20
–15V
1970TC
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APPLICATIO S I FOR ATIO
The LT1970 power op amp with precision controllable
current limit is a flexible voltage and current source
module. The drawing on the front page of this data sheet
is representative of the basic application of the circuit,
however many alternate uses are possible with proper
understanding of the subcircuit capabilities.
CIRCUIT DESCRIPTION
Main Operational Amplifier
Subcircuit block GM1, the 1X unity-gain current buffer
and output transistors Q1 and Q2 form a standard operational amplifier. This amplifier has ±500mA current output
capability and a 3.6MHz gain bandwidth product. Most
applications of the LT1970 will use this op amp in the main
signal path. All conventional op amp circuit configurations
are supported. Inverting, noninverting, filter, summation
or nonlinear circuits may be implemented in a conventional manner. The output stage includes current limiting
at ±800mA to protect against fault conditions. The input
stage has high differential breakdown of 36V minimum
between – IN and + IN. No current will flow at the inputs
when differential input voltage is present. This feature is
important when the precision current sense amplifiers
“ISINK” and “ISRC” become active.
Current Limit Amplifiers
Amplifier stages “ISINK” and “ISRC” are very high transconductance amplifier stages with independently controlled
offset voltages. These amplifiers monitor the voltage
between input pins SENSE+ and SENSE– which usually
sense the voltage across a small external current sense
resistor. The transconductance amplifiers outputs connect to the same high impedance node as the main input
stage GM1 amplifier. Small voltage differences between
SENSE+ and SENSE–, smaller than the user set VCSNK/10
and VCSRC/10 in magnitude, cause the current limit amplifiers to decouple from the signal path. This is functionally
indicated by diodes D1 and D2 in the Block Diagram. When
the voltage VSENSE increases in magnitude sufficient to
equal or overcome one of the offset voltages VCSNK/10 or
VCSRC/10, the appropriate current limit amplifier becomes
1970f
9
LT1970
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APPLICATIO S I FOR ATIO
active and because of its very high transconductance,
takes control from the input stage, GM1. The output
current is regulated to a value of IOUT = VSENSE /RSENSE =
(VCSRC or VCSNK)/(10 • RSENSE).
Most applications will connect pins SENSE+ and OUT together, with the load on the opposite side of the external
sense resistor and pin SENSE–. Feedback to the inverting
input of GM1 should be connected from SENSE– to – IN.
The common mode range of stages “ISINK” and “ISRC”
allow other connections. Ground side sensing of load
current may be employed by connecting the load between
pins OUT and SENSE+. Pin SENSE– would be connected to
ground in this instance. Load current would be regulated
in exactly the same way as the conventional connection.
However, voltage mode accuracy would be degraded in
this case due to the voltage across RSENSE.
Creative applications are possible where pins SENSE+ and
SENSE– monitor a parameter other than load current. The
operating principle that at most one of the current limit
stages may be active at one time, and that when active, the
current limit stages take control of the output from GM1,
can be used for many different signals.
Current Limit Threshold Control Buffers
Input pins VCSNK and VCSRC are used to set the response
thresholds of current limit amplifiers “ISINK” and “ISRC”.
Each of these inputs may be independently driven by a
voltage of 0V to 5V above the COMMON reference pin. The
0V to 5V input voltage is attenuated by a factor of 10 and
applied as an offset to the appropriate current limit amplifier. AC signals may be applied to these pins. The AC
bandwidth from a VC pin to the output is typically 2MHz.
The transfer function from VC to the associated VOS is
linear from about 0.1V to 5V in, or 10mV to 500mV at the
current limit amplifier inputs. An intentional nonlinearity is
built into the transfer functions at low levels. This nonlinearity insures that both the sink and source limit amplifiers
cannot become active simultaneously. Simultaneous activation of the limit amplifiers could result in uncontrolled
outputs. As shown in the Typical Performance Characteristics curves, the control inputs have a “hockey stick”
shape, to keep the minimum limit threshold at 4mV for
each limit amplifier.
ENABLE Control
The ENABLE input pin puts the LT1970 into a low supply
current, high impedance output state. The ENABLE pin
responds to TTL threshold levels with respect to the
COMMON pin. Pulling the ENABLE pin low is the best way
to force zero current at the output. Setting VCSNK = VCSRC
= 0V allows the output current to remain as high as
±4mV/RSENSE.
Operating Status Flags
The LT1970 has three digital output indicators; TSD, ISRC
and ISNK. These outputs are open collector drivers referred to the COMMON pin. The outputs have 36V capabilities and can sink in excess of 10mA. ISRC and ISNK
indicate activation of the associated current limit amplifier. The TSD output indicates excessive die temperature
has caused the circuit to enter thermal shutdown. The
three digital outputs may be wire “OR’d” together, monitored individually or left open. These outputs do not affect
circuit operation, but provide an indication of the present
operational status of the chip.
THERMAL MANAGEMENT
Minimizing Power Dissipation
The LT1970 can operate with up to 36V total supply
voltage with output currents up to ±500mA. The amount
of power dissipated in the chip could approach 18W under
worst-case conditions. This amount of power will cause
die temperature to rise until the circuit enters thermal
shutdown. While the thermal shutdown feature prevents
damage to the circuit, normal operation is impaired.
Thermal design of the LT1970 operating environment is
essential to getting maximum utility from the circuit.
The first concern for thermal management is minimizing
the heat which must be dissipated. The separate power
pins V+ and V– can be a great aid in minimizing on-chip
power. The output pin can swing to within 1.0V of V+ or V–
even under maximum output current conditions. Using
separate power supplies, or off chip dissipative elements,
to set V+ and V– to their minimum values for the required
output swing will minimize power dissipation. The supplies VCC and VEE may also be reduced to a minimal value,
1970f
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LT1970
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APPLICATIO S I FOR ATIO
but these supply pins do not carry high currents, and the
power saving is much less. VCC and VEE must be greater
than the maximum output swing by 2V or more.
and reducing peaking. The current sense resistor, usually
connected between the output pin and the load can serve
as a part of the decoupling resistance.
When V – and V+ are provided separately from VCC and VEE,
care must be taken to insure that V– and V+ are always less
than or equal to the main supplies in magnitude. Protection Schottky diodes may be required to insure this in all
cases, including power on/off transients.
Operation with reduced V + and V – supplies does not affect
any performance parameters except maximum output
swing. All DC accuracy and AC performance specifications
guaranteed with VCC = V + and VEE = V – are still valid within
the reduced signal swing range.
Very large capacitive loads above 1µF can also cause
transient overshoots when the current limiting circuits
activate. The FILTER pin is provided to assist in controlling
this problem. Should load capacitance cause transient
overshoot, a 1nF to 100nF capacitor between the FILTER
and SENSE– pins will minimize the overshoot. The best
value of capacitor to use in this situation will likely require
some empirical evaluation, as the optimum is a complex
function of output current, load resistance, sense resistor
and load capacitance.
Heat Sinking
Inductive Loads
The power dissipated in the LT1970 die must have a path
to the environment. With 100°C/W thermal resistance in
free air with no heat sink, the package power dissipation is
limited to only 1W. The 20-pin TSSOP package with
exposed copper underside is an efficient heat conductor if
it is effectively mounted on a PC board. Thermal resistances as low as 40°C/W can be obtained by soldering the
bottom of the package to a large copper pattern on the PC
board. For operation at 85°C, this allows up to 1.625W of
power to be dissipated on the LT1970. At 25°C operation,
up to 3.125W of power dissipation can be achieved. The
PC board heat spreading copper area must be connected
to VEE.
Load inductance is usually not a problem at the outputs of
operational amplifiers, but the LT1970 can be used as a
high output impedance current source. This condition
may be the main operating mode, or when the circuit
enters a protective current limit mode. Just as load capacitance degrades the phase margin of normal op amps, load
inductance causes a peaking in the loop response of the
feedback controlled current source. The inductive load
may be caused by long lead lengths at the amplifier output.
If the amplifier will be driving inductive loads or long lead
lengths (greater than 4 inches) a 500pF capacitor from the
SENSE– pin to the ground plane will cancel the inductive
load and insure stability.
Supply Bypassing
DRIVING REACTIVE LOADS
Capacitive Loads
The LT1970 is much more tolerant of capacitive loading
than most operational amplifiers. In a worst-case configuration as a voltage follower, the circuit is stable for capacitive loads less than 2.5nF. Higher gain configurations
improve the CLOAD handling. If very large capacitive loads
are to be driven, a resistive decoupling of the amplifier
from the capacitive load is effective in maintaining stability
The LT1970 can supply large currents from the power
supplies to a load at frequencies up to 4MHz. Power supply
impedance must be kept low enough to deliver these
currents without causing supply rails to droop. Low ESR
capacitors, such as 0.1µF or 1µF ceramics, located close
to the pins are essential in all applications. When large,
high speed transient currents are present additional capacitance may be needed near the chip. Check supply rails
with a scope and if signal related ripple is seen on the
supply rail, increase the decoupling capacitor as needed.
1970f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT1970
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TYPICAL APPLICATIO
AV = – 1 Amplifier with Discrete Power Devices to Boost Output Current to 5A
VCC
15V
CURRENT LIMIT
CONTROL VOLTAGE
0V TO 5V
10µF
100Ω
0.1µF
IRF9640
1k
VCC
ENABLE
VCSRC
+IN
VCSNK
V+
LT1970
–IN
SENSE+
SENSE–
COMMON
V–
100Ω
OUT
100Ω
RCS
0.1Ω
5W
VEE
LOAD
2.2k
2.2k
VIN
IRF9540
100Ω
VEE
–15V
10µF
0.1µF
1970 TA03
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PACKAGE DESCRIPTIO
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663,
Exposed Pad Variation CA)
6.60 ±0.10
4.50 ±0.10
0.45 ±0.05
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD
1.15
(.0453)
MAX
4.30 – 4.48*
(.169 – .176)
6.40 – 6.60*
(.252 – .260)
5.2
(.205)
20 1918 17 16 15 14 13 12 11
0° – 8°
0.105 – 0.180
(.0041 – .0071)
0.65
(.0256)
BSC
0.50 – 0.70
(.020 – .028)
0.195 – 0.30
(.0077 – .0118)
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
0.05 – 0.15
PACKAGE
(.002 – .006)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3.0
6.25 – 6.50
(.118) (.246 – .256)
1 2 3 4 5 6 7 8 9 10
FE20 TSSOP 1101
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .150mm (.006") PER SIDE
RELATED PARTS
PART NUMBER
LT1010
LT1206
LT1210
DESCRIPTION
Fast ±150mA Power Buffer
250mA/60MHz Current Feedback Amplifier
1.1A/35MHz Current Feedback Amplifier
COMMENTS
Shutdown Mode, Adjustable Supply Current
Stable with CL = 10,000pF
1970f
12
Linear Technology Corporation
LT/TP 0102 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2002
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