LP5904 www.ti.com SNVS637G – MARCH 2011 – REVISED APRIL 2013 Ultra Low Noise, 200 mA Linear Regulator for RF/Analog Circuits - Requires No Bypass Capacitor Check for Samples: LP5904 FEATURES PACKAGE • • 1 • • • • Stable with 1.0 µF Ceramic Input and Output Capacitors No Noise Bypass Capacitor Required Remote Output Capacitor Placement Thermal-overload and Short-circuit Protection –40°C to +125°C Junction Temperature Range for Operation DESCRIPTION The LP5904 is a linear regulator capable of supplying 200 mA output current. Designed to meet the requirements of RF/ Analog circuits, the LP5904 device provides low noise, high PSRR, low quiescent current, and low line transient response figures. Using new innovative design techniques the LP5904 offers class-leading device noise performance without a noise bypass capacitor and the ability for remote output capacitor placement. An active pulldown circuit with a 280Ω resistor is wired from the output to ground pins to quickly discharge output when the device is disabled (VEN = low). APPLICATIONS • • • Cellular Phones PDA Handsets Wireless LAN Devices KEY SPECIFICATIONS • • • • • • • • • • 4-Bump DSBGA (lead free) 0.815 mm × 0.815 mm × 0.600 mm The device is designed to work with a 1.0 µF input and a 1.0 µF output ceramic capacitor. (No Bypass Capacitor is required.) Input Voltage Range … 2.2V to 5.5V Output Voltage Range … 1.2V to 4.4V Output Current … 200 mA Low Output Voltage Noise at 200 mA … 6.5µVRMS PSRR … 78 dB at 1kHz Output Voltage Tolerance … ± 2% Virtually Zero IQ (Disabled) … <1 µA Very Low IQ (Enabled) … 11 µA Startup Time … 85 µs Low Dropout … 95 mV typ The device is available in a DSBGA package. For other package options contact your local TI sales office. This device is available between 1.2V and 4.4V in 25 mV steps. Please contact Texas Instruments Sales for specific voltage option needs. TYPICAL APPLICATION CIRCUIT VOUT VIN INPUT 1.0 PF OUTPUT 1 PF LP5904 ENABLE VEN GND GND SVA-30110401 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated LP5904 SNVS637G – MARCH 2011 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAMS VIN A1 VOUT A2 VOUT A2 VIN A1 B1 B2 GND B2 GND VEN VEN B1 BOTTOM VIEW TOP VIEW SVA-30110402 Note: The actual physical placement of the package marking will vary from part to part. The package marking “A” designates the date code, and will vary in production. Figure 1. 4-Bump Thin DSBGA Package Package Number YFQ0004AAA PIN DESCRIPTIONS PIN DESCRIPTION NAME NO. A1 VIN A2 VOUT B1 VEN Enable input; disables the regulator when ≤ 0.4V. Enables the regulator when ≥ 1.2V. An internal 1MΩ pulldown resistor connects this input to ground. B2 GND Common ground. Input voltage supply. A 1.0 µF capacitor should be connected at this input. Output voltage. A 1.0 µF Low ESR capacitor should be connected to this pin. Connect this output to the load circuit. An internal 280Ω discharge resistor prevents a charge remaining on VOUT when disabled. ORDERING INFORMATION DSBGA PACKAGE (LEAD FREE) (1) OUTPUT VOLTAGE (V) 3000 TAPE AND REEL 1.2 LP5904TME-1.2/NOPB LP5904TMX-1.2/NOPB 1.8 (2) LP5904TME-1.8/NOPB LP5904TMX-1.8/NOPB (2) LP5904TME-2.5/NOPB LP5904TMX-2.5/NOPB 2.6 (2) LP5904TME-2.6/NOPB LP5904TMX-2.6/NOPB 2.8 LP5904TME-2.8/NOPB LP5904TMX-2.8/NOPB 2.5 2.85 LP5904TME-2.85/NOPB LP5904TMX-2.85/NOPB 3.0 (2) LP5904TME-3.0/NOPB LP5904TMX-3.0/NOPB 3.1 LP5904TME-3.1/NOPB LP5904TMX-3.1/NOPB (2) LP5904TME-3.2/NOPB LP5904TMX-3.2/NOPB 3.4 (2) LP5904TME-3.4/NOPB LP5904TMX-3.4/NOPB 3.2 (1) (2) 2 SUPPLIED AS 250 TAPE AND REEL Contact your local TI Sales Office for availability of other voltage options. Not yet released — contact TI sales office for sample availability. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 LP5904 www.ti.com SNVS637G – MARCH 2011 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) (3) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN Input Voltage –0.3 6.0 V VOUT Output Voltage –0.3 to (VIN + 0.3V) 6.0 V VEN Enable Input Voltage –0.3 to (VIN + 0.3V) 6.0 V 150 °C 150 °C 260 °C 2 kV 200 V Continuous Power Dissipation (4) Internally Limited Junction Temperature (TJMAX) Storage Temperature Range –65 Maximum Lead Temperature (Soldering, 10 sec.) ESD Rating (5) (1) (2) (3) (4) (5) Human Body Model Machine Model If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. Internal thermal shutdown circuitry protects the device from permanent damage. The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 OPERATING RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) MIN VIN Input Voltage Range VEN Enable Voltage Range Recommended Load Current (3) NOM MAX UNIT 2.2 5.5 V 0 to (VIN + 0.3) 5.5 V 0 200 mA TJ Junction Temperature Range –40 +125 °C TA Ambient Temperature Range (3) –40 +85 °C (1) (2) (3) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). See applications section. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER θJA (1) (2) Junction to Ambient Thermal Resistance (1) MAX UNIT JEDEC Board (DSBGA) (2) TEST CONDITIONS MIN TYP 119.6 °C/W 4L Cellphone Board (DSBGA) 186.5 °C/W Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Detailed description of the board can be found in JESD51-7 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 3 LP5904 SNVS637G – MARCH 2011 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (1) (2) Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the full operating junction temperature range (–40°C ≤ TJ ≤ +125°C). Unless otherwise noted, specifications apply to the LP5904 Typical Application Circuit with: VIN = VOUT (NOM) + 1.0V, VEN = 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, IOUT = 1.0 mA. PARAMETER VIN TEST CONDITIONS Input Voltage Output Voltage Tolerance ΔVOUT Line Regulation ILOAD VIN = (VOUT(NOM) + 1.0V) to 5.5V, IOUT = 1mA to 200 mA MIN –2 2 % VIN = (VOUT(NOM) + 1.0V) to 5.5V, IOUT = 1 mA 0.16 IOUT = 1mA to 200 mA Load Current See %/V 0.002 (3) 0 Ground Current (5) IG VDO Dropout Voltage (6) ISC Short Circuit Current Limit Power Supply Rejection Ratio (8) PSRR eN Output Noise Voltage (8) TSHUTDOWN Thermal Shutdown %/mA 200 200 VEN = 1.2V, IOUT = 0 mA Quiescent Current (4) 11 20 VEN = 1.2V, IOUT = 200 mA 250 325 VEN = 0.3V (Disabled) 0.2 1.0 IOUT = 0 mA (VEN = 1.2V) 12.2 IOUT = 100 mA 45 IOUT = 200 mA 95 See (7) 220 88 f = 1 kHz, IOUT = 10 mA 80 f = 10 kHz, IOUT = 10 mA 70 f = 100 kHz, IOUT = 10 mA 50 f = 2MHz, IOUT = 10 mA 30 IOUT = 1mA 10 IOUT = 200 mA 6.5 Temperature 150 µA mV mA dB µVRMS 160 Hysteresis mA µA 450 f = 100 Hz, IOUT = 10 mA BW = 10 Hz to 100 kHz UNIT V 0.06 Load Regulation MAX 5.5 VIN = (VOUT(NOM) + 1.0V) to 5.0V, IOUT = 1 mA Maximum Output Current IQ TYP 2.2 °C 15 LOGIN INPUT THRESHOLDS VIL Low Input Threshold (VEN) VIN = 2.2V to 5.5V VIH High Input Threshold (VEN) VIN = 2.2V to 5.5V IEN Input Current at VEN Pin (9) (1) (2) (3) (4) (5) (6) (7) (8) (9) 4 0.4 1.2 V V VEN = 5.5V and VIN = 5.5V 5.5 VEN = 0.0V and VIN = 5.5V 0.001 µA All voltages are with respect to the potential at the GND pin. Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not specified, but do represent the most likely norm. The device maintains a stable, regulated output voltage without a load current. Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. This specification does not apply for input voltages below 2.2V. Short Circuit Current is measured with VOUT pulled to 0V and VIN worst case = 5.5V. This specification is ensured by design. There is a 1MΩ resistor between VEN and ground on the device. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 LP5904 www.ti.com SNVS637G – MARCH 2011 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS(1)(2) (continued) Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the full operating junction temperature range (–40°C ≤ TJ ≤ +125°C). Unless otherwise noted, specifications apply to the LP5904 Typical Application Circuit with: VIN = VOUT (NOM) + 1.0V, VEN = 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, IOUT = 1.0 mA. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TRANSIENT CHARACTERISTICS Line Transient VIN = (VOUT(NOM) + 1.0V) to (VOUT(NOM) + 1.6V) in 30 µs, IOUT = 1mA (10) –2 mV VIN = (VOUT(NOM) + 1.6V) to (VOUT(NOM) + 1.0V) in 30 µs, IOUT = 1mA ΔVOUT IOUT = 1mA to 200 mA in 10 µs Load Transient (10) 2 –50 IOUT = 200 mA to 1mA in 10 µs mV 50 Overshoot on Startup (10) Stated as a percentage of nominal VOUT Turn-on Time To 95% of VOUT(NOM) 85 2 % 300 µs (10) This specification is ensured by design. OUTPUT AND INPUT CAPACITORS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS CIN Input Capacitance (2) COUT Output Capacitance (2) ESR Output/Input Capacitance (2) (1) (2) Capacitance for stability MIN (1) TYP 0.5 1.0 0.5 1.0 5 MAX UNIT 10 500 µF mΩ Note: The minimum capacitance should be greater than 0.5 μF over the full range of operating conditions. The capacitor tolerance should be 30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application should be considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however capacitor types X5R, Y5V and Z5U may be used with consideration of the application and conditions. This specification is ensured by design. BLOCK DIAGRAM IN OUT REFERENCE FILTER + Rf VREFC Cf + 280W A special integrated filter for noise suppression Bandgap VEN 1.2V SVA-30110406 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 5 LP5904 SNVS637G – MARCH 2011 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN = 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA = 25°C. Iq vs VIN 50 Ground Current vs IOUT 250 -40°C 25°C 85°C 125°C 45 GROUND CURRENT ( A) 40 IQ( A) 35 30 Dropout Region 25 20 15 10 200 150 100 50 5 0 0 2.2 2.7 3.2 3.7 4.2 VIN(V) 4.7 5.2 5.7 0 50 100 150 IOUT(mA) 200 250 SVA-30110460 350 Figure 3. Ground Current vs IOUT VOUT Variation vs IOUT 1.000% VIN = 3.0V VIN = 3.8V VIN = 4.2V VIN = 5.5V 300 GROUND CURRENT ( A) SVA Figure 2. 0.500% VOUT VARIATION 250 200 150 100 0.000% 25oC 100oC -40oC -0.5000% 85oC 50 0 -1.000% 0 50 100 150 200 IOUT(mA) 250 0 300 50 100 150 200 LOAD CURRENT (mA) SV SVA-30110403 2.840 Figure 5. VOUT vs VIN VOUT vs IOUT 2.840 50 A 500 A 1mA 10 mA 100 mA 200 mA VOUT(V) 2.800 2.800 2.780 2.780 2.760 2.760 2.740 3.5 2.740 4.0 4.5 VIN(V) Figure 6. 6 VIN = 3.8V VIN = 5.0V VIN = 5.5V 2.820 VOUT(V) 2.820 Figure 4. 5.0 5.5 SVA Submit Documentation Feedback 0 50 100 IOUT(mA) 150 200 Figure 7. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 LP5904 www.ti.com SNVS637G – MARCH 2011 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN = 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA = 25°C. VOUT vs IOUT 2.840 VOUT(V) 2.820 Startup, No Load -40°C 25°C 85°C 100°C 2.800 2.780 2.760 2.740 0 20 40 60 80 100120140160180200 IOUT(mA) OVER TEMPERATURE SVA-30110442 Figure 8. Figure 9. Startup, Load = 28Ω Startup, Load = 14Ω SVA-30110443 SVA-30110444 Figure 10. Figure 11. Load Transient, Load = 1mA to 200mA, VOUT = 2.8V Line Transient Load = 1mA, VOUT = 2.8 at VIN Rising Edge VOUT VIN 1V/DIV 10 mV/ DIV VOUT 40 Ps/DIV SVA-30110445 Figure 12. SVA-30110412 Figure 13. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 7 LP5904 SNVS637G – MARCH 2011 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN = 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA = 25°C. Line Transient Load = 1mA, VOUT = 2.8 at VIN Falling Edge Line Transient Load = 200 mA, VOUT = 2.8 at VIN Rising Edge 1V/DIV VIN VIN 1V/DIV 10 mV/ DIV VOUT 10 mV/ DIV VOUT 40 Ps/DIV 40 Ps/DIV SVA-30110413 SVA-30110414 Figure 14. Figure 15. Line Transient Load = 200 mA, VOUT = 2.8 at VIN Falling Edge Dropout Voltage vs Load Current 120 100 VIN 10 mV/ DIV VOUT DROPOUT (mV) 1V/DIV 80 60 40 20 40 Ps/DIV 0 SVA-30110415 0 50 100 IOUT(mA) 150 200 SVA-30110466 Figure 16. Figure 17. PSRR Output Noise Spectral Density, VOUT = 2.8V Load = 0mA Load = 1mA Load = 50mA 10 V/¥(Hz) 1 .1 .01 .001 10 100 1000 10000 FREQUENCY (Hz) 100000 SVA-30110446 Figure 18. 8 Figure 19. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 LP5904 www.ti.com SNVS637G – MARCH 2011 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN = 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA = 25°C. Turn On Time, 1 mA Load VOUT = 2.8V, VIN = 3.93V (Battery) Turn OFF Time, no Load, VOUT = 3.3V VEN = VIN VOUT 1V/DIV VOUT 1V/DIV VEN 1A/DIV IOUT 1V/DIV 1V/DIV IIN 2A/DIV 200 Ps/DIV 20 Ps/DIV SVA-30110418 SVA-30110416 Figure 20. Figure 21. Turn OFF Time, 1 mA Load VOUT = 3.3V Turn OFF Time, 200 mA Load VOUT = 3.3V 1V/DIV VOUT 1V/DIV VEN 1A/DIV IOUT 1V/DIV VOUT 1V/DIV VEN 1A/DIV IOUT 200 Ps/DIV 200 Ps/DIV SVA-30110420 SVA-30110419 Figure 22. Figure 23. Turn OFF Time, VEN = VIN at No Load VOUT = 3.3V Turn OFF Time, VEN = VIN at 200 mA VOUT = 3.3V 1V/DIV 1V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN = VIN IOUT 2A/DIV VEN = VIN IOUT 2A/DIV 10 Ps/DIV 10 Ps/DIV SVA-30110421 Figure 24. SVA-30110422 Figure 25. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 9 LP5904 SNVS637G – MARCH 2011 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN = 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA = 25°C. Inrush, VIN = (VOUT(NOM)) + 1V, VOUT = 3.3V, IOUT = 100 µA Inrush, VIN = (VOUT(NOM)) + 1V, VOUT = 3.3V, IOUT = 200 mA VOUT 1V/DIV 1V/DIV VOUT 1V/DIV VEN VEN 1V/DIV 2A/DIV IIN IIN 2A/DIV 20 Ps/DIV 20 Ps/DIV SVA-30110423 SVA-30110424 Figure 26. Figure 27. VEN Ramp Down vs VOUT at 1mA Load VOUT = 3.3V VEN Ramp Down vs VOUT at 200 mA Load VOUT = 3.3V 1V/DIV 1V/DIV 1V/DIV 1V/DIV VOUT VOUT VEN IIN 1A/DIV VEN 1A/DIV IIN 20 ms/DIV 20 ms/DIV SVA-30110425 SVA-30110426 Figure 28. Figure 29. Inrush, VIN Ramp at 1mA Load VOUT = 2.8V, VIN = 3.8V, TRISE = 100 ms Supply Ramping VEN = VIN = (VOUT + 1V) vs VOUT at IOUT = 200 mA, VOUT = 3.3V VOUT 1V/DIV VIN VEN = VIN = VOUT +1 1V/DIV VOUT 1V/DIV 1V/DIV 0 mA/ DIV IIN IIN 1A/DIV 40 ms/DIV 20 ms/DIV SVA-30110427 SVA-30110417 Figure 30. 10 Figure 31. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 LP5904 www.ti.com SNVS637G – MARCH 2011 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) Unless otherwise noted, VOUT = 2.8V, VIN = 3.8V, EN = 1.2V, CIN = 1.0 µF, COUT = 1.0 µF, TA = 25°C. VEN Ramping vs VOUT at IOUT = 100 µA, VIN = (VOUT + 1V), VOUT = 3.3V Supply Ramping VEN = VIN = (VOUT + 1V) vs VOUT at IOUT = 100 µA, VOUT = 3.3V VOUT 1V/DIV VOUT 1V/DIV VEN = VIN = VOUT +1 1V/DIV VEN 1V/DIV IIN 1A/DIV IIN 1A/DIV 40 ms/DIV 40 ms/DIV SVA-30110429 SVA-30110428 Figure 32. Figure 33. VEN Ramping vs VOUT at IOUT = 200 mA, VIN = (VOUT + 1V), VOUT = 3.3V High Inrush due to Fast Power-On (VIN = VEN) Such as in Hot-Plug VOUT 1V/DIV VEN 1V/DIV IIN 1A/DIV 40 ms/DIV SVA-30110430 SVA-30110405 Figure 34. Figure 35. No Inrush Current in Normal Power-On due to System Capacitance Showing VIN Ramping SVA-30110409 Figure 36. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 11 LP5904 SNVS637G – MARCH 2011 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION POWER DISSIPATION AND DEVICE OPERATION The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die and ambient air. As stated in the Operating Ratings (1), the allowable power dissipation for the device in a given package can be calculated using the equation: (T - TA PD = JMAX qJA (1) The actual power dissipation across the device can be represented by the following equation: PD = (VIN ) - VOUT ´ IOUT (2) This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. These two equations should be used to determine the optimum operating conditions for the device in the application. EXTERNAL CAPACITORS Like any low-dropout regulator, the LP5904 requires external capacitors for regulator stability. The LP5904 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. INPUT CAPACITOR An input capacitor is required for stability. The input capacitor should be at least equal to, or greater than, the output capacitor for good load transient performance. At least a 1.0 µF capacitor has to be connected between the LP5904 input pin and ground for stable operation over full load current range. Basically, it is ok to have more output capacitance than input, as long as the input is at least 1.0 µF. This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. NOTE Important: To ensure stable operation it is essential that good PCB practices are employed to minimize ground impedance and keep input inductance low. If these conditions cannot be met, or if long leads are to be used to connect the battery or other power source to the LP5904, then it is recommended to increase the input capacitor to at least 10 µF. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be specified by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain 1.0 µF ±30% over the entire operating temperature range. OUTPUT CAPACITOR The LP5904 is designed specifically to work with a very small ceramic output capacitor, typically 1.0 µF. A ceramic capacitor (dielectric types X5R or X7R) in the 0.5 µF to 10 µF range, and with ESR between 5mΩ to 500 mΩ, is suitable in the LP5904 application circuit. For this device the output capacitor should be connected between the VOUT pin and a good ground connection. (1) 12 In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAXOP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). See APPLICATION INFORMATION. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 LP5904 www.ti.com SNVS637G – MARCH 2011 – REVISED APRIL 2013 It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as attractive for reasons of size and cost (see CAPACITOR CHARACTERISTICS below). The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value that is within the range 5mΩ to 500 mΩ for stability. REMOTE CAPACITOR OPERATION The LP5904 requires at least a 1µF capacitor at output pin, but there is no strict requirements about the location of the capacitor in regards the LDO output pin. In practical designs the output capacitor may be located some 510 cm away from the LDO. This means that there is no need to have a special capacitor close to the output pin if there is already respective capacitor(s) in the system (like a capacitor at the input of supplied part). The Remote Capacitor feature helps user to minimize the number of capacitors in the system. As a good design practice, it is good to keep the wiring parasitic inductance at a minimum, which means to use as wide as possible traces from the LDO output to the capacitor(s), keeping the LDO trace layer as close as possible to ground layer and avoiding vias on the path. If there is a need to use vias, implement as many as possible vias between the connection layers. The recommendation is to keep parasitic wiring inductance less than 35 nH. For the applications with fast load transients, it is recommended to use an input capacitor equal to or larger to the sum of the capacitance at the output node for the best load transient performance. CAPACITOR CHARACTERISTICS The LP5904 is designed to work with ceramic capacitors on the input and output to take advantage of the benefits they offer. For capacitance values in the range of 0.5 µF to 10 µF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1.0 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LP5904. The temperature performance of ceramic capacitors varies by type and manufacturer. Most large value ceramic capacitors (≥ 2.2 µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C. A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.5 µF to 10 µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed. NO-LOAD STABILITY The LP5904 will remain stable and in regulation with no external load. ENABLE CONTROL The LP5904 may be switched ON or OFF by a logic input at the ENABLE pin. A high voltage at this pin will turn the device on. When the enable pin is low, the regulator output is off and the device typically consumes 3nA. However, if the application does not require the shutdown feature, the VEN pin can be tied to VIN to keep the regulator output permanently on. A 1MΩ pulldown resistor ties the VEN input to ground, this ensures that the device will remain off when the enable pin is left open circuit. To ensure proper operation, the signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. DSBGA MOUNTING The DSBGA package requires specific mounting techniques, which are detailed in Texas Instruments Application Note AN-1112 (SNVA009). Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 13 LP5904 SNVS637G – MARCH 2011 – REVISED APRIL 2013 www.ti.com For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the DSBGA device. DSBGA LIGHT SENSITIVITY Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with wavelengths in the red and infrared part of the spectrum have the most detrimental effect; thus, the fluorescent lighting used inside most buildings has very little effect on performance. 14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 LP5904 www.ti.com SNVS637G – MARCH 2011 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision F (April 2013) to Revision G • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LP5904 15 PACKAGE OPTION ADDENDUM www.ti.com 5-May-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) (4/5) LP5904SP-2.8/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SP-2.85/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SP-3.0/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SP-3.1/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SP-3.3/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SP-4.4/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SPX-1.2/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SPX-1.8/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SPX-2.8/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SPX-2.85/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SPX-3.0/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SPX-3.1/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SPX-3.3/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904SPX-4.4/NOPB NRND USON NLB 4 TBD Call TI Call TI LP5904TME-1.2/NOPB NRND DSBGA YFQ 4 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5904TME-1.5/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI LP5904TME-1.8/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI LP5904TME-2.5/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI LP5904TME-2.7/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI LP5904TME-2.8/NOPB ACTIVE DSBGA YFQ 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5904TME-2.85/NOPB ACTIVE DSBGA YFQ 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5904TME-3.1/NOPB ACTIVE DSBGA YFQ 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5904TME-3.3/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI LP5904TME-3.4/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI LP5904TME-4.4/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI LP5904TMX-1.2/NOPB NRND DSBGA YFQ 4 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 250 3000 Addendum-Page 1 Device Marking -40 to 125 -40 to 125 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 5-May-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP5904TMX-2.5/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI LP5904TMX-2.8/NOPB NRND DSBGA YFQ 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5904TMX-2.85/NOPB NRND DSBGA YFQ 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 LP5904TMX-3.0/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI LP5904TMX-3.1/NOPB NRND DSBGA YFQ 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5904TMX-3.3/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI LP5904TMX-3.4/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI LP5904TMX-4.4/NOPB NRND DSBGA YFQ 4 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 5-May-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LP5904TME-1.2/NOPB DSBGA YFQ 4 250 178.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 0.89 0.89 0.76 4.0 8.0 Q1 LP5904TME-2.8/NOPB DSBGA YFQ 4 250 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1 LP5904TME-2.85/NOPB DSBGA YFQ 4 250 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1 LP5904TME-3.1/NOPB DSBGA YFQ 4 250 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1 LP5904TMX-1.2/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1 LP5904TMX-2.8/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1 LP5904TMX-2.85/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1 LP5904TMX-3.1/NOPB DSBGA YFQ 4 3000 178.0 8.4 0.89 0.89 0.76 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP5904TME-1.2/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0 LP5904TME-2.8/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0 LP5904TME-2.85/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0 LP5904TME-3.1/NOPB DSBGA YFQ 4 250 210.0 185.0 35.0 LP5904TMX-1.2/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0 LP5904TMX-2.8/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0 LP5904TMX-2.85/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0 LP5904TMX-3.1/NOPB DSBGA YFQ 4 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NLB0004A TOP SIDE OF PACKAGE BOTTOM SIDE OF PACKAGE SPD04A (Rev A) www.ti.com MECHANICAL DATA YFQ0004xxx D 0.600±0.075 E TMD04XXX (Rev A) D: Max = 0.84 mm, Min = 0.78 mm E: Max = 0.84 mm, Min = 0.78 mm 4215073/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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