Aeroflex ACT-SF41632N-39F2C Act-sf41632 high speed 128kx32 sram / 512kx32 flash multichip module Datasheet

ACT-SF41632 High Speed
128Kx32 SRAM / 512Kx32 Flash
Multichip Module
CIRCUIT TECHNOLOGY
www.aeroflex.com
FEATURES
FLASH MEMORY FEATURES
Sector Architecture (Each Die)
● 8 Equal Sectors of 64K bytes each
● Any combination of sectors can be erased with
one command sequence.
■ +5V Programing, +5V Supply
■ Embedded Erase and Program Algorithms
■ Hardware and Software Write Protection
■ Page Program Operation and Internal Program
Control Time.
■ 10,000 Erase/Program Cycles
X LA
ISO
9001
E
I NC .
C
F
LE
S
A E RO
■
B
4 – 128K x 8 SRAMs & 4 – 512K x 8 Flash Die in
One MCM
■ Access Times of 25ns, 35ns (SRAM) and
60ns, 70ns, 90ns (Flash)
■ Organized as 128K x 32 of SRAM and 512K x 32
of Flash Memory with Common Data Bus
■ Low Power CMOS
■ Input and Output TTL Compatible Design
■ MIL-PRF-38534 Compliant MCMs Available
■ Decoupling Capacitors and Multiple Grounds for
Low Noise
■ Commercial, Industrial and Military Temperature
Ranges
■ Industry Standard Pinouts
■ TTL Compatible Inputs and Outputs
■ Packaging – Hermetic Ceramic
● 66–Lead, PGA-Type, 1.385"SQ x 0.245"max,
Aeroflex code# "P1,P5 with/without shoulders)"
● 68–Lead, Dual-Cavity CQFP(F2), 0.88"SQ x
.20"max (.18 max thickness available, contact
factory for details) (Drops into the 68 Lead
JEDEC .99"SQ CQFJ footprint)
■
RTIFIE D
Block Diagram – PGA Type Package(P1 & P5) & CQFP(F2)
FWE1 SWE1
FWE2 SWE2
FWE3 SWE3
FWE4 SWE4
OE
A0–A18
SCE
FCE
PIN DESCRIPTION
I/O0-31
Data I/O
A0–18
Address Inputs
FWE1-4
Flash Write Enables
SWE1-4 SRAM Write Enables
512K X 8 FLASH
128K X 8 SRAM
I/O0-7
512K X 8 FLASH
128K X 8 SRAM
I/O8-15
512K X 8 FLASH
128K X 8 SRAM
I/O16-23
512K X 8 FLASH
128K X 8 SRAM
FCE
Flash Chip Enable
SCE
SRAM Chip Enable
OE
Output Enable
NC
Not Connected
VCC
Power Supply
GND
Ground
I/O24-31
eroflex Circuit Technology - Advanced Multichip Modules © SCD3851 REV A 5/21/98
Absolute Maximum Ratings
Symbol
Rating
TC
TSTG
Range
Units
Case Operating Temperature
-55 to +125
°C
Storage Temperature
-65 to +150
°C
-0.5 to +7
V
300
°C
VG
Maximum Signal Voltage to Ground
TL
Maximum Lead Temperature (10 seconds)
Parameter
Flash Data Retention
10 Years
Flash Endurance (Write/Erase Cycles)
10,000
Normal Operating Conditions
Symbol
Minimum
Maximum
Units
Power Supply Voltage
+4.5
+5.5
V
VIH
Input High Voltage
+2.2
VCC + 0.3
V
VIL
Input Low Voltage
-0.5
+0.8
V
VCC
Parameter
Capacitance
(VIN = 0V, f = 1MHz, TA = 25°C)
Symbol Parameter
Maximum
Units
CAD
A0 – A18 Capacitance
80
pF
COE
OE Capacitance
80
pF
CWE1-4
F/S Write Enable Capacitance
30
pF
CCE
F/S Chip Enable Capacitance
50
pF
CI / O
I/O0 – I/O31 Capacitance
30
pF
This parameter is guaranteed by design but not tested
DC Characteristics
(VCC = 5.0V, VSS = 0V, Tc = -55°C to +125°C)
Parameter
Sym
Conditions
Min
Max Units
Input Leakage Current
ILI
VCC = Max, VIN = 0 to VCC
10
µA
Output Leakage Current
ILO
FCE = SCE = VIH, OE = VIH,
VOUT = 0 to VCC
10
µA
500
mA
SRAM Operating Supply Current x 32 I x32 SCE = VIL, OE = VIH, f = 5MHz, VCC =
CC
Max, FCE = VIH
Mode
Standby Current
ISB
FCE = SCE = VIH, OE = VIH, f = 5MHz,
VCC = Max
80
mA
SRAM Output Low Voltage
VOL
IOL = 8 mA, VCC = Min, FCE = VIH
0.4
V
SRAM Output High Voltage
VOH
IOH = -4.0 mA, , VCC = Min, FCE = VIH
Flash Vcc Active Current for Read (1)
ICC1
FCE = VIL, OE = VIH, SCE = VIH
260
mA
Flash Vcc Active Current for Program
or Erase (2)
ICC2
FCE = VIL, OE = VIH, SCE = VIH
300
mA
Flash Output Low Voltage
VOL
IOL = 12 mA, VCC = Min, SCE = VIH
0.45
V
Flash Output High Voltage
VOH1
IOH = -2.5 mA, , VCC = Min, SCE = VIH
Flash Low Vcc Lock Out Voltage
VLKO
2.4
V
0.85 x VCC
3.2
V
4.2
V
Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The
frequency component typically is less than 2mA/MHz, with OE at VIH 2) ICC active while Embedded Algorithim (program or
erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
Aeroflex Circuit Technology
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SCD3851 REV A 5/21/98
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SRAM AC Characteristics
(VCC = 5.0V, VSS= 0V, TC = -55°C to +125°C)
Read Cycle
Parameter
Symbol
–025
Min Max
–035
Min Max
25
35
Units
ns
Read Cycle Time
tRC
Address Access Time
tAA
25
35
ns
Chip Select Access Time
tACE
25
35
ns
Output Hold from Address Change
tOH
Output Enable to Output Valid
tOE
Chip Select to Output in Low Z *
tCLZ
3
3
ns
Output Enable to Output in Low Z *
tOLZ
0
0
ns
Chip Deselect to Output in High Z *
tCHZ
12
20
ns
Output Disable to Output in High Z *
tOHZ
12
20
ns
–025
Min Max
–035
Min Max
0
0
15
ns
20
ns
* Parameters guaranteed by design but not tested
Write Cycle
Parameter
Symbol
Units
Write Cycle Time
tWC
25
35
ns
Chip Select to End of Write
tCW
20
25
ns
Address Valid to End of Write
tAW
20
25
ns
Data Valid to End of Write
tDW
15
20
ns
Write Pulse Width
tWP
20
25
ns
Address Setup Time
tAS
0
0
ns
Output Active from End of Write *
tOW
0
0
ns
Write to Output in High Z *
tWHZ
Data Hold from Write Time
tDH
0
0
ns
Address Hold Time
tAH
0
0
ns
10
20
ns
* Parameters guaranteed by design but not tested
SRAM Truth Table
Mode
SCE
OE
SWE
Data I/O
Power
Standby
H
X
X
High Z
Standby
Read
L
L
H
Data Out
Active
Output Disable
L
H
H
High Z
Active
Write
L
X
L
Data In
Active
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Timing Diagrams — SRAM
Write Cycle Timing Diagrams
Read Cycle Timing Diagrams
Write Cycle (SWE Controlled, OE = VIH)
Read Cycle 1 (SCE = OE = VIL, SWE = VIH)
tWC
tRC
A0-18
A0-18
tAA
tAW
tCW
tOH
DI/O
Previous Data Valid
tAH
SCE
Data Valid
tAS
tWP
SWE
tWHZ
tOW
tDH
tDW
SEE NOTE
DI/O
Data Valid
Read Cycle 2 (SWE = VIH)
tRC
Write Cycle (SCE Controlled, OE = VIH )
A0-18
tWC
tAA
A0-18
tAH
tAW
SCE
tACE
tAS
tCHZ
tCLZ
SEE NOTE
SCE
tOHZ
SWE
tCW
SEE NOTE
OE
tWP
tOE
SEE NOTE
tOLZ
SEE NOTE
DI/O
UNDEFINED
tDW
Data Valid
High Z
DI/O
tDH
Data Valid
Note: Guaranteed by design, but not tested.
DON’T CARE
AC Test Circuit
Current Source
AC Test Conditions
IOL
VZ ~ 1.5 V (Bipolar Supply)
To Device Under Test
CL = 50 pF
Parameter
Typical
Units
Input Pulse Level
0 – 3.0
V
Input Rise and Fall
5
ns
Input and Output Timing Reference Level
1.5
V
IOH
Current Source
Notes:
1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance
ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance
load circuit. 6) ATE Tester includes jig capacitance.
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SCD3851 REV A 5/21/98
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Flash AC Characteristics – Read Only Operations
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Symbol
–60
–70
–90
Units
JEDEC Stand’d Min Max Min Max Min Max
Parameter
Read Cycle Time
tAVAV
tRC
Address Access Time
tAVQV
tACC
60
70
90
ns
60
70
90
ns
Chip Enable Access Time
tELQV
tCE
60
70
90
ns
Output Enable to Output Valid
tGLQV
tOE
30
35
35
ns
Chip Enable to Output High Z (1)
tEHQZ
tDF
20
20
20
ns
Output Enable High to Output High Z(1)
tGHQZ
tDF
20
20
20
ns
Output Hold from Address, CE or OE Change, Whichever is First
tAXQX
tOH
0
0
0
ns
Note 1. Guaranteed by design, but not tested
Flash AC Characteristics – Write / Erase / Program Operations, FWE Controlled
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter
Write Cycle Time
Symbol
JEDEC Stand’d
tAVAC
–60
–70
–90
Min Max Min Max Min Max
tWC
60
70
Units
90
ns
Chip Enable Setup Time
tELWL
tCE
0
0
0
ns
Write Enable Pulse Width
tWLWH
tWP
40
45
45
ns
Address Setup Time
tAVWL
tAS
0
0
0
ns
Data Setup Time
tDVWH
tDS
40
45
45
ns
Data Hold Time
tWHDX
tDH
0
0
0
ns
Address Hold Time
tWLAX
tAH
45
45
45
ns
Write Enable Pulse Width High
tWHWL
tWPH
20
20
20
ns
Duration of Byte Programming Operation
tWHWH1
Sector Erase Time
tWHWH2
Read Recovery Time before Write
tGHWL
14
0
tOEH 1
Chip Erase Time
TYP
14
30
0
50
Chip Programming Time
Chip Enable Hold Time
14
30
tVCE
Vcc Setup Time
TYP
TYP
µs
30
Sec
50
µs
0
50
µs
50
50
50
Sec
10
10
10
ns
120
tWHWH3
120
120
Sec
1. Toggle and Data Polling only.
Flash AC Characteristics – Write / Erase / Program Operations, FCE Controlled
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter
Symbol
JEDEC Stand’d
–60
–70
–90
Min Max Min Max Min Max
Units
Write Cycle Time
tAVAC
tWC
60
70
90
ns
Write Enable Setup Time
tWLEL
tWS
0
0
0
ns
Chip Enable Pulse Width
tELEH
tCP
40
45
45
ns
Address Setup Time
tAVEL
tAS
0
0
0
ns
Data Setup Time
tDVEH
tDS
40
45
45
ns
Data Hold Time
tEHDX
tDH
0
0
0
ns
Address Hold Time
tELAX
tAH
45
45
45
ns
Chip Enable Pulse Width High
tEHEL
tCPH
20
20
20
ns
Duration of Byte Programming
tWHWH1
Sector Erase Time
tWHWH2
Read Recovery Time
tGHEL
Chip Programming Time
Chip Erase Time
Aeroflex Circuit Technology
tWHWH3
5
14
TYP
14
30
0
TYP
14
30
0
TYP
µs
30
Sec
0
ns
50
50
50
Sec
120
120
120
Sec
SCD3851 REV A 5/21/98
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AC Waveforms for Flash Memory Read Operations
tRC
Addresses
Addresses Stable
tACC
FCE
tDF
OE
tOE
FWE
tCE
tOH
High Z
Outputs
Output Valid
High Z
Write/Erase/Program
Operation for Flash Memory, FWE Controlled
Data Polling
Addresses
5555H
PA
tWC
tAS
PA
tRC
tAH
FCE
tGHWL
OE
tWP
tWHWH1
tWPH
FWE
tCE
tDF
tOE
tDH
AOH
Data
PD
D7
DOUT
tDS
tOH
5.0V
tCE
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the deviced.
4. Dout is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
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AC Waveforms Chip/Sector
Erase Operations for Flash Memory
Data Polling
tAH
5555H
Addresses
2AAAH
5555H
5555H
2AAAH
SA
tAS
FCE
tGHWL
OE
tWP
FWE
tCE
tWPH
tDH
AAH
Data
55H
80H
AAH
55H
10H/30H
tDS
VCC
tVCE
Notes:
1. SA is the sector address for sector erase.
AC Waveforms for Data Polling
During Embedded Algorithm Operations for Flash Memory
tCH
FCE
tDF
tOE
OE
tOEH
tCE
FWE
tOH
*
DQ7
DQ7
DQ7=
Valid Data
High Z
tWHWH1 or 2
DQ0-DQ6
DQ0–DQ6
Valid Data
DQ0–DQ6=Invalid
tOE
* DQ7=Valid Data (The device has completed the Embedded operation).
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Write/Erase/Program Operation for Flash Memory, FCE Controlled
Data Polling
Addresses
5555H
PA
tWC
tAS
PA
tAH
FCE
tGHWL
OE
tCP
FWE
tWHWH1
tCPH
tWS
tDH
AOH
Data
PD
D7
DOUT
tDS
5.0V
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Aeroflex Circuit Technology
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SCD3851 REV A 5/21/98
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Pin Numbers & Functions
66 Pins — PGA-Type
Pin #
Function
Pin #
Function
Pin #
Function
Pin #
Function
1
I/O8
18
A15
35
I/O25
52
FWE3
2
I/O9
19
Vcc
36
I/O26
53
SWE3
3
I/O10
20
FCE
37
A7
54
GND
4
A14
21
SCE
38
A12
55
I/O19
5
A16
22
I/O3
39
SWE1
56
I/O31
6
A11
23
I/O15
40
A13
57
I/O30
7
A0
24
I/O14
41
A8
58
I/O29
8
A18
25
I/O13
42
I/O16
59
I/O28
9
I/O0
26
I/O12
43
I/O17
60
A1
10
I/O1
27
OE
44
I/O18
61
A2
11
I/O2
28
A17
45
VCC
62
A3
12
FWE2
29
FWE1
46
SWE4
63
I/O23
13
SWE2
30
I/O7
47
FWE4
64
I/O22
14
GND
31
I/O6
48
I/O27
65
I/O21
15
I/O11
32
I/O5
49
A4
66
I/O20
16
A10
33
I/O4
50
A5
17
A9
34
I/O24
51
A6
"P1" — 1.385" SQ PGA Type Package Standard (with shoulders on Pins 1, 11, 56 & 66)
"P5" — 1.385" SQ PGA Type Special Order Package (without shoulders)
Bottom View (P1 & P5)
Side View
(P5)
Side View
(P1)
.245
MAX
.025
.035
1.400 SQ
MAX
1.000
TYP
.600
TYP
.220
MAX
Pin 1
Pin 56
.100
TYP
1.000
TYP
.100 TYP
.020
.016
.020
.016
Pin 66
.145
MIN
Pin 11
.165
MIN
.100 TYP
All dimensions in inches
Aeroflex Circuit Technology
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SCD3851 REV A 5/21/98
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Pin Numbers & Functions
68 Pins — Dual-Cavity CQFP
Pin #
Function
Pin #
Function
Pin #
Function
Pin #
Function
1
GND
18
GND
35
OE
52
GND
2
SWE3
19
I/O8
36
SWE2
53
FI/O23
3
A5
20
I/O9
37
A17
54
FI/O22
4
A4
21
I/O10
38
FWE2
55
FI/O21
5
A3
22
I/O11
39
FWE3
56
FI/O20
6
A2
23
I/O12
40
FWE4
57
FI/O19
7
A1
24
I/O13
41
A18
58
FI/O18
8
A0
25
I/O14
42
SCE
59
FI/O17
9
NC
26
I/O15
43
SWE1
60
FI/O16
10
I/O0
27
Vcc
44
FI/O31
61
VCC
11
I/O1
28
A11
45
FI/O30
62
A10
12
I/O2
29
A12
46
FI/O29
63
A9
13
I/O3
30
A13
47
FI/O28
64
A8
14
I/O4
31
A14
48
FI/O27
65
A7
15
I/O5
32
A15
49
FI/O26
66
A6
16
I/O6
33
A16
50
FI/O25
67
FWE1
17
I/O7
34
FCE
51
FI/O24
68
SWE4
Package Outline — Dual-Cavity CQFP "F2"
Top View
Pin 9
.990 SQ
±.010
.890 SQ
MAX
Pin 10
Pin 61
*.200 MAX
.010 REF
Pin 60
.015
±.002
.010 ±.002
.010 R
REF
+3°/-3°
.050
TYP
.010 ±.005
.040
±.005
Detail “A”
Pin 26
Pin 27
Pin 44
.800 REF
Pin 43
See Detail “A”
*.180 MAX available, call factory for details
All dimensions in inches
Aeroflex Circuit Technology
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SCD3851 REV A 5/21/98
Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Ordering Information
Model Number
DESC Part Number
Speed
Package
ACT-SF41632N–26P1X
TBD
25(S) / 60(F) ns
1.385"sq PGA-Type
ACT-SF41632N–37P1X
TBD
35(S) / 70(F) ns
1.385"sq PGA-Type
ACT-SF41632N–39P1X
TBD
35(S) / 90(F) ns
1.385"sq PGA-Type
ACT-SF41632N–26F2X
TBD
25(S) / 60(F) ns
.88"sq CQFP
ACT-SF41632N–37F2X
TBD
35(S) / 70(F) ns
.88"sq CQFP
ACT-SF41632N–39F2X
TBD
35(S) / 90(F) ns
.88"sq CQFP
Note: (S) = Speed for SRAM, (F) = Speed for FLASH
Part Number Breakdown
ACT– SF 416 32 N– 26 P1 M
Aeroflex Circuit
Technology
Memory Type
SF = SRAM Flash Combo Module
Screening
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C Screened *
Q = MIL-PRF-38534 Compliant/SMD
Memory Depth, Locations
4 = 4M SRAM, 16 = 16M Flash
Memory Width, Bits
Package Types & Sizes
Surface Mount Packages
F2 = 0.88"SQ 68 Leads Dual-Cavity CQFP
Pinout Options
N = None
Thru-Hole Packages
P1 = 1.385"SQ PGA 66 Pins W/Shoulder
P5 = 1.385"SQ PGA 66 Pins WO/Shoulder
Memory Speed (Code)
26 = 25ns SRAM & 60ns FLASH
37 = 35ns SRAM & 70ns FLASH
39 = 35ns SRAM & 90ns FLASH
* Screened to the individual test methods of MIL-STD-883
Specifications subject to change without notice.
Telephone: (516) 694-6700
FAX:
(516) 694-6715
Toll Free Inquiries: 1-(800) 843-1553
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830
Aeroflex Circuit Technology
11
SCD3851 REV A 5/21/98
Plainview NY (516) 694-6700
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