LM6172QML www.ti.com SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 LM6172QML Dual High Speed, Low Power, Low Distortion, Voltage Feedback Amplifiers Check for Samples: LM6172QML FEATURES DESCRIPTION • Available with Radiation Specification – High Dose Rate 300 krad(Si) – ELDRS Free 100 krad(Si) • Easy to Use Voltage Feedback Topology • High Slew Rate 3000V/μs • Wide Unity-Gain Bandwidth 100MHz • Low Supply Current 2.3mA / Amplifier • High Output Current 50mA / Amplifier • Specified for ±15V and ±5V Operation The LM6172 is a dual high speed voltage feedback amplifier. It is unity-gain stable and provides excellent DC and AC performance. With 100MHz unity-gain bandwidth, 3000V/μs slew rate and 50mA of output current per channel, the LM6172 offers high performance in dual amplifiers; yet it only consumes 2.3mA of supply current each channel. APPLICATIONS The LM6172 is built with TI's advanced VIP™ III (Vertically Integrated PNP) complementary bipolar process. 1 234 • • • • • • • Scanner I- to -V Converters ADSL/HDSL Drivers Multimedia Broadcast Systems Video Amplifiers NTSC, PAL® and SECAM Systems ADC/DAC Buffers Pulse Amplifiers and Peak Detectors The LM6172 operates on ±15V power supply for systems requiring large voltage swings, such as ADSL, scanners and ultrasound equipment. It is also specified at ±5V power supply for low voltage applications such as portable video systems. Connection Diagram Figure 1. 8-Pin CDIP Top View N/C 1 16 N/C OUT A 2 15 N/C IN- A 3 14 V+ IN+ A 4 13 N/C N/C 5 12 OUT B V- 6 11 IN- B N/C 7 10 IN+ B N/C 8 9 N/C Figure 2. 16LD CLGA Top View 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VIP is a trademark of Texas Instruments. PAL is a registered trademark of and used under lisence from Advanced Micro Devices, Inc.. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2011, Texas Instruments Incorporated LM6172QML SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 www.ti.com LM6172 Driving Capacitive Load LM6172 Simplified Schematic (Each Amplifier) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML LM6172QML www.ti.com SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage (V+ − V−) Differential Input Voltage 36V (2) ±10V Maximum Junction Temperature Power Dissipation 150°C (3) (4) , Output Short Circuit to Ground 1.03W (5) Continuous Storage Temperature Range −65°C ≤ TA ≤ +150°C Common Mode Voltage Range V+ +0.3V to V− −0.3V Input Current ±10mA Thermal Resistance (6) θJA θJC Package Weight ESD Tolerance (1) (2) (3) (4) (5) (6) (7) 8LD CDIP (Still Air) 100°C/W 8LD CDIP (500LF/Min Air Flow) 46°C/W 16LD CLGA (Still Air) “WG” 124°C/W 16LD CLGA (500LF/Min Air Flow) “WG” 74°C/W 16LD CLGA (Still Air) “GW” 135°C/W 16LD CLGA (500LF/Min Air Flow) “GW” 85°C/W 8LD CDIP (4) 2°C/W 16LD CLGA “WG” (4) 6°C/W 16LD CLGA “GW” 7°C/W 8LD CDIP 980mg 16LD CLGA “WG” 365mg 16LD CLGA “GW” 410mg (7) 4KV Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Differential Input Voltage is measured at VS = ±15V. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. The package material for these devices allows much improved heat transfer over our standard ceramic packages. In order to take full advantage of this improved heat transfer, heat sinking must be provided between the package base (directly beneath the die), and either metal traces on, or thermal vias through, the printed circuit board. Without this additional heat sinking, device power dissipation must be calculated using θJA, rather than θJC, thermal resistance. It must not be assumed that the device leads will provide substantial heat transfer out the package, since the thermal resistance of the leadframe material is very poor, relative to the material of the package base. The stated θJC thermal resistance is for the package material only, and does not account for the additional thermal resistance between the package base and the printed circuit board. The user must determine the value of the additional thermal resistance and must combine this with the stated value for the package, to calculate the total allowed power dissipation for the device. Continuous short circuit operation can result in exceeding the maximum allowed junction temperature of 150°C All numbers apply for packages soldered directly into a PC board. Human body model, 1.5 kΩ in series with 100 pF. RECOMMENDED OPERATING CONDITIONS (1) 5.5V ≤ VS ≤ 36V Supply Voltage −55°C ≤ TA ≤ +125°C Operating Temperature Range (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML 3 LM6172QML SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 www.ti.com QUALITY CONFORMANCE INSPECTION Mil-Std-883, Method 5005 - Group A Subgroup Description 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Settling time at +25 13 Settling time at +125 14 Settling time at -55 LM6172 (±5V) ELECTRICAL CHARACTERISTICS DC PARAMETERS The following conditions apply, unless otherwise specified. Symbol Parameter VIO Input Offset Voltage IIB Input Bias Current IIO Input Offset Current CMRR Common Mode Rejection Ratio PSRR Power Supply Rejection Ratio (1) TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V & RL > 1MΩ Conditions VS = ±15V to ±5V Large Signal Voltage Gain RL = 100Ω RL = 1KΩ VO Output Swing RL = 100Ω (1) (2) 4 Notes VCM = ±2.5V RL = 1KΩ AV Temp (°C) Min Subgroups Max Units 1.0 mV 1 3.0 mV 2, 3 2.5 µA 1 3.5 µA 2, 3 1.5 µA 1 2.2 µA 2, 3 70 dB 1 65 dB 2, 3 75 dB 1 70 dB 2, 3 See (2) 70 dB 1 See (2) 65 dB 2, 3 See (2) 65 dB 1 See (2) dB 2, 3 60 3.1 -3.1 V 1 3.0 -3.0 V 2, 3 2.5 -2.4 V 1 2.4 -2.3 V 2, 3 Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are specified only for the conditions as specified in Mil-Std-883, Method 1019.5, Condition A. Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT = ±5V. For VS = ±5V, VOUT = ±1V. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML LM6172QML www.ti.com SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 LM6172 (±5V) ELECTRICAL CHARACTERISTICS (1) DC PARAMETERS (continued) The following conditions apply, unless otherwise specified. Symbol Parameter TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V & RL > 1MΩ Conditions Sourcing RL = 100Ω IL Output Current (Open Loop) Sinking RL = 100Ω IS Supply Current (3) Notes Min Max Units Subgroups See (3) 25 mA 1 See (3) 24 mA 2, 3 See (3) -24 mA 1 See (3) -23 mA 2, 3 6.0 mA 1 7.0 mA 2, 3 Both Amplifiers The open loop output current is specified by measurement of the open loop output voltage swing using 100Ω output load. DC DRIFT PARAMETERS (1) The following conditions apply, unless otherwise specified. TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V & RL > 1MΩ Delta calculations performed on QMLV devices at group B , subgroup 5. Symbol Parameter Conditions Notes Min Max Units Subgroups VIO Input Offset Voltage -0.25 0.25 mV 1 IIB Input Bias Current -0.50 0.50 µA 1 IIO Input Ofset Current -0.25 0.25 µA 1 (1) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are specified only for the conditions as specified in Mil-Std-883, Method 1019.5, Condition A. LM6172 (±15V) ELECTRICAL CHARACTERISTICS DC PARAMETERS (1) The following conditions apply, unless otherwise specified. Symbol VIO Parameter TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, & RL = 1MΩ Conditions Input Bias Current IIO Input Offset Current CMRR Common Mode Rejection Ratio PSRR Power Supply Rejection Ratio VCM = ±10V VS = ±15V to ±5V RL = 1KΩ Large Signal Voltage Gain RL = 100Ω (1) (2) Max Units Subgroups 1.5 mV 1 3.5 mV 2, 3 3.0 µA 1 4.0 µA 2, 3 2.0 µA 1 3.0 µA 2, 3 70 dB 1 65 dB 2, 3 75 dB 1 70 dB 2, 3 Min Input Offset Voltage IIB AV Notes See (2) 75 dB 1 See (2) 70 dB 2, 3 See (2) 65 dB 1 See (2) 60 dB 2, 3 Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are specified only for the conditions as specified in Mil-Std-883, Method 1019.5, Condition A. Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT = ±5V. For VS = ±5V, VOUT = ±1V. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML 5 LM6172QML SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 www.ti.com LM6172 (±15V) ELECTRICAL CHARACTERISTICS DC PARAMETERS (1) (continued) The following conditions apply, unless otherwise specified. Symbol Parameter TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, & RL = 1MΩ Conditions Notes RL = 1KΩ VO Output Swing RL = 100Ω Sourcing RL = 100Ω IL Output Current (Open Loop) Sinking RL = 100Ω IS Supply Current (3) Subgroups Min Max Units 12.5 -12.5 V 1 12 -12 V 2, 3 6.0 -6.0 V 1 5.0 -5.0 V 2, 3 See (3) 60 mA 1 See (3) 50 mA 2, 3 See (3) -60 mA 1 See (3) -50 mA 2, 3 8.0 mA 1 9.0 mA 2, 3 Both Amplifiers The open loop output current is specified by measurement of the open loop output voltage swing using 100Ω output load. AC PARAMETERS (1) The following conditions apply, unless otherwise specified. Symbol SR Conditions AV = 2, VI = ±2.5V 3nS Rise & Fall time Slew Rate GBW (1) Parameter TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V Unity-Gain Bandwidth Notes See Units Subgroups 1700 V/µS 4 80 MHz 4 Min Max (2) (3) See , (4) Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are specified only for the conditions as specified in Mil-Std-883, Method 1019.5, Condition A. See AN0009 for SR test circuit. Slew Rate measured between ±4V. See AN0009 for GBW test circuit. (2) (3) (4) DC DRIFT PARAMETERS (1) The following conditions apply, unless otherwise specified. TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V Delta calculations performed on QMLV devices at group B , subgroup 5. Symbol Parameter Conditions Notes Min Max Units Subgroups VIO Input Offset Voltage -0.25 0.25 mV 1 IIB Input Bias Current -0.50 0.50 µA 1 IIO Input Offset Current -0.25 0.25 µA 1 (1) 6 Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics. These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are specified only for the conditions as specified in Mil-Std-883, Method 1019.5, Condition A. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML LM6172QML www.ti.com SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, TA = 25°C Supply Voltage vs. Supply Current Supply Current vs. Temperature Figure 3. Figure 4. Input Offset Voltage vs. Temperature Input Bias Current vs. Temperature Figure 5. Figure 6. Short Circuit Current vs. Temperature (Sourcing) Short Circuit Current vs. Temperature (Sinking) Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML 7 LM6172QML SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted, TA = 25°C 8 Output Voltage vs. Output Current (VS = ±15V) Output Voltage vs. Output Current (VS = ±5V) Figure 9. Figure 10. CMRR vs. Frequency PSRR vs. Frequency Figure 11. Figure 12. PSRR vs. Frequency Open-Loop Frequency Response Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML LM6172QML www.ti.com SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted, TA = 25°C Open-Loop Frequency Response Gain-Bandwidth Product vs. Supply Voltage at Different Temperature Figure 15. Figure 16. Large Signal Voltage Gain vs. Load Large Signal Voltage Gain vs. Load Figure 17. Figure 18. Input Voltage Noise vs. Frequency Input Voltage Noise vs. Frequency Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML 9 LM6172QML SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted, TA = 25°C 10 Input Current Noise vs. Frequency Input Current Noise vs. Frequency Figure 21. Figure 22. Slew Rate vs. Supply Voltage Slew Rate vs. Input Voltage Figure 23. Figure 24. Large Signal Pulse Response AV = +1, VS = ±15V Small Signal Pulse Response AV = +1, VS = ±15V Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML LM6172QML www.ti.com SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted, TA = 25°C Large Signal Pulse Response AV = +1, VS = ±5V Small Signal Pulse Response AV = +1, VS = ±5V Figure 27. Figure 28. Large Signal Pulse Response AV = +2, VS = ±15V Small Signal Pulse Response AV = +2, VS = ±15V Figure 29. Figure 30. Large Signal Pulse Response AV = +2, VS = ±5V Small Signal Pulse Response AV = +2, VS = ±5V Figure 31. Figure 32. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML 11 LM6172QML SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted, TA = 25°C 12 Large Signal Pulse Response AV = −1, VS = ±15V Small Signal Pulse Response AV = −1, VS = ±15V Figure 33. Figure 34. Large Signal Pulse Response AV = −1, VS = ±5V Small Signal Pulse Response AV = −1, VS = ±5V Figure 35. Figure 36. Closed Loop Frequency Response vs. Supply Voltage (AV = +1) Closed Loop Frequency Response vs. Supply Voltage (AV = +2) Figure 37. Figure 38. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML LM6172QML www.ti.com SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise noted, TA = 25°C Harmonic Distortion vs. Frequency (VS = ±15V) Harmonic Distortion vs. Frequency (VS = ±5V) Figure 39. Figure 40. Crosstalk Rejection vs. Frequency Maximum Power Dissipation vs. Ambient Temperature Figure 41. Figure 42. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML 13 LM6172QML SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 www.ti.com APPLICATION NOTES LM6172 PERFORMANCE DISCUSSION The LM6172 is a dual high-speed, low power, voltage feedback amplifier. It is unity-gain stable and offers outstanding performance with only 2.3mA of supply current per channel. The combination of 100MHz unity-gain bandwidth, 3000V/μs slew rate, 50mA per channel output current and other attractive features makes it easy to implement the LM6172 in various applications. Quiescent power of the LM6172 is 138mW operating at ±15V supply and 46mW at ±5V supply. LM6172 CIRCUIT OPERATION The class AB input stage in LM6172 is fully symmetrical and has a similar slewing characteristic to the current feedback amplifiers. In the LM6172 Simplified Schematic (Page 2), Q1 through Q4 form the equivalent of the current feedback input buffer, RE the equivalent of the feedback resistor, and stage A buffers the inverting input. The triple-buffered output stage isolates the gain stage from the load to provide low output impedance. LM6172 SLEW RATE CHARACTERISTIC The slew rate of LM6172 is determined by the current available to charge and discharge an internal high impedance node capacitor. This current is the differential input voltage divided by the total degeneration resistor RE. Therefore, the slew rate is proportional to the input voltage level, and the higher slew rates are achievable in the lower gain configurations. When a very fast large signal pulse is applied to the input of an amplifier, some overshoot or undershoot occurs. By placing an external series resistor such as 1kΩ to the input of LM6172, the slew rate is reduced to help lower the overshoot, which reduces settling time. REDUCING SETTLING TIME The LM6172 has a very fast slew rate that causes overshoot and undershoot. To reduce settling time on LM6172, a 1kΩ resistor can be placed in series with the input signal to decrease slew rate. A feedback capacitor can also be used to reduce overshoot and undershoot. This feedback capacitor serves as a zero to increase the stability of the amplifier circuit. A 2pF feedback capacitor is recommended for initial evaluation. When the LM6172 is configured as a buffer, a feedback resistor of 1kΩ must be added in parallel to the feedback capacitor. Another possible source of overshoot and undershoot comes from capacitive load at the output. Please see the section “ Driving Capacitive Loads” for more detail. DRIVING CAPACITIVE LOADS Amplifiers driving capacitive loads can oscillate or have ringing at the output. To eliminate oscillation or reduce ringing, an isolation resistor can be placed as shown in Figure 43. The combination of the isolation resistor and the load capacitor forms a pole to increase stability by adding more phase margin to the overall system. The desired performance depends upon the value of the isolation resistor; the bigger the isolation resistor, the more damped (slow) the pulse response becomes. For LM6172, a 50Ω isolation resistor is recommended for initial evaluation. Figure 43. Isolation Resistor Used to Drive Capacitive Load 14 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML LM6172QML www.ti.com SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 Figure 44. The LM6172 Driving a 510pF Load with a 30Ω Isolation Resistor Figure 45. The LM6172 Driving a 220 pF Load with a 50Ω Isolation Resistor LAYOUT CONSIDERATION Printed Circuit Boards And High Speed Op Amps There are many things to consider when designing PC boards for high speed op amps. Without proper caution, it is very easy to have excessive ringing, oscillation and other degraded AC performance in high speed circuits. As a rule, the signal traces should be short and wide to provide low inductance and low impedance paths. Any unused board space needs to be grounded to reduce stray signal pickup. Critical components should also be grounded at a common point to eliminate voltage drop. Sockets add capacitance to the board and can affect frequency performance. It is better to solder the amplifier directly into the PC board without using any socket. Using Probes Active (FET) probes are ideal for taking high frequency measurements because they have wide bandwidth, high input impedance and low input capacitance. However, the probe ground leads provide a long ground loop that will produce errors in measurement. Instead, the probes can be grounded directly by removing the ground leads and probe jackets and using scope probe jacks. Components Selection And Feedback Resistor It is important in high speed applications to keep all component leads short because wires are inductive at high frequency. For discrete components, choose carbon composition-type resistors and mica-type capacitors. Surface mount components are preferred over discrete components for minimum inductive effect. Large values of feedback resistors can couple with parasitic capacitance and cause undesirable effects such as ringing or oscillation in high speed amplifiers. For LM6172, a feedback resistor less than 1kΩ gives optimal performance. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML 15 LM6172QML SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 www.ti.com COMPENSATION FOR INPUT CAPACITANCE The combination of an amplifier's input capacitance with the gain setting resistors adds a pole that can cause peaking or oscillation. To solve this problem, a feedback capacitor with a value CF > (RG × CIN)/RF can be used to cancel that pole. For LM6172, a feedback capacitor of 2pF is recommended. Figure 46 illustrates the compensation circuit. Figure 46. Compensating for Input Capacitance POWER SUPPLY BYPASSING Bypassing the power supply is necessary to maintain low power supply impedance across frequency. Both positive and negative power supplies should be bypassed individually by placing 0.01μF ceramic capacitors directly to power supply pins and 2.2μF tantalum capacitors close to the power supply pins. Figure 47. Power Supply Bypassing TERMINATION In high frequency applications, reflections occur if signals are not properly terminated. Figure 48 shows a properly terminated signal while Figure 49 shows an improperly terminated signal. 16 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML LM6172QML www.ti.com SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 Figure 48. Properly Terminated Signal Figure 49. Improperly Terminated Signal To minimize reflection, coaxial cable with matching characteristic impedance to the signal source should be used. The other end of the cable should be terminated with the same value terminator or resistor. For the commonly used cables, RG59 has 75Ω characteristic impedance, and RG58 has 50Ω characteristic impedance. POWER DISSIPATION The maximum power allowed to dissipate in a device is defined as: PD = (TJ(max) − TA)/θJA Where • • • • PD is the power dissipation in a device TJ(max) is the maximum junction temperature TA is the ambient temperature θJA is the thermal resistance of a particular package For example, for the LM6172 in a SOIC-16 package, the maximum power dissipation at 25°C ambient temperature is 1000mW. Thermal resistance, θJA, depends on parameters such as die size, package size and package material. The smaller the die size and package, the higher θJA becomes. The 8-pin CDIP package has a lower thermal resistance (95°C/W) than that of 8-pin SOIC (160°C/W). Therefore, for higher dissipation capability, use an 8-pin CDIP package. The total power dissipated in a device can be calculated as: PD = PQ + PL • PQ is the quiescent power dissipated in a device with no load connected at the output. • PL is the power dissipated in the device with a load connected at the output; it is not the power dissipated by Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML 17 LM6172QML SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 www.ti.com the load. Furthermore, • • PQ: = supply current x total supply voltage with no load PL: = output current x (voltage difference between supply voltage and output voltage of the same supply) For example, the total power dissipated by the LM6172 with VS = ±15V and both channels swinging output voltage of 10V into 1kΩ is PD: = PQ + PL : = 2[(2.3mA)(30V)] + 2[(10mA)(15V − 10V)] : = 138mW + 100mW : = 238mW Application Circuits Figure 50. I- to -V Converters Figure 51. Differential Line Driver 18 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML LM6172QML www.ti.com SNOSAR4A – DECEMBER 2010 – REVISED OCTOBER 2011 REVISION HISTORY Released Revision 12/08/2010 A New Release, Corporate format Section 1 MDS data sheet converted into one Corp. data sheet format. MNLM6172AM-X-RH Rev 0A0 will be archived. Changes 10/05/2011 B Features, Ordering Information, Abs Max Ratings, Footnotes Update Radiation, Add new ELDRS FREE die id, 'GW' NSID'S w/coresponding SMD numbers. Add 'GW' Theta JA & Theta JC along with weight.Add Note 15, Modify Note 14. LM6172QML Rev A will be archived. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Links: LM6172QML 19 PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-9560401QPA ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM6172AMJQML 5962-95604 01QPA Q ACO 01QPA Q >T 5962-9560402QXA ACTIVE CFP NAC 16 42 TBD Call TI Call TI -55 to 125 LM6172AMGW -QML Q 5962-95604 02QXA ACO 02QXA >T 5962F9560401QPA OBSOLETE CDIP NAB 8 TBD Call TI Call TI -55 to 125 LM6172AMJFQL 5962F95604 01QPA Q ACO 01QPA Q >T 5962F9560401V9A ACTIVE DIESALE Y 0 39 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 5962F9560401VPA ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM6172AMJFQV 5962F95604 01VPA Q ACO 01VPA Q >T 5962F9560402VXA ACTIVE CFP NAC 16 42 TBD Call TI Call TI -55 to 125 LM6172AMGWF QMLV Q 5962F95604 02VXA ACO 02VXA >T 5962R9560403V9A ACTIVE DIESALE Y 0 39 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 5962R9560403VXA ACTIVE CFP NAC 16 42 TBD Call TI Call TI -55 to 125 LM6172 MDR ACTIVE DIESALE Y 0 39 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 LM6172-MDE ACTIVE DIESALE Y 0 39 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -55 to 125 LM6172AMGW-QML ACTIVE CFP NAC 16 42 TBD Call TI Call TI -55 to 125 Addendum-Page 1 LM6172AMGW RLQMLV Q 5962R95604 03VXA ACO 03VXA >T LM6172AMGW -QML Q Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 27-Jul-2016 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-95604 02QXA ACO 02QXA >T LM6172AMGWFQMLV ACTIVE CFP NAC 16 42 TBD Call TI Call TI -55 to 125 LM6172AMGWF QMLV Q 5962F95604 02VXA ACO 02VXA >T LM6172AMGWRLQV ACTIVE CFP NAC 16 42 TBD Call TI Call TI -55 to 125 LM6172AMGW RLQMLV Q 5962R95604 03VXA ACO 03VXA >T LM6172AMJ-QML ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM6172AMJQML 5962-95604 01QPA Q ACO 01QPA Q >T LM6172AMJFQML OBSOLETE CDIP NAB 8 TBD Call TI Call TI -55 to 125 LM6172AMJFQL 5962F95604 01QPA Q ACO 01QPA Q >T LM6172AMJFQMLV ACTIVE CDIP NAB 8 TBD Call TI Call TI -55 to 125 LM6172AMJFQV 5962F95604 01VPA Q ACO 01VPA Q >T 40 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2016 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF LM6172QML, LM6172QML-SP : • Military: LM6172QML • Space: LM6172QML-SP NOTE: Qualified Version Definitions: • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3 MECHANICAL DATA NAB0008A J08A (Rev M) www.ti.com MECHANICAL DATA NAC0016A WG16A (RevG) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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