EtronTech
EM639325
4M x 32 bit Synchronous DRAM (SDRAM)
Advance (Rev. 2.1, Aug. /2015)
Features
Overview
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The EM639325 SDRAM is a high-speed CMOS
synchronous DRAM containing 128 Mbits. It is
internally configured as a quad 1M x 32 DRAM with
a synchronous interface (all signals are registered
on the positive edge of the clock signal, CLK). Each
of the 1M x 32 bit banks is organized as 4096 rows
by 256 columns by 32 bits. Read and write accesses
to the SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed
number of locations in a programmed sequence.
Accesses begin with the registration of a BankActivate
command which is then followed by a Read or Write
command.
The EM639325 provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with
a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use. By having a programmable
mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring
high memory bandwidth.
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Fast access time from clock: 5/5.4/5.4 ns
Fast clock rate: 200/166/143 MHz
Fully synchronous operation
Internal pipelined architecture
Four internal banks (1M x 32-bit x 4bank)
Programmable Mode
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential & Interleaved
- Burst-Read-Single-Write
Burst stop function
Individual byte controlled by DQM0-3
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
Single 3.3V ±0.3V power supply
Industrial Temperature: TA = -40~85°C
Interface: LVTTL
86-pin 400 mil plastic TSOP II package
- Pb free and Halogen free
90-ball 8 x 13 x 1.2mm FBGA package
- Pb and Halogen Free
Table 1. Key Specifications
EM639325
-5I/6I/7I
tCK3 Clock Cycle time(min.)
tAC3 Access time from CLK (max.)
5/5.4/5.4
ns
tRAS Row Active time(min.)
40/42/42
ns
55/60/63
ns
tRC
Row Cycle time(min.)
5/6/7
ns
Table 2. Ordering Information
Part Number
Frequency
Package
EM639325TS-5IG
200MHz
TSOP II
EM639325TS-6IG
166MHz
EM639325TS-7IG
143MHz
EM639325BK-5IH
200MHz
EM639325BK-6IH
166MHz
EM639325BK-7IH
143MHz
TS: indicates TSOP II Package
BK: indicates 8 x 13 x 1.2mm FBGA Package
I: indicates Industrial Grade
G: indicates Pb and Halogen Free for TSOP II Package
H: indicates Pb and Halogen Free for FBGA Package
TSOP II
TSOP II
FBGA
FBGA
FBGA
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.
EtronTech
EM639325
Figure 1. Pin Assignment (Top View)
VDD
1
86
VSS
DQ0
2
85
DQ15
VDDQ
3
84
VSSQ
DQ1
4
83
DQ14
DQ2
5
82
DQ13
VSSQ
6
81
VDDQ
DQ3
7
80
DQ12
DQ4
8
79
DQ11
VDDQ
9
78
VSSQ
DQ5
10
77
DQ10
DQ6
11
76
DQ9
VSSQ
12
75
VDDQ
DQ7
13
74
DQ8
NC
14
73
NC
VDD
15
72
VSS
DQM0
16
71
DQM1
WE#
17
70
NC
CAS#
18
69
NC
RAS#
19
68
CLK
CS#
20
67
CKE
A11
21
66
A9
BA0
22
65
A8
BA1
23
64
A7
A10/AP
24
63
A6
A0
25
62
A5
A1
26
61
A4
A2
27
60
A3
DQM2
28
59
DQM3
VDD
29
58
VSS
NC
30
57
NC
DQ16
31
56
DQ31
VSSQ
32
55
VDDQ
DQ17
33
54
DQ30
DQ18
34
53
DQ29
VDDQ
35
52
VSSQ
DQ19
36
51
DQ28
DQ20
37
50
DQ27
VSSQ
38
49
VDDQ
DQ21
39
48
DQ26
DQ22
40
47
DQ25
VDDQ
41
46
VSSQ
DQ23
42
45
DQ24
VDD
43
44
VSS
Rev. 2.1
2
Aug. /2015
EtronTech
EM639325
Figure 2. Ball Assignment (Top View)
1
2
3
7
8
9
A
DQ26
DQ24
VSS
VDD
DQ23
DQ21
B
DQ28
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
C
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
D
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
E
VDDQ
DQ31
NC
NC
DQ16
VSSQ
F
VSS
DQM3
A3
A2
DQM2
VDD
G
A4
A5
A6
A10
A0
A1
H
A7
A8
NC
NC
BA1
A11
J
CLK
CKE
A9
BA0
CS#
RAS#
K
DQM1
NC
NC
CAS#
WE#
DQM0
L
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
M
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
N
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
P
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
R
DQ13
DQ15
VSS
VDD
DQ0
DQ2
Rev. 2.1
3
Aug. /2015
EtronTech
EM639325
CLOCK
BUFFER
Column Decoder
CKE
A10/AP
DQ0
DQ Buffer
COMMAND
DECODER
DQ31
CONTROL
SIGNAL
GENERATOR
DQM0~3
Row
Decoder
CS#
RAS#
CAS#
WE#
4096 x 256 x 32
CELL ARRAY
(BANK #0)
COLUMN
COUNTER
~
CLK
Row
Decoder
Figure 3. Block Diagram
4096 x 256 x 32
CELL ARRAY
(BANK #1)
Column Decoder
MODE
REGISTER
4096 x256 x 32
CELL ARRAY
(BANK #2)
Column Decoder
REFRESH
COUNTER
Row
Decoder
A9
A11
BA0
BA1
ADDRESS
BUFFER
Row
Decoder
~
A0
4096 x 256 x 32
CELL ARRAY
(BANK #3)
Column Decoder
Rev. 2.1
4
Aug. /2015
EtronTech
EM639325
Pin Descriptions
Table 3. Pin Details
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE
goes low synchronously with clock(set-up and hold time same as other inputs), the
internal clock is suspended from the next clock cycle and the state of output and
burst address is frozen as long as the CKE remains low. When all banks are in the
idle state, deactivating the clock controls the entry to the Power Down and Self
Refresh modes. CKE is synchronous except after the device enters Power Down
and Self Refresh modes, where CKE becomes asynchronous until exiting the same
mode. The input buffers, including CLK, are disabled during Power Down and Self
Refresh modes, providing low standby power.
BA0, BA1
Input
Bank Activate: BA0 and BA1 defines to which bank the BankActivate, Read, Write,
or BankPrecharge command is being applied. The bank address BA0 and BA1 is
used latched in mode register set.
A0-A11
Input
Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 1M available in the
respective bank. During a Precharge command, A10 is sampled to determine if all
banks are to be precharged (A10 = HIGH). The address inputs also provide the opcode during a Mode Register Set or Special Mode Register Set command.
CS#
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
RAS#
Input
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH,"
either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH," the BankActivate command is
selected and the bank designated by BA is turned on to the active state. When the
WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
CAS#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is
started by asserting CAS# "LOW." Then, the Read or Write command is selected by
asserting WE# "LOW" or "HIGH."
WE#
Input
Write Enable: The WE# signal defines the operation commands in conjunction with
the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE#
input is used to select the BankActivate or Precharge command and Read or Write
command.
DQM0DQM3
Input
Data Input/Output Mask: Data Input Mask: DQM0-DQM3 are byte specific. Input
data is masked when DQM is sampled HIGH during a write cycle. DQM3 masks
DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0
masks DQ7-DQ0.
DQ0DQ31
Input/
Output
Data I/O: The DQ0-31 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
Rev. 2.1
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Aug. /2015
EtronTech
EM639325
No Connect: These pins should be left unconnected.
NC
-
VDDQ
Supply
DQ Power: Provide isolated power to DQs for improved noise immunity.
VSSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VDD
Supply
Power Supply: 3.3V ±0.3V.
VSS
Supply
Ground
Rev. 2.1
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Aug. /2015
EtronTech
EM639325
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 4 shows the truth table for the operation commands.
Table 4. Truth Table (Note (1), (2))
Command
BankActivate
State
CKEn-1 CKEn DQM(6) BA0,1 A10 A11, A9-0 CS# RAS# CAS# WE#
Idle(3)
H
X
X
V
Row address
L
L
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
Write
Active(3)
H
X
V
V
L
L
H
L
L
Write and AutoPrecharge
Active(3)
H
X
V
V
H
Column
address
(A0 ~ A7)
L
H
L
L
Read
Active(3)
H
X
V
V
L
L
H
L
H
Read and Autoprecharge
Active(3)
H
X
V
V
H
L
H
L
H
Mode Register Set
Idle
H
X
X
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
Active(4)
H
X
X
X
X
X
L
H
H
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
SelfRefresh Exit
Idle
L
H
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
X
X
X
L
H
H
H
Burst Stop
Column
address
(A0 ~ A7)
OP code
(SelfRefresh)
Clock Suspend Mode Entry
Active
Power Down Mode Entry
Any(5)
Clock Suspend Mode Exit
H
H
L
L
X
X
X
X
X
X
X
X
Active
L
H
X
X
X
X
X
X
X
X
Any
L
H
X
X
X
X
H
X
X
X
L
H
H
H
X
X
X
X
Active
H
X
H
X
X
X
X
X
X
Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DQM0-3
X
Power Down Mode Exit
(PowerDown)
Data Write/Output Enable
Active
H
X
L
X
Data Mask/Output Disable
Rev. 2.1
7
X
X
Aug. /2015
EtronTech
EM639325
Commands
1
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BA 0,1= Bank, A0-A11 = Row Address)
The BankActivate command activates the idle bank designated by the BA0,1 (Bank Activate)
signal. By latching the row address on A0 to A11 at the time of this command, the selected row
access is initiated. The read or write operation in the same bank can occur after a time delay of
tRCD(min.) from the time of bank activation. A subsequent BankActivate command to a different row
in the same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The minimum time interval between successive BankActivate commands to the
same bank is defined by tRC(min.). The SDRAM has four internal banks on the same chip and shares
part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of
the two banks. tRRD(min.) specifies the minimum time required between activating different banks.
After this command is used, the Write command performs the no mask write operation.
Figure 4. BankActivate Command Cycle (Burst Length = n)
T0
T1
T2
T3
Tn+3
Tn+4
Tn+5
Tn+6
CLK
ADDRESS
Bank A
Row Addr.
Bank A
Col Addr.
Bank B
Row Addr.
RAS# - CAS# delay(tRCD)
COMMAND
Bank A
Activate
NOP
NOP
Bank A
Row Addr.
RAS# - RAS# delay time(tRRD)
Bank B
Activate
R/W A with
AutoPrecharge
NOP
NOP
Bank A
Activate
RAS# - Cycle time(tRC)
AutoPrecharge
Begin
Don’t Care
2
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BA0, 1 = Bank, A10 = "L", A0-A9, A11 = Don't care)
The BankPrecharge command precharges the bank designated by BA0, 1 signal. The
precharged bank is switched from the active state to the idle state. This command can be asserted
anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The
maximum time any bank can be active is specified by tRAS(max.). Therefore, the precharge function
must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged
bank is still in the idle state and is ready to be activated again.
3
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BA0,1 = Don’t care, A10 = "H", A0-A9, A11 = Don't care)
The PrechargeAll command precharges all the four banks simultaneously and can be issued
even if all banks are not in the active state. All banks are then switched to the idle state.
4
Read command
(RAS# = "H", CAS# = "L", WE# = "H", BA0, 1 = Bank, A10 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS latency after the issue of the Read command. Each subsequent data-out
element will be valid by the next positive clock edge (refer to the following figure). The DQs go into
high-impedance at the end of the burst unless other command is initiated. The burst length, burst
sequence, and CAS latency are determined by the mode register which is already programmed. A
full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and
continue).
Rev. 2.1
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Aug. /2015
EtronTech
EM639325
Figure 5. Burst Read Operation (Burst Length = 4, CAS# Latency = 2, 3)
T0
T1
READ A
NOP
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS# latency=2
tCK2, DQ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CAS# latency=3
tCK3, DQ
DOUT A0 DOUT A1 DOUT A2
DOUT A3
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.
DQM latency is two clocks for output buffers). A read burst without the auto precharge function may
be interrupted by a subsequent Read or Write command to the same bank or the other active bank
before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank too. The interrupt coming from the Read command can occur on any
clock cycle following a previous Read command (refer to the following figure).
Figure 6. Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS# latency=2
tCK2, DQ
READ A
READ B
NOP
DOUT A0
CAS# latency=3
tCK3, DQ
NOP
NOP
NOP
DOUT B0
DOUT B1
DOUT B2
DOUT A0
DOUT B0
DOUT B1
NOP
NOP
NOP
DOUT B3
DOUT B2
DOUT B3
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from
a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
single cycle with high-impedance on the DQ pins must occur between the last read data and the
Write command (refer to the following figure). If the data output of the burst read occurs at the
second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the
Write command to avoid internal bus contention.
Rev. 2.1
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Aug. /2015
EtronTech
EM639325
Figure 7. Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T9
T8
CLK
DQM
COMMAND
NOP
NOP
BANKA
ACTIVATE
NOP
CAS# latency=2
tCK2, DQ
READ A
NOP
WRITE
A
NOP
NOP
DIN A0
DIN A1
DIN A2
NOP
DIN A3
Must be Hi-Z before
the Write Command
Figure 8. Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 2)
CLK
T0
T1
T2
T3
T4
T5
T6
T7
T8
DQM
COMMAND
NOP
NOP
READ A
NOP
CAS# latency=2
tCK2, DQ
NOP
WRITE B
DIN B0
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
Must be Hi-Z before
the Write Command
Don’t Care
Figure 9. Read to Write Interval (Burst Length ≧ 4, CAS# Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
READ A
NOP
NOP
CAS# Latency=3
tCK3, DQ
NOP
DOUT A0
NOP
WRITE B
NOP
NOP
DIN B0
DIN B1
DIN B2
Must be Hi-Z before
the Write Command
Don’t Care
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS latency.
Rev. 2.1
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Aug. /2015
EtronTech
EM639325
Figure 10. Read to Precharge (CAS# Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
ADDRESS
Bank,
Col A
Bank
Row
Bank(s)
tRP
COMMAND
READ A
NOP
CAS# latency=2
tCK2, DQ
NOP
NOP
Precharge
NOP
NOP
Activate
NOP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CAS# latency=3
tCK3, DQ
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Don’t Care
5
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BA = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the
read operation. Once this command is given, any subsequent command cannot occur within a time
delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
6
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BA = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
Figure 11. Burst Write Operation (Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
DQ
NOP
WRITE A
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
The first data element and the write
are registered on the same clock edge
NOP
NOP
NOP
NOP
Don’t Care
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
Rev. 2.1
11
Aug. /2015
EtronTech
EM639325
Figure 12. Write Interrupted by a Write (Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
DQ
WRITE A
WRITE B
NOP
NOP
NOP
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
NOP
NOP
NOP
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
Figure 13. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE A
CAS# latency=2
tCK2, DQ
DIN A0
CAS# latency=3
tCK3, DQ
DIN A0
READ B
NOP
NOP
NOP
NOP
NOP
NOP
DOUT B0 DOUT B1 DOUT B2 DOUT B3
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Input data must be removed from the DQ at least one clock cycle before
the Read data appears on the outputs to avoid data contention
Don’t Care
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
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EM639325
Figure 14. Write to Precharge
T0
CLK
T1
T2
T3
T4
T5
T6
T7
Activate
NOP
DQM
tRP
COMMAND
WRITE
ADDRESS
BANK
COL n
NOP
NOP
Precharge
NOP
NOP
BANK(S)
ROW
tWR
DIN
N+1
DIN
N
DQ
Don’t Care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
7
Write and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "L", BA = Bank, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed
in this command and the auto precharge function is ignored.
Figure 15. Burst Write with Auto-Precharge (Burst Length = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
COMMAND
Bank A
Activate
NOP
NOP
WRITE A
Auto Precharge
NOP
NOP
NOP
NOP
NOP
Bank A
Activate
tDAL
DQ
DIN A0
tDAL=tWR+tRP
8
DIN A1
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued
at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to
the mode register. Two clock cycles are required to complete the write in the mode register (refer to
the following figure). The contents of the mode register can be changed using the same command
and the clock cycle requirements during operation as long as all banks are in the idle state.
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EM639325
Table 5. Mode Register Bitmap
BA1
0
A9
0
1
BA0
0
A11
0
A10
A9
0 W.B.L
Write Burst Length
Burst
Single Bit
A6
0
0
0
0
1
A8
0
1
0
A8
A7
A6
A5
A4
CAS Latency
TM
A7
0
0
1
Test Mode
Normal
Reserved
Reserved
A3
BT
A3
0
1
A2
A1
A0
Burst Length
Burst Type
Sequential
Interleave
A5
0
0
1
1
0
A4
CAS Latency
A2
A1
A0
Burst Length
0
Reserved
0
0
0
1
1
Reserved
0
0
1
2
0
2 clocks
0
1
0
4
1
3 clocks
0
1
1
8
0
Reserved
1
1
1 Full Page (Sequential)
All other Reserved
All other Reserved
Note: Column address is repeated until terminated in Full Page Mode
Figure 16. Mode Register Set Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
tMRD
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A9,
A11
DQM
DQ
tRP
Hi-Z
PrechargeAll
Rev. 2.1
Mode Register
Set Command
14
Any
Command
Don’t Care
Aug. /2015
EtronTech
EM639325
• Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 6. Burst Definition
Start Address
A2
A1
A0
X
X
0
X
X
1
X
0
0
X
0
1
X
1
0
X
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Burst Length
2
4
8
Full page
9
location = 0-255
Sequential
Interleave
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
n, n+1, n+2, n+3, …255, 0,
1, 2, … n-1, n, …
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Not Support
No-Operation command (RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is
Low). This prevents unwanted commands from being registered during idle or wait states.
10
Burst Stop command (RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS latency (refer to the following figure). The termination
of a write burst is shown in the following figure.
Figure 17. Termination of a Burst Read Operation
(Burst Length＞4, CAS# Latency = 2, 3)
T0
T1
T2
T3
READ A
NOP
NOP
NOP
CLK
COMMAND
CAS# latency=2
tCK2, DQ
CAS# latency=3
tCK3, DQ
Rev. 2.1
T4
Burst
Stop
T5
NOP
T6
NOP
T7
NOP
T8
NOP
The burst ends after a delay equal to the CAS# latency
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
15
DOUT A3
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EtronTech
EM639325
Figure 18. Termination of a Burst Write Operation (Burst Length = X)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
DQ
NOP
Burst
Stop
WRITE A
NOP
NOP
DIN A0
DIN A1
DIN A2
NOP
NOP
NOP
NOP
Don’t Care
11 Device Deselect command (CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.
12
AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", BA0,1 = “Don‘t care, A0-A11 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 4096 times within 64ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to
be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.
13
SelfRefresh Entry command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A11 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by
restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
14 SelfRefresh Exit command
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP
or Device Deselect commands must be issued for tRC(min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
15
Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended (masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command
performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are
turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown
state longer than the refresh period (64ms) since the command does not perform any refresh
operations.
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16
Clock Suspend Mode Exit / PowerDown Mode Exit command
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from
the subsequent cycle by providing this command (asserting CKE "HIGH", the command should be
NOP or deselect). When the device is in the PowerDown mode, the device exits this mode and all
disabled buffers are turned on to the active state. tXSR(min.) is required when the device exits from
the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end
of this command.
17
Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of the
input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also
used for device selection, byte selection and bus control in a memory system.
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Table 7. Absolute Maximum Rating
Symbol
VIN, VOUT
Item
Input, Output Voltage
Values
-1.0 ~ 4.6
Unit
V
VDD, VDDQ
Power Supply Voltage
-1.0 ~ 4.6
V
TA
Ambient Temperature
-40 ~ 85
°C
TSTG
Storage Temperature
-55 ~ 150
°C
PD
Power Dissipation
1.1
W
IOS
Short Circuit Output Current
50
mA
Note
Note: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
Table 8. Recommended D.C. Operating Conditions (VDD = 3.3V ±0.3V, TA = -40~85°C)
Symbol
Parameter/ Condition
Min.
Typ.
Max.
Unit
Note
VDD
DRAM Core Supply Voltage
3.0
3.3
3.6
V
2
VDDQ
I/O Supply Voltage
3.0
3.3
3.6
V
2
VIH
Input High Level Voltage
2
-
VDDQ+0.3
V
2
VIL
Input Low Level Voltage
-0.3
-
0.8
V
2
-10
-
10
µA
-10
-
10
µA
IIL
Input Leakage Current
( 0V≦VIN≦VDD, All other pins not under test = 0V )
IOZ
Output Leakage Current
(Output Disable, 0V≦VIN≦VDDQ )
VOH
Output High Level Voltage ( IOUT = -2mA )
2.4
-
-
V
VOL
Output Low Level Voltage ( IOUT = 2mA )
-
-
0.4
V
Table 9. Capacitance (VDD = 3.3V, f = 1MHz, TA = 25°C)
Symbol
CI
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
Min.
3.5
5.5
Max.
5.5
7.5
Unit
pF
pF
Note: These parameters are periodically sampled and are not 100% tested.
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Table 10. D.C. Characteristics (VDD = 3.3V ±0.3V, TA = -40~85°C)
Description/Test condition
Operating Current
tRC ≥ tRC(min), Outputs Open, One bank active
Precharge Standby Current in power down mode
tCK = 15ns, CKE ≤ VIL(max)
Precharge Standby Current in power down mode
tCK = ∞, CKE ≤ VIL(max)
Precharge Standby Current in non-power down mode
tCK = 15ns, CS# ≥ VIH(min), CKE ≥ VIH
Input signals are changed every 2clks
Precharge Standby Current in non-power down mode
tCK = ∞, CLK ≤ VIL(max), CKE ≥ VIH
Active Standby Current in non-power down mode
tCK = 15ns, CKE ≥ VIH(min), CS# ≥ VIH(min)
Input signals are changed every 2clks
Active Standby Current in non-power down mode
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
Operating Current (Burst mode)
tCK =tCK(min), Outputs Open, Multi-bank interleave
Refresh Current
tRC ≥ tRC(min)
Self Refresh Current
CKE ≤ 0.2V ; for other inputs VIH≧VDD - 0.2V, VIL ≤ 0.2V
Rev. 2.1
-5I
-6I
Max.
-7I
IDD1
200
160
140
IDD2P
3
3
3
IDD2PS
3
3
3
50
50
50
30
30
30
Symbol
19
IDD2N
IDD2NS
Unit Note
3
mA
IDD3N
60
60
60
IDD3NS
50
50
50
IDD4
240
200
170
3, 4
IDD5
300
260
230
3
IDD6
3
3
3
Aug. /2015
EtronTech
EM639325
Table 11. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V ±0.3V, TA = -40~85°C) (Note: 5~8)
Symbol
-5I
Min. Max.
A.C. Parameter
-6I
Min. Max.
-7I
Min. Max.
tRC
Row cycle time (same bank)
55
-
60
-
63
-
tRCD
RAS# to CAS# delay (same bank)
15
-
18
-
21
-
tRP
Precharge to refresh / row activate
command (same bank)
Row activate to row active delay
15
-
18
-
21
-
tRRD
(different banks)
tRAS
Row activate to precharge time
(same bank)
Unit Note
ns
10
-
12
-
14
-
40
100K
42
100K
42
100K
tWR
Write recovery time
2
-
2
-
2
-
tCCD
CAS# to CAS# Delay time
1
-
1
-
1
-
Clock cycle time
CL* = 2
-
-
10
-
10
-
tCK
CL* = 3
5
-
6
-
7
-
tCH
Clock high time
2
-
2.5
-
2.5
-
tCL
Clock low time
2
-
2.5
-
2.5
-
tCK
ns
9
10
10
Access time from CLK
CL* = 2
-
-
-
6
-
6.5
tAC
(positive edge)
CL* = 3
-
5
-
5.4
-
5.4
tOH
Data output hold time
2
-
2.5
-
2.5
-
tLZ
Data output low impedance
1
-
1
-
1
-
tHZ
Data output high impedance CL* = 3
-
5
-
5.4
-
5.4
tIS
Data/Address/Control Input set-up time
1.5
-
1.5
-
1.5
-
tIH
Data/Address/Control Input hold time
0.8
-
0.8
-
0.8
-
ns
tPDE
PowerDown Exit Setup Time
tIS+tCK
-
tIS+tCK
-
tIS+tCK
-
ns
tMRD
Mode Register Set Command Cycle Time
2
-
2
-
2
-
tCK
tREFI
Refresh Interval Time
-
15.6
-
15.6
-
15.6
µs
tXSR
Exit Self-Refresh to any Command
tRC+tIS
-
tRC+tIS
-
tRC+tIS
-
ns
9
ns
8
10
10
*CL is CAS Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width ≦3ns. VIL(Min) = -1.0V for pulse
width ≦ 3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
6. A.C. Test Conditions
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EM639325
Table 12. LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels (VIH /VIL)
2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
1.4V
3.3V
50Ω
1.2KΩ
Output
Output
30pF
Z0=50Ω
870Ω
Figure 19.1 LVTTL D.C. Test Load (A)
30pF
Figure 19.2 LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. If clock rising time is longer than 1 ns, (tR / 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time tT (tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ (simultaneously) when CKE= “L”, DQM= “H” and all input
signals are held "NOP" state.
2) Start clock and maintain stable condition for minimum 200 µs, then bring CKE= “H” and, it is
recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
* The Auto Refresh command can be issue before or after Mode Register Set command
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EM639325
Timing Waveforms
Figure 20. AC Parameters for Write Timing (Burst Length=4)
T0
CLK
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCH
tCL
CKE
tIS
tIS
Begin Auto
Precharge Bank A
tIH
Begin Auto
Precharge Bank B
CS#
RAS#
CAS#
WE#
BA0,1
tIH
A10
RAx
RBx
RAy
tIS
A0-A9,
A11
RAx
CAx
RBx
CBx
RAy
CAy
DQM
tRCD
tDAL
tIS
tRC
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Ax1
Write with
Auto Precharge
Command
Bank A
Ax2
Activate
Command
Bank B
tWR
tIH
Ax3
Bx0
Bx1
Write with
Auto Precharge
Command
Bank B
Bx2
Bx3
Ay0
Activate
Command
Bank A
Write
Command
Bank A
Ay1
Ay2
Ay3
Precharge
Command
Bank A
Don’t Care
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EM639325
Figure 21. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=3)
T0
CLK
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
tCH tCL
CKE
tIS
Begin Auto
Precharge Bank B
tIS
tIH
tIH
CS#
RAS#
CAS#
WE#
BA0,1
tIH
A10
RAx
RBx
RAy
tIS
A0-A9,
A11
RAx
CAx
RBx
CBx
RAy
tRRD
tRAS
DQM
tRC
tAC
tRCD
tHZ
tLZ
DQ
Hi-Z
Ax0
Ax1
Read
Command
Bank A
Activate
Command
Bank B
Bx0
Bx1
tHZ
tOH
Activate
Command
Bank A
tRP
Read with
Precharge
Auto Precharge Command
Command
Bank A
Bank B
Activate
Command
Bank A
Don’t Care
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EM639325
Figure 22. Auto Refresh (Burst Length=4, CAS# Latency=3)
T0
T1
T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
tRP
tRC
tRC
CAx
tRCD
DQM
DQ
Ax0
Precharge All
Command
Auto Refresh
Command
Auto Refresh
Command
Activate
Command
Bank A
Read
Command
Bank A
Don’t Care
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EM639325
Figure 23. Power on Sequence and Auto Refresh
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High Level
Is reguired
Minimum for 2 Refresh Cycles are required
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A9,
A11
DQM
DQ
tRP
tMRD
Hi-Z
Precharge All
Command
Inputs must be
Stable for
200µs
Mode Register
Set Command
1st Auto Refresh(*)
Command
2nd Auto Refresh(*)
Command
Any
Command
Don’t Care
Note(*): The Auto Refresh command can be issue before or after Mode Register Set command
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EM639325
Figure 24. Self Refresh Entry & Exit Cycle
T0
T1 T2 T3 T4
CLK
*Note 1
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
*Note 2
CKE
tXSR
*Note 5
*Note 3,4
*Note 8
tPDE
tIS tIH
*Note 6
tIS
CS#
*Note 7
RAS#
*Note 9
CAS#
WE#
BA0,1
A10
A0-A9,
A11
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Exit
Self Refresh Entry
Auto Refresh
Don’t Care
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
5.
6.
7.
8.
9.
To Exit SelfRefresh Mode
System clock restart and be stable before returning CKE high.
Enable CKE and CKE should be set high for valid setup time and hold time.
CS# starts from high.
Minimum tXSR is required after CKE going high to complete SelfRefresh exit.
4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Rev. 2.1
26
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EtronTech
EM639325
Figure 25. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
DQ
tHZ
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Ax3
Clock Suspend
3 Cycles
Don’t Care
Rev. 2.1
27
Aug. /2015
EtronTech
EM639325
Figure 26. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
DQ
Hi-Z
DAx0
Activate
Command
Bank A
Rev. 2.1
DAx1
Clock Suspend
1 Cycle
Write
Command
Bank A
DAx2
DAx3
Clock Suspend
3 Cycles
Clock Suspend
2 Cycles
Don’t Care
28
Aug. /2015
EtronTech
EM639325
Figure 27. Power Down Mode and Clock Suspension (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
CLK
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tIH tIS
tPDE
CKE
Valid
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
DQ
tHZ
Hi-Z
Ax0
ACTIVE
Activate
Read
STANDBY
Command
Command
Bank A
Bank A
Power Down
Power Down
Mode Exit
Mode Entry
Rev. 2.1
Ax1
Clock Suspension
Start
Ax2
Ax3
Clock Suspension
End
Precharge
Command
Bank A
Power Down
Mode Entry
29
PRECHARGE
STANDBY
Power Down
Mode Exit
Any
Command
Don’t Care
Aug. /2015
EtronTech
EM639325
Figure 28. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAw
A0-A9,
A11
RAw
RAz
CAw
CAx
CAy
RAz
CAz
DQM
DQ
Hi-Z
Aw0
Activate
Command
Bank A
Read
Command
Bank A
Aw1
Aw2
Read
Command
Bank A
Aw3
Ax0
Read
Command
Bank A
Ax1
Ay0
Ay1
Ay2
Precharge
Command
Bank A
Ay3
Activate
Command
Bank A
Read
Command
Bank A
Don’t Care
Rev. 2.1
30
Aug. /2015
EtronTech
EM639325
Figure 29. Random Column Write (Page within same Bank)
(Burst Length=4)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBw
A0-A9,
A11
RBw
RBz
CBw
CBx
CBy
RBz
CBz
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0
Activate
Command
Bank B
Write
Command
Bank B
DBx1
Write
Command
Bank B
DBy0 DBy1 DBy2
Write
Command
Bank B
DBy3
DBz0
Precharge
Command
Bank B
Activate
Command
Bank B
DBz1
Write
Command
Bank B
Don’t Care
Rev. 2.1
31
Aug. /2015
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EM639325
Figure 30. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBx
A0-A9,
A11
RBx
CBx
Hi-Z
Activate
Command
Bank B
RBy
RAx
CAx
RBy
tAC
tRCD
DQM
DQ
RAx
tRP
Bx0
Read
Command
Bank B
CBy
Bx1
Bx2
Bx3
Bx4
Activate
Command
Bank A
Bx5
Bx6
Read
Command
Bank A
Bx7
Ax0
Precharge
Command
Bank B
Ax1
Ax2
Ax3
Activate
Command
Bank B
Ax4
Ax5
Ax6
Read
Command
Bank B
Ax7
By0
Precharge
Command
Bank A
Don’t Care
Rev. 2.1
32
Aug. /2015
EtronTech
EM639325
Figure 31. Random Row Write (Interleaving Banks)
(Burst Length=8)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
RAy
RBx
CBx
tRCD
DQM
DQ
RBx
Hi-Z
Activate
Command
Bank A
tWR*
DAx0
DAx1
Write
Command
Bank A
DAx2 DAx3
DAx4
DAx5 DAx6
Activate
Command
Bank B
DAx7
DBx0
CAy
tRP
DBx1 DBx2 DBx3
Write
Command
Bank B
Precharge
Command
Bank A
tWR*
DBx4
DBx5 DBx6
Activate
Command
Bank A
DBx7
DAy0
DAy1 DAy2
Write
Command
Bank A
DAy3
Precharge
Command
Bank B
Don’t Care
*tWR>tWR (min.)
Rev. 2.1
RAy
33
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EtronTech
EM639325
Figure 32. Read and Write Cycle (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
CAy
CAz
DQM
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Rev. 2.1
Ax1
Ax2
Ax3
Read
Command
Bank A
DAy0 DAy1
Write
Command
Bank A
34
DAy3
The Write Data
is Masked with a
Zero Clock
Read
Latency
Command
Bank A
Az0
Az1
Az3
The Read Data
is Masked with a
Two Clock
Latency
Don’t Care
Aug. /2015
EtronTech
EM639325
Figure 33. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBx
CAx
RBx
CBx
CBy
CBz
CAy
tRCD
DQM
tAC
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Rev. 2.1
Read
Command
Bank A
Activate
Command
Bank B
Ax1
Ax2
Read
Command
Bank B
Ax3
Bx0
Read
Command
Bank B
Bx1
By0
Read
Command
Bank B
By1
Bz0
Read
Command
Bank A
Bz1
Ay0
Precharge
Command
Bank B
Ay1
Ay2
Ay3
Precharge
Command
Bank A
Don’t Care
35
Aug. /2015
EtronTech
EM639325
Figure 34. Interleaved Column Write Cycle (Burst Length=4)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBw
CAx
RBw
CBw
CBx
CBy
CAy
CBz
tWR
tRCD
tWR
DQM
tRRD>tRRD (min)
DQ
Hi-Z
DAx0
Activate
Command
Bank A
Rev. 2.1
DAx1
DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
36
DBy1
Write
Command
Bank B
DAy0 DAy1 DBz0
Write
Command
Bank A
DBz1
DBz2
Write
Command
Bank B
Precharge
Command
Bank A
DBz3
Precharge
Command
Bank B
Don’t Care
Aug. /2015
EtronTech
EM639325
Figure 35. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBy
RBx
CAx
RBx
CBx
CAy
RBy
CBy
tRP
DQM
DQ
Hi-Z
Activate
Command
Bank A
Rev. 2.1
Ax0
Read
Command
Bank A
Activate
Command
Bank B
Ax1
Ax2
Ax3
Bx0
Read with
Auto Precharge
Command
Bank B
Bx1
Bx2
Read with
Auto Precharge
Command
Bank A
Bx3
Ay0
Ay1
Activate
Command
Bank B
Ay2
Ay3
By0
By1
By2
Read with
Auto Precharge
Command
Bank B
Don’t Care
37
Aug. /2015
EtronTech
EM639325
Figure 36. Auto Precharge after Write Burst (Burst Length=4)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBy
RBx
CAx
RBx
CBx
CAy
RBy
CBy
tDAL
DQM
DQ
Hi-Z
Activate
Command
Bank A
Rev. 2.1
DAx0 DAx1
DAx2
Write
Command
Bank A
Activate
Command
Bank B
DAx3
DBx0 DBx1 DBx2
DBx3
Write with
Auto Precharge
Command
Bank B
DAy0 DAy1 DAy2
Write with
Auto Precharge
Command
Bank A
DAy3
DBy0 DBy1 DBy2
Activate
Command
Bank B
DBy3
Write with
Auto Precharge
Command
Bank B
Don’t Care
38
Aug. /2015
EtronTech
EM639325
Figure 37. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBy
RBx
CAx
RBx
CBx
RBy
tRP
DQM
DQ
Hi-Z
Activate
Command
Bank A
Ax
Read
Command
Bank A
Activate
Command
Bank B
Ax+1
Ax+2
Ax-2
Ax-1
Ax
Ax+1
Bx
Bx+1
Bx+2
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Bx+3
Bx+4
Bx+5
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
Don’t Care
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Rev. 2.1
39
Aug. /2015
EtronTech
EM639325
Figure 38. Full Page Write Cycle (Burst Length=Full Page)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RBy
RBx
CAx
RBx
CBx
RBy
DQM
Data is ignored
DQ
Hi-Z
Activate
Command
Bank A
Rev. 2.1
DAx
DAx+1
Write
Command
Bank A
DAx+2
DAx+3
DAx-1
DAx
DAx+1
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
DBx
DBx+1
DBx+2
DBx+3
DBx+4
DBx+5
Write
Command
Bank B
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
40
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
Don’t Care
Aug. /2015
EtronTech
EM639325
Figure 39. Byte Read and Write Operation (Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
T5 T6
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0, 1
A10
RAx
A0-A9,
A11
RAx
CAx
CAy
CAz
DQM m
DQM n
DQ M
Ax0
DQ N
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Ax1
Ax2
Upper Byte
is masked
DAy1
Ax3
DAy0
Lower Byte
is masked
DAy1
Write
Command
Bank A
Day2
DAy3
Upper Byte
is masked
Az0
Read
Command
Bank A
Lower Byte
is masked
Az1
Az2
Az1
Az2
Az3
Lower Byte
is masked
Don’t Care
Note : M represent DQ in the byte m; N represent DQ in the byte n.
Rev. 2.1
41
Aug. /2015
EtronTech
EM639325
Figure 40. Random Row Read (Interleaving Banks)
(Burst Length=4, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0, 1
A10
RAx
RBx
A0-A9,
A11
RAx
RBx
RBw
CAx
CBx
CBy
CAy
CBz
RBw
tRP
DQM
tRRD
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Rev. 2.1
tRCD
Ax1
Activate
Read
Command
Command
Bank B
Bank B
Read
Read
Command
Command
Bank A
Bank A
Bx0
Ay0
Read
Command
Bank B
Ay1
By0
By1
By2
By3
Read
Command
Bank B
Bz0
Bz1
Bz2
Precharge
Activate
Command Bank B
Command
(Precharge Temination) Bank B
Don’t Care
42
Aug. /2015
EtronTech
EM639325
Figure 41. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBx
A0-A9,
A11
RAx
RBx
RBw
CAx
CBx
CAy
CBy
CAz
CBz
RBw
tRP
DQM
tRRD
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Rev. 2.1
tRCD
Ax1
Activate
Read
Command
Command
Bank B
Bank B
Read
Read
Command
Command
Bank A
Bank A
Bx0
Ay0
Read
Command
Bank B
Ay1
By0
Read
Command
Bank A
By1
Az0
Az1
Read
Command
Bank B
Az2
Bz0
Bz1
Bz2
Precharge
Activate
Command Bank B
Command
(Precharge Temination) Bank B
Don’t Care
43
Aug. /2015
EtronTech
EM639325
Figure 42. Full Page Random Column Write (Burst Length=Full Page)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBx
A0-A9,
A11
RAx
RBx
RBw
CAx
CBx
CBy
CAy
CAz
CBz
RBw
tWR
tRP
DQM
tRRD
DQ
Hi-Z
DAx0 DAx1
Activate
Command
Bank A
Rev. 2.1
tRCD
Activate
Command
Bank B
Write
Command
Bank A
DBx0
DAy0
DAy1 DBy0 DBy1
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
DAz0
DAz1
Write
Command
Bank A
DAz2
DBz0
DBz1
Write
Command
Bank B
DBz2
Precharge
Activate
Command Bank B
Command
(Precharge Temination) Bank B
Write Data
are masked
44
Don’t Care
Aug. /2015
EtronTech
EM639325
Figure 43. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0
T1 T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
RAy
CAx
RAy
tWR
RAz
CAy
RAz
tRP
tRP
DQM
DQ
DAx0 DAx1
Activate
Command
Bank B
Rev. 2.1
Precharge
Write
Command
Command
Bank A
Bank A
Precharge Termination
of a Write Burst
Write Data are masked
Ay0
Activate
Command
Bank A
Read
Command
Bank A
Ay1
Precharge
Command
Bank A
Ay2
Activate
Command
Bank A
Precharge Termination
of a Read Burst
Don’t Care
45
Aug. /2015
EtronTech
EM639325
Figure 44. 86 Pin TSOP II Package Outline Drawing Information
86
0.254
HE
E
44
θ°
L
L1
A1 A2
e
B
S
Symbol
A
A1
A2
B
C
D
E
e
HE
L
L1
S
y
θ
C
43
D
A
1
L
L1
y
Dimension in inch
Min
Normal
Max
0.047
－
－
0.002
0.004
0.008
0.035
0.039
0.043
0.007
0.009
0.011
0.005
－
－
0.87
0.875
0.88
0.395
0.400
0.405
0.0197
－
－
0.455
0.463
0.471
0.016
0.020
0.024
0.0315
－
－
0.024
－
－
0.004
－
－
－
0°
8°
Min
－
0.05
0.9
0.17
－
22.09
10.03
－
11.56
0.40
－
－
－
0°
Dimension in mm
Normal
－
0.10
1
0.22
0.127
22.22
10.16
0.50
11.76
0.50
0.80
0.61
－
－
Max
1.20
0.2
1.1
0.27
－
22.35
10.29
－
11.96
0.60
－
－
0.10
8°
Notes:
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension: mm
Rev. 2.1
46
Aug. /2015
EtronTech
EM639325
Figure 45. 90 ball FBGA 8x13x1.2mm(max.) Outline Drawing Information
PIN #1
Top View
Bottom View
Side View
DETAIL : "A"
Symbol
A
A1
A2
C
D
E
D1
E1
e
b
F
Rev. 2.1
Dimension in inch
Dimension in mm
Min
Nom Max
Min
Nom Max
--0.047
--1.20
0.012 0.014 0.016 0.30 0.35 0.40
0.027 0.029 0.031 0.69 0.74 0.79
0.007 0.008 0.010 0.17 0.21 0.25
0.311 0.315 0.319 7.90 8.00 8.10
0.508 0.512 0.516 12.90 13.00 13.10
-0.252
--6.40
--0.441
--11.2
--0.031
--0.80
-0.016 0.018 0.020 0.40 0.45 0.50
-0.126
--3.2
-47
Aug. /2015