Keysight DSOX4FPGAX Infiniivision mso dynamic probe Datasheet

Keysight Technologies
InfiniiVision MSO Dynamic Probe for
Xilinx FPGAs (N5406A and DSOX4FPGAX,
and DSOX6FPGAX)
Data Sheet
Figure 1. FPGA dynamic probe for Xilinx used in conjunction with a Keysight InfiniiVision 6000, 7000, or 4000 or 6000
X-Series MSO provides an effective solution for simple through complex debugging of systems incorporating Xilinx FPGAs.
02 | Keysight | InfiniiVision MSO Dynamic Probe for Xilinx FPGAs (N5406A and DSOX4FPGAX, and DSOX6FPGAX) - Data Sheet
The challenge
You rely on the insight a MSO (mixed-signal oscilloscope) provides to understand the
behavior of your FPGA in the context of the surrounding system. Design engineers
typically take advantage of the programmability of the FPGA to route internal nodes to
a small number of physical pins for debugging. While this approach is very useful, it has
significant limitations.
–– Since pins on the FPGA are typically an expensive resource, there are a relatively
small number available for debug. This limits internal visibility (i.e. one pin is required
for each internal signal to be probed).
–– When you need to access different internal signals, you must change your design to
route these signals to the available pins. This can be time consuming and can affect
the timing of your FPGA design.
–– Finally, the process required to map the signal names from your FPGA design to the
MSO digital channel labels is manual and tedious.
–– When new signals are routed out, you need to manually update these signal names
on the MSO, which takes additional time and is a potential source of confusing
errors.
03 | Keysight | InfiniiVision MSO Dynamic Probe for Xilinx FPGAs (N5406A and DSOX4FPGAX, and DSOX6FPGAX) - Data Sheet
Debug Your FPGAs Faster and More Effectively With a MSO
A better way
Collaborative development between
Keysight Technologies, Inc. and Xilinx have
produced a faster and more effective way
to use your MSO to debug FPGAs and the
surrounding system. The Keysight FPGA
dynamic probe, used in conjunction with a
Keysight MSO, provides the most effective
solution for simple through complex
debugging.
View internal activity
With the digital channels on your MSO, you
are normally limited to measuring signals
at the periphery of the FPGA. With the
FPGA dynamic probe, you can now access
signals internal to the FPGA. You can
measure up to 64 internal signals for each
external pin dedicated to debug, unlocking
visibility into your design that you never
had before.
Moving probe points internal to an FPGA
used to be time consuming. Now, in less
than a second, you can easily measure
different sets of internal signals without
design changes. FPGA timing stays
constant when you select new sets of
internal signals for probing.
The FPGA dynamic probe maps internal
signal names from your FPGA design
tool to your Keysight MSO. Eliminate
unintentional mistakes and save hours of
time with this automatic setup of signal
and bus names on your MSO.
FPGA
USB
LAN
GPIB
ATC2
Parallel
or USB
JTAG
Insert ATC2 core with
Xilinx core inserter
Xilinx JTAG cable
Figure 2. Create a timesaving FPGA measurement system. Insert an ATC2 (Keysight Trace Core)
core into your FPGA design. With the application running on your PC you control which group of
internal signals to measure via JTAG.
1-128
1-128
1-128
1-128
To FPGA pins
1-128
Select
Leverage the work you did in
your design environment
SW application installed
on a PC connected to
6000 or 7000 Series MSOs
PC board
Selection MUX
Make multiple measurements in
seconds
SW application can be
licensed to a particular
PC or particular MSO
Probe outputs
on FPGA pins
Change signal bank
election via JTAG
JTAG
Figure 3. Access up to 64 internal signals for each debug pin. Signal banks all have identical width
(1 to 128 signals wide) determined by the number of device pins you devote for debug. Each pin
provides sequential access to one signal from every input bank.
04 | Keysight | InfiniiVision MSO Dynamic Probe for Xilinx FPGAs (N5406A and DSOX4FPGAX, and DSOX6FPGAX) - Data Sheet
A Quick Tour of the Application
Design step 1: Create the ATC2
core
Use Xilinx Core Inserter or EDK to select
your ATC2 parameters and to create
a debug core that best matches your
development needs. Parameters include
number of pins, number of signal banks,
the type of measurement (state or timing),
and other ATC2 attributes.
Design step 2: Select groups of
signals to probe
Specify banks of internal signals that are
potential candidates for MSO measurements
(using Xilinx Core Inserter or EDK).
Activate FPGA dynamic probe
for Xilinx
The FPGA dynamic probe application allows
you to control the ATC2 core and set up
the MSO for the desired measurements.
This application runs on a PC.
05 | Keysight | InfiniiVision MSO Dynamic Probe for Xilinx FPGAs (N5406A and DSOX4FPGAX, and DSOX6FPGAX) - Data Sheet
A Quick Tour of the Application (Continued)
Connect your MSO to your PC
From FPGA dynamic probe application
software, specify the communication link
between your PC and MSO.
Measurement setup step 1:
Establish a connection between
the PC and the ATC2 core
The FPGA dynamic probe application
establishes a connection between the
PC and a Xilinx cable. It also determines
what devices are on the JTAG scan chain
and lets you pick which one you wish to
communicate with. Core and device names
are user definable.
Measurement setup step 2:
Map FPGA pins
Quickly specify how the FPGA pins (the
signal outputs of ATC2) are connected
to your MSO. Select your probe type and
rapidly provide the information needed for
the MSO to automatically track names of
signals routed through the ATC2 core.
06 | Keysight | InfiniiVision MSO Dynamic Probe for Xilinx FPGAs (N5406A and DSOX4FPGAX, and DSOX6FPGAX) - Data Sheet
A Quick Tour of the Application (Continued)
For ATC2 cores with auto setup enabled,
each pin of the ATC2 core, one at a time,
produces a unique stimulus pattern. The
instrument looks for this unique pattern on
any of its acquisition channels. When the
instrument finds the pattern, it associates
that instrument channel with the ATC2
output pin producing it. It then repeats the
process for each of the remaining output
pins eliminating the need to manually
enter probe layout information.
Measurement setup step 3:
Import signal names
Tired of manually entering bus and
signal names on your MSO? The FPGA
dynamic probe application reads a .cdc
file produced by Xilinx Core Inserter. The
names of signals you measure will now
automatically show on your MSO digital
channel labels.
Setup complete:
Make measurements
Quickly change which signal bank is
routed to the MSO. A single mouse click
tells the ATC2 core to switch to the newly
specified signal bank without any impact
to the timing of your design. To make
measurements throughout your FPGA,
change signal banks as often as needed.
User-definable signal bank names make
it straight forward to select a part of your
design to measure.
07 | Keysight | InfiniiVision MSO Dynamic Probe for Xilinx FPGAs (N5406A and DSOX4FPGAX, and DSOX6FPGAX) - Data Sheet
A Quick Tour of the Application (Continued)
Triggering on valid states
MSOs incorporate logic state triggering
for triggering on specific states. Set up a
valid state trigger by specifying the clock
edge and the desired bus/signal pattern.
Because the ATC2 core outputs both the
clock signal and bus values, triggering on
the combination ensures your state trigger
is valid—even though the digital channels
are sampling asynchronously. Track valid
states by measuring the bus value on each
falling clock edge for image shown.
Automatic bus groupings
InfiniiVision MSOs include up to 2 bus
groupings. Contiguous signal names are
automatically grouped and displayed as
buses. Bus values can be displayed as HEX
or binary values. Additional signals are
shown using independent waveforms.
Correlate internal FPGA activity
with external measurements
View internal FPGA activity and timecorrelate internal FPGA measurements
with external analog and digital events in
the surrounding system. FPGA Dynamic
Probe unlocks the power of the MSO for
system-level debug with FPGAs.
08 | Keysight | InfiniiVision MSO Dynamic Probe for Xilinx FPGAs (N5406A and DSOX4FPGAX, and DSOX6FPGAX) - Data Sheet
Specifications and Characteristics
Supported oscilloscopes
Standalone oscilloscopes
MSO digital channels
Bus groupings
Triggering capabilities
Supported Xilinx FPGA families
Supported Xilinx cables (required)
Supported probing mechanisms
Keysight trace core characteristics
Number of output signals
Signal banks
Modes
FPGA resource consumption
Features with application
Compatible design tools
ISE 1 ChipScope Pro version
14.3 or greater
Vivado
Synthesis
InfiniiVision 6000 and 7000 Series, and 4000 and 6000 X-Series MSOs
16
Up to 2, each with 6 character labels
Determined by MSO, all have state triggering
Zynq-7000/7000Q, Artix-7/7Q, Kintex-7/7Q, Virtex-7/7Q, Virtex-6/6Q, Virtex-5/5Q/5QV, Virtex-4/4Q/4QV,
Spartan-6/6Q, Spartan-3A, 3AN, and 3E
Platform Cable USB, Platform cable II
Soft touch (34-channel and 17-channel), Mictor, Samtec, Flying lead, 6000 and 7000 Series MSOs come
standard with a 40 pin probe cable and flying leads. Cables and probing for Mictor, soft touch, or Samtec
probing must be purchased separately.
User definable: Clock line plus 4 to 128 signals in 1 signal increments
User definable: 1, 2, 4, 8, 16, 32, or 64
State (synchronous) or timing (asynchronous) mode
Approximately 1 slice required per input signal to ATC2 Core Consumes no BUFGs, DCM or Block RAM
resources. See resource calculator at www.keysight.com/find/fpga
Mouse-click bank select, graphical pin mapping, cdc signal name import, auto-pin mapping, and ATC2
"always on" option
Keysight MSO FPGA dynamic probe SW version
2.60 or greater
Designs using Vivado not currently supported
Core Inserter produces ATC2 cores post-synthesis (pre-place and route) making the cores synthesis
independent. ATC2 cores produced by Core Generator are compatible with:
–– Exemplar Leonardo Spectrum
–– Synopsys Design Compiler
–– Synopsys Design Compiler II
–– Synopsys FPGA Express
–– Synplicity Synplify
–– Xilinx XST
Additional information available via the Internet:
www.keysight.com/find/FPGA and www.keysight.com/find/7000-xilinx.
09 | Keysight | InfiniiVision MSO Dynamic Probe for Xilinx FPGAs (N5406A and DSOX4FPGAX, and DSOX6FPGAX) - Data Sheet
Ordering Information
Ordering information
N5405A
–– Option 001
DSOX4FPGAX
DSOX6FPGAX
FPGA dynamic probe for 6000 or 7000 MSOs
Entitlement certificate for perpetual node-locked license locked to oscilloscope
Dynamic probe for 4000 X-Series MSOs
Dynamic probe for 6000 X-Series MSOs
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10 | Keysight | InfiniiVision MSO Dynamic Probe for Xilinx FPGAs (N5406A and DSOX4FPGAX, and DSOX6FPGAX) - Data Sheet
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11 | Keysight | InfiniiVision MSO Dynamic Probe for Xilinx FPGAs (N5406A and DSOX4FPGAX, and DSOX6FPGAX) - Data Sheet
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Published in USA, November 16, 2015
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