STMicroelectronics M48Z2M1Y 5v or 3.3v, 16 mbit (2mb x 8) zeropower sram Datasheet

M48Z2M1Y
M48Z2M1V
5V or 3.3V, 16 Mbit (2Mb x 8) ZEROPOWER® SRAM
FEATURES SUMMARY
■
■
■
■
■
■
■
INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, AND
BATTERIES
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z2M1Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V
– M48Z2M1V: VCC = 3.0 to 3.6V
2.8V ≤ VPFD ≤ 3.0V
BATTERIES ARE INTERNALLY ISOLATED
UNTIL POWER IS APPLIED
PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 2Mb x 8 SRAMs
March 2005
Figure 1. 36-pin, DIP Module
36
1
PLDIP36 (PL)
Module
1/17
M48Z2M1Y, M48Z2M1V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 36-pin, DIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Logic Diagram . .
Signal Names . .
DIP Connections
Block Diagram . .
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...................
...................
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.......
.......
.......
......
......
......
......
.......
.......
.......
.......
......
......
......
......
......
......
......
......
.....4
.....4
.....4
.....5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Address Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . 6
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12.PLDIP36 – 36-pin Plastic DIP Long Module, Package Outline . . . . . . . . . . . . . . . . . . . . 14
Table 11. PLDIP36 – 36-pin Plastic DIP Long Module, Package Mechanical Data . . . . . . . . . . . . 14
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
M48Z2M1Y, M48Z2M1V
Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3/17
M48Z2M1Y, M48Z2M1V
SUMMARY DESCRIPTION
The M48Z2M1Y/V ZEROPOWER® RAM is a nonvolatile 16,777,216-bit, Static RAM organized as
2,097,152 words by 8 bits. The device combines
two internal lithium batteries, CMOS SRAMs and a
control circuit in a plastic 36-pin DIP, long Module.
The ZEROPOWER RAM replaces industry standard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A20
VCC
DQ0-DQ7
21
8
A0-A20
W
DQ0-DQ7
M48Z2M1Y
M48Z2M1V
E
G
Chip Enable
G
Output Enable
W
WRITE Enable
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally
AI02048
Figure 3. DIP Connections
1
36
2
35
34
3
33
4
5
32
6
31
30
7
29
8
M48Z2M1Y
9 M48Z2M1V 28
27
10
26
11
25
12
24
13
14
23
15
22
16
21
17
20
18
19
AI02049
4/17
Data Inputs / Outputs
E
VSS
NC
A20
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Address Inputs
VCC
A19
NC
A15
A17
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
M48Z2M1Y, M48Z2M1V
Figure 4. Block Diagram
VCC
A0-A20
POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
E
2048K x 8
SRAM ARRAY
DQ0-DQ7
E
W
G
INTERNAL
BATTERIES
VSS
AI02050
OPERATION MODES
The M48Z2M1Y/V has its own Power-fail Detect
Circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
operations brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the batteries which sustain data until valid
power returns.
Table 2. Operating Modes
Mode
VCC
Deselect
WRITE
READ
3.0 to 3.6V
or
4.5 to 5.5V
READ
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)(1)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO(1)
X
X
X
High Z
Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 10., page 13 for details.
5/17
M48Z2M1Y, M48Z2M1V
READ Mode
The M48Z2M1Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 16,777,216 locations
in the static storage array. Thus, the unique address specified by the 21 Address Inputs defines
which one of the 2,097,152 bytes of data is to be
accessed. Valid data will be available at the Data
I/O pins within Address Access time (tAVQV) after
the last address input signal is stable, providing
that the E (Chip Enable) and G (Output Enable)
access times are also satisfied. If the E and G ac-
cess times are not met, valid data will be available
after the later of Chip Enable Access time (tELQV)
or Output Enable Access Time (tGLQV). The state
of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time
(tAXQX) but will go indeterminate until the next Address Access.
Figure 5. Address Controlled, READ Mode AC Waveforms
A0-A20
tAVAV
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
AI02051
Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
tAVAV
A0-A20
VALID
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI02052
Note: WRITE Enable (W) = High.
6/17
M48Z2M1Y, M48Z2M1V
Table 3. READ Mode AC Characteristics
M48Z2M1Y
M48Z2M1V
–70
–85
(1)
Symbol
Parameter
Min
tAVAV
READ Cycle Time
Max
70
Min
Unit
Max
85
ns
tAVQV(2)
Address Valid to Output Valid
tAXQX(2)
Address Transition to Output Transition
tEHQZ(3)
Chip Enable High to Output Hi-Z
30
35
ns
tELQV(2)
Chip Enable Low to Output Valid
70
85
ns
tELQX(3)
Chip Enable Low to Output Transition
tGHQZ(3)
Output Enable High to Output Hi-Z
25
35
ns
tGLQV(2)
Output Enable Low to Output Valid
35
45
ns
tGLQX(3)
Output Enable Low to Output Transition
70
5
85
5
5
ns
5
5
ns
ns
5
ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 100pF or 50pF (see Figure 10., page 11).
3. CL = 5pF (see Figure 10., page 11).
WRITE Mode
of another READ or WRITE cycle. Data-in must be
valid tDVEH or tDVWH prior to the end of WRITE and
remain valid for tEHDX or tWHDX afterward. G
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G, a low on W
will disable the outputs tWLQZ after W falls.
The M48Z2M1Y/V is in the WRITE Mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W
or E. A WRITE is terminated by the earlier rising
edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for minimum of tEHAX from E or tWHAX from W prior to the initiation
Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveforms
tAVAV
VALID
A0-A20
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02053
Note: Output Enable (G) = High.
7/17
M48Z2M1Y, M48Z2M1V
Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms
tAVAV
VALID
A0-A20
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI02054
Note: Output Enable (G) = High.
Table 4. WRITE Mode AC Characteristics
Symbol
M48Z2M1Y
M48Z2M1V
–70
–85
Parameter(1)
Min
Max
Min
Unit
Max
tAVAV
WRITE Cycle Time
70
85
ns
tAVEH
Address Valid to Chip Enable High
65
75
ns
tAVEL
Address Valid to Chip Enable Low
0
0
ns
tAVWH
Address Valid to WRITE Enable High
65
75
ns
tAVWL
Address Valid to WRITE Enable Low
0
0
ns
tDVEH
Input Valid to Chip Enable High
30
35
ns
tDVWH
Input Valid to WRITE Enable High
30
35
ns
tEHAX
Chip Enable High to Address Transition
15
15
ns
tEHDX
Chip Enable High to Input Transition
10
15
ns
tELEH
Chip Enable Low to Chip Enable High
55
75
ns
tWHAX
WRITE Enable High to Address Transition
5
5
ns
tWHDX
WRITE Enable High to Input Transition
0
0
ns
tWHQX(2,3)
WRITE Enable High to Output Transition
5
5
ns
tWLQZ(2,3)
WRITE Enable Low to Output Hi-Z
tWLWH
WRITE Enable Pulse Width
25
55
30
65
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF (see Figure 10., page 11).
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
8/17
ns
ns
M48Z2M1Y, M48Z2M1V
Data Retention Mode
With valid VCC applied, the M48Z2M1Y/V operates as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs
become high impedance, and all inputs are treated
as “Don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to completion. If
the memory cycle fails to terminate within the time
tWP, write protection takes place. When VCC drops
below VSO, the control circuit switches power to
the internal energy source which preserves data.
The internal coin cells will maintain data in the
M48Z2M1Y/V after the initial application of VCC for
an accumulated period of at least 10 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the batteries are disconnected, and the power supply is switched to
external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can
resume.
For more information on Battery Storage life refer
to the Application Note AN1012.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
Figure 9. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VCC Noise And Negative Going Transients
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
9.) is recommended in order to provide the needed
filtering.
VSS
AI02169
9/17
M48Z2M1Y, M48Z2M1V
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 5. Absolute Maximum Ratings
Symbol
Value
Unit
TA
Ambient Operating Temperature
0 to 70
°C
TSTG
Storage Temperature (VCC Off)
–40 to 85
°C
TBIAS
Temperature Under Bias
–40 to 85
°C
260
°C
M48Z2M1Y
–0.3 to 7
V
M48Z2M1V
–0.3 to 4.6
V
M48Z2M1Y
–0.3 to 7
V
M48Z2M1V
TSLD
(1)
VIO
Parameter
Lead Solder Temperature for 10 seconds
Input or Output Voltages
VCC
Supply Voltage
–0.3 to 4.6
V
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
No preheat above 150°C, or direct exposure to IR reflow (or IR preheat) allowed, to avoid damaging the Lithium battery.
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
10/17
M48Z2M1Y, M48Z2M1V
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 6. Operating and AC Measurement Conditions
Parameter
M48Z2M1Y
M48Z2M1V
Unit
4.5 to 5.5
3.0 to 3.6
V
0 to 70
0 to 70
°C
Load Capacitance (CL)
100
50
pF
Input Rise and Fall Times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Supply Voltage (VCC)
Ambient Operating Temperature (TA)
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 10. AC Testing Load Circuit
5V
1.9kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
CL includes JIG capacitance
CL = 100pF or 5pF (Y)
50pF or 5pF (V)
AI07816
11/17
M48Z2M1Y, M48Z2M1V
Table 7. Capacitance
Parameter(1,2)
Symbol
CIN
CIO(3)
Min
Max
Unit
Input Capacitance
40
pF
Input / Output Capacitance
40
pF
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. Outputs deselected.
3. At 25°C.
Table 8. DC Characteristics
Sym
Parameter
ILI(2)
Input Leakage Current
ILO(2)
Output Leakage Current
Test Condition(1)
M48Z2M1Y
M48Z2M1V
Unit
Min
Max
Min
Max
0V ≤ VIN ≤ VCC
±4
±4
µA
0V ≤ VOUT ≤ VCC
±4
±4
µA
E = VIL,
Outputs open
140
70
mA
E = VIH
10
2
mA
E ≥ VCC – 0.2V
8
1
mA
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
VIL
Input Low Voltage
–0.3
0.8
–0.3
0.6
V
VIH
Input High Voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
0.4
2.4
2.2
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. Outputs deselected.
12/17
V
M48Z2M1Y, M48Z2M1V
Figure 11. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tDR
tF
tR
tFB
tRB
tER
tWP
E
DON'T CARE
RECOGNIZED
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01031
Table 9. Power Down/Up AC Characteristics
Parameter(1)
Symbol
Min
Max
Unit
120
ms
tER
E Recovery Time
40
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
tFB(3)
VPFD (min) to VSO VCC Fall Time
M48Z2M1Y
10
µs
M48Z2M1V
150
µs
10
µs
tR
tWP
VPFD (min) to VPFD (max) VCC Rise Time
Write Protect Time from VCC = VPFD
M48Z2M1Y
40
150
µs
M48Z2M1V
40
250
µs
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10. Power Down/Up Trip Points DC Characteristics
Symbol
Parameter(1,2)
VPFD
Power-fail Deselect Voltage
VSO
Battery Back-up Switchover Voltage
tDR(3)
Expected Data Retention Time
Min
Typ
Max
Unit
M48Z2M1Y
4.2
4.3
4.5
V
M48Z2M1V
2.8
2.9
3.0
V
M48Z2M1Y
3.0
V
M48Z2M1V
2.45
V
10
YEARS
Note: 1. All voltages referenced to VSS.
2. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
3. At 25°C; VCC = 0V.
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M48Z2M1Y, M48Z2M1V
PACKAGE MECHANICAL INFORMATION
Figure 12. PLDIP36 – 36-pin Plastic DIP Long Module, Package Outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
PMDIP
Note: Drawing is not to scale.
Table 11. PLDIP36 – 36-pin Plastic DIP Long Module, Package Mechanical Data
mm
inches
Symb
Typ
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Min
Max
Typ
Min
Max
A
9.27
9.52
0.3650
0.3748
A1
0.38
B
0.43
0.59
0.0169
0.0232
C
0.20
0.33
0.0079
0.0130
D
52.58
53.34
2.0701
2.1000
E
18.03
18.80
0.7098
0.7402
e1
2.30
2.81
0.0906
0.1106
e3
38.86
47.50
1.5300
1.8701
eA
14.99
16.00
0.5902
0.6299
L
3.05
3.81
0.1201
0.1500
S
4.45
5.33
0.1752
0.2098
N
36
0.0150
36
M48Z2M1Y, M48Z2M1V
PART NUMBERING
Table 12. Ordering Information Scheme
Example:
M48Z
2M1Y
–70
PL
1
Device Type
M48Z
Supply Voltage and Write Protect Voltage
2M1Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
2M1V = VCC = 3.0 to 3.6V; VPFD = 2.8 to 3.0V
Speed
–70 = 70ns (Y)
–85 = 85ns (V)
Package
PL = PLDIP36
Temperature Range
1 = 0 to 70°C
9(1) = Extended Temperature
Shipping Method
blank = Tubes
Note: 1. Contact Sales Offices for availability of Extended Temperature.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
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M48Z2M1Y, M48Z2M1V
REVISION HISTORY
Table 13. Document Revision History
Date
Rev. No.
July 1999
1.0
First Issue
31-Aug-00
2.0
From Preliminary Data to Data Sheet
20-Mar-02
3.0
Reformatted; Temperature information added to tables (Table 7, 8, 3, 4, 9, 10)
29-May-02
3.1
Modified “VCC Noise and Negative Going Transients” text
28-Mar-03
3.2
Remove 5V/5%, add 3V part (Figure 2, 3, 10; Table 5, 6, 8, 2, 3, 4, 9, 10, 12)
02-Jul-03
3.3
Changed characteristic (Table 8)
18-Feb-05
4.0
Reformatted; IR reflow update (Table 5)
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Revision Details
M48Z2M1Y, M48Z2M1V
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