Fairchild FQP8P10 100v p-channel mosfet Datasheet

TM
FQP8P10
100V P-Channel MOSFET
General Description
Features
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as audio amplifier,
high efficiency switching DC/DC converters, and DC motor
control.
•
•
•
•
•
•
•
-8.0A, -100V, RDS(on) = 0.53Ω @VGS = -10 V
Low gate charge ( typical 12 nC)
Low Crss ( typical 30 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
175°C maximum junction temperature rating
D
G
TO-220
G DS
FQP Series
S
Absolute Maximum Ratings
Symbol
VDSS
ID
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
- Continuous (TC = 100°C)
IDM
Drain Current
- Pulsed
(Note 1)
FQP8P10
-100
Units
V
-8.0
A
-5.7
A
-32
A
VGSS
Gate-Source Voltage
± 30
V
EAS
Single Pulsed Avalanche Energy
(Note 2)
150
mJ
IAR
Avalanche Current
(Note 1)
-8.0
A
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
(Note 1)
6.5
-6.0
65
0.43
-55 to +175
mJ
V/ns
W
W/°C
°C
300
°C
dv/dt
PD
TJ, TSTG
TL
(Note 3)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
Typ
--
RθCS
Thermal Resistance, Case-to-Sink
0.5
--
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
--
62.5
°C/W
©2002 Fairchild Semiconductor Corporation
Max
2.31
Units
°C/W
Rev. B, August 2002
FQP8P10
QFET
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
-100
--
--
V
--
-0.1
--
V/°C
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = -250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = -250 µA, Referenced to 25°C
IDSS
IGSSF
IGSSR
VDS = -100 V, VGS = 0 V
--
--
-1
µA
VDS = -80 V, TC = 150°C
--
--
-10
µA
Gate-Body Leakage Current, Forward
VGS = -30 V, VDS = 0 V
--
--
-100
nA
Gate-Body Leakage Current, Reverse
VGS = 30 V, VDS = 0 V
--
--
100
nA
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
-2.0
--
-4.0
V
RDS(on)
Static Drain-Source
On-Resistance
VGS = -10 V, ID = -4.0 A
--
0.41
0.53
Ω
gFS
Forward Transconductance
VDS = -40 V, ID = -4.0 A
--
4.3
--
S
--
360
470
pF
--
120
155
pF
--
30
40
pF
ns
(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = -25 V, VGS = 0 V,
f = 1.0 MHz
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = -50 V, ID = -8.0 A,
RG = 25 Ω
(Note 4, 5)
VDS = -80 V, ID = -8.0 A,
VGS = -10 V
(Note 4, 5)
--
11
30
--
110
230
ns
--
20
50
ns
--
35
80
ns
--
12
15
nC
--
3.0
--
nC
--
6.4
--
nC
A
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
-8.0
ISM
--
--
-32
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = -8.0 A
Drain-Source Diode Forward Voltage
--
--
-4.0
V
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = -8.0 A,
dIF / dt = 100 A/µs
(Note 4)
--
98
--
ns
--
0.35
--
µC
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 3.5mH, IAS = -8.0A, VDD = -25V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ -8.0A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2002 Fairchild Semiconductor Corporation
Rev. B, August 2002
FQP8P10
Electrical Characteristics
FQP8P10
Typical Characteristics
VGS
-15.0 V
-10.0 V
-8.0 V
-7.0 V
-6.5 V
-5.5 V
-5.0 V
Bottom : -4.5 V
Top :
-ID, Drain Current [A]
10
0
10
1
10
-I D , Drain Current [A]
1
-1
10
175℃
0
10
25℃
-55℃
※ Notes :
1. VDS = -40V
2. 250μ s Pulse Test
※ Notes :
1. 250μ s Pulse Test
2. TC = 25℃
-1
-2
10
10
-1
0
10
4
2
1
10
10
6
8
10
-VGS , Gate-Source Voltage [V]
-VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
VGS = - 10V
1.2
0.9
1
10
-I DR , Reverse Drain Current [A]
RDS(on) [ Ω ],
Drain-Source On-Resistance
1.5
VGS = - 20V
0.6
0.3
※ Note : TJ = 25℃
0.0
0
10
175℃
※ Notes :
1. VGS = 0V
2. 250μ s Pulse Test
-1
0
5
10
15
20
25
10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-ID , Drain Current [A]
-VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
900
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
800
Coss
600
※ Notes :
1. VGS = 0 V
2. f = 1 MHz
500
400
Crss
300
200
100
0
-1
10
VDS = -20V
10
VDS = -50V
Ciss
-V GS , Gate-Source Voltage [V]
700
Capacitance [pF]
25℃
VDS = -80V
8
6
4
2
※ Note : ID = -8.0 A
0
0
10
1
10
-VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2002 Fairchild Semiconductor Corporation
0
2
4
6
8
10
12
14
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. B, August 2002
FQP8P10
Typical Characteristics
(Continued)
1.2
3.0
RDS(ON) , (Normalized)
Drain-Source On-Resistance
-BV DSS , (Normalized)
Drain-Source Breakdown Voltage
2.5
1.1
1.0
※ Notes :
1. VGS = 0 V
2. ID = -250 μ A
0.9
0.8
-100
-50
0
50
100
150
2.0
1.5
1.0
※ Notes :
1. VGS = -10 V
2. ID = -4.0 A
0.5
0.0
-100
200
-50
o
0
50
100
150
200
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
10
2
10
Operation in This Area
is Limited by R DS(on)
8
1 ms
1
-I D, Drain Current [A]
-I D, Drain Current [A]
100 µs
10
10 ms
DC
0
10
※ Notes :
6
4
2
o
1. TC = 25 C
o
2. TJ = 175 C
3. Single Pulse
-1
10
0
1
10
0
25
2
10
10
50
100
125
150
175
Figure 10. Maximum Drain Current
vs. Case Temperature
D = 0 .5
0
※ N o te s :
1 . Z θ J C ( t ) = 2 . 3 1 ℃ /W M a x .
2 . D u ty F a c t o r , D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C( t )
0 .2
0 .1
0 .0 5
10
-1
0 .0 2
0 .0 1
JC
( t) , T h e r m a l R e s p o n s e
Figure 9. Maximum Safe Operating Area
10
75
TC, Case Temperature [℃]
-VDS, Drain-Source Voltage [V]
PDM
t1
Z
θ
s in g le p u ls e
10
t2
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ]
Figure 11. Transient Thermal Response Curve
©2002 Fairchild Semiconductor Corporation
Rev. B, August 2002
FQP8P10
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
Qg
200nF
12V
-10V
300nF
VDS
VGS
Qgs
Qgd
DUT
-3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
RL
t on
VDD
VGS
RG
td(on)
VGS
t off
tr
td(off)
tf
10%
DUT
-10V
VDS
90%
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- L IAS2 -------------------2
BVDSS - VDD
L
VDS
tp
ID
RG
VDD
DUT
-10V
tp
©2002 Fairchild Semiconductor Corporation
VDD
Time
VDS (t)
ID (t)
IAS
BVDSS
Rev. B, August 2002
FQP8P10
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
VDS
DUT
_
I SD
L
Driver
RG
VGS
VGS
( Driver )
I SD
( DUT )
Compliment of DUT
(N-Channel)
VDD
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
Body Diode Reverse Current
IRM
di/dt
IFM , Body Diode Forward Current
VDS
( DUT )
VSD
Body Diode
Forward Voltage Drop
VDD
Body Diode Recovery dv/dt
©2002 Fairchild Semiconductor Corporation
Rev. B, August 2002
FQP8P10
Package Dimensions
TO-220
4.50 ±0.20
2.80 ±0.10
(3.00)
+0.10
1.30 –0.05
18.95MAX.
(3.70)
ø3.60 ±0.10
15.90 ±0.20
1.30 ±0.10
(8.70)
(1.46)
9.20 ±0.20
(1.70)
9.90 ±0.20
1.52 ±0.10
0.80 ±0.10
2.54TYP
[2.54 ±0.20]
10.08 ±0.30
(1.00)
13.08 ±0.20
)
(45°
1.27 ±0.10
+0.10
0.50 –0.05
2.40 ±0.20
2.54TYP
[2.54 ±0.20]
10.00 ±0.20
Dimensions in Millimeters
©2002 Fairchild Semiconductor Corporation
Rev. B, August 2002
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Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
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The datasheet is printed for reference information only.
©2002 Fairchild Semiconductor Corporation
Rev. I1