Fairchild FQT3P20 200v p-channel mosfet Datasheet

QFET
TM
FQT3P20
200V P-Channel MOSFET
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters.
Features
•
•
•
•
•
-0.67A, -200V, RDS(on) = 2.7Ω @VGS = 10 V
Low gate charge ( typical 6.0 nC)
Low Crss ( typical 7.5 pF)
Fast switching
Improved dv/dt capability
S
!
D
●
●
G!
▶ ▲
S
G
●
SOT-223
!
FQT Series
Absolute Maximum Ratings
Symbol
VDSS
ID
D
TC = 25°C unless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
- Continuous (TC = 70°C)
IDM
Drain Current
VGSS
Gate-Source Voltage
EAS
Single Pulsed Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
dv/dt
PD
TJ, TSTG
TL
- Pulsed
FQT3P20
-200
Units
V
-0.67
A
-0.53
A
-2.7
A
± 30
V
(Note 2)
150
mJ
(Note 1)
-0.67
A
(Note 1)
0.25
-5.5
2.5
0.02
-55 to +150
mJ
V/ns
W
W/°C
°C
300
°C
(Note 1)
(Note 3)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJA
Parameter
Thermal Resistance, Junction-to-Ambient *
Typ
--
Max
50
Units
°C/W
* When mounted on the minimum pad size recommended (PCB Mount)
©2001 Fairchild Semiconductor Corporation
Rev. A, May 2001
FQT3P20
May 2001
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
-200
--
--
V
--
-0.18
--
V/°C
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = -250 µA
∆BVDSS/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = -250 µA, Referenced to 25°C
IDSS
IGSSF
IGSSR
VDS = -200 V, VGS = 0 V
--
--
-1
µA
VDS = -160 V, TC = 125°C
--
--
-10
µA
Gate-Body Leakage Current, Forward
VGS = -30 V, VDS = 0 V
--
--
-100
nA
Gate-Body Leakage Current, Reverse
VGS = 30 V, VDS = 0 V
--
--
100
nA
-3.0
--
-5.0
V
Zero Gate Voltage Drain Current
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
RDS(on)
Static Drain-Source
On-Resistance
VGS = -10 V, ID = -0.335 A
--
2.06
2.7
Ω
gFS
Forward Transconductance
VDS = -40 V, ID = -0.335 A (Note 4)
--
0.7
--
S
VDS = -25 V, VGS = 0 V,
f = 1.0 MHz
--
190
250
pF
--
45
60
pF
--
7.5
10
pF
--
8.5
25
ns
--
35
80
ns
--
12
35
ns
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = -100 V, ID = -2.8 A,
RG = 25 Ω
(Note 4, 5)
VDS = -160 V, ID = -2.8 A,
VGS = -10 V
(Note 4, 5)
--
25
60
ns
--
6.0
8.0
nC
--
1.7
--
nC
--
2.9
--
nC
A
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
-0.67
ISM
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = -0.67 A
Drain-Source Diode Forward Voltage
--
--
-2.7
A
---
-100
-5.0
--
V
ns
--
0.34
--
µC
VSD
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = -2.8 A,
dIF / dt = 100 A/µs
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 500mH, IAS = -0.67A, VDD = -50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ -2.8A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2001 Fairchild Semiconductor Corporation
Rev. A, May 2001
FQT3P20
Electrical Characteristics
FQT3P20
Typical Characteristics
VGS
-15.0 V
-10.0 V
-8.0 V
-7.0 V
-6.5 V
-6.0 V
Bottom : -5.5 V
Top :
-ID, Drain Current [A]
0
-ID , Drain Current [A]
0
10
-1
10
10
150℃
25℃
-55℃
※ Notes :
1. 250μ s Pulse Test
2. TC = 25℃
※ Notes :
1. VDS = -40V
2. 250μ s Pulse Test
-1
-1
0
10
10
1
10
2
10
4
6
8
10
-VGS , Gate-Source Voltage [V]
-VDS, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
8
-IDR , Reverse Drain Current [A]
RDS(on) [ Ω ],
Drain-Source On-Resistance
10
VGS = - 10V
6
VGS = - 20V
4
2
0
10
25℃
150℃
※ Notes :
1. VGS = 0V
2. 250μ s Pulse Test
※ Note : TJ = 25℃
0
-1
0
2
4
6
8
10
0.2
0.4
0.6
-ID , Drain Current [A]
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
400
VDS = -40V
10
Capacitance [pF]
300
Ciss
Coss
200
※ Notes :
1. VGS = 0 V
2. f = 1 MHz
Crss
100
-V GS , Gate-Source Voltage [V]
VDS = -100V
VDS = -160V
8
6
4
2
※ Note : ID = -2.8 A
0
0
-1
10
0
10
1
10
-VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
©2001 Fairchild Semiconductor Corporation
0
1
2
3
4
5
6
7
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Rev. A, May 2001
(Continued)
2.5
1.2
2.0
1.1
RDS(ON) , (Normalized)
Drain-Source On-Resistance
-BV DSS , (Normalized)
Drain-Source Breakdown Voltage
FQT3P20
Typical Characteristics
1.0
※ Notes :
1. VGS = 0 V
2. ID = -250 μ A
0.9
0.8
-100
-50
0
50
100
150
1.5
1.0
※ Notes :
1. VGS = -10 V
2. ID = -0.335 A
0.5
0.0
-100
200
-50
0
50
100
150
200
o
o
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
0.8
1
10
Operation in This Area
is Limited by R DS(on)
-ID, Drain Current [A]
100 µs
0.6
-ID, Drain Current [A]
1 ms
10 ms
0
10
100 ms
0.4
DC
-1
10
0.2
※ Notes :
-2
10
o
1. TC = 25 C
o
2. TJ = 150 C
3. Single Pulse
0.0
25
-3
10
-1
10
0
1
10
2
10
10
50
75
Figure 9. Maximum Safe Operating Area
125
150
Figure 10. Maximum Drain Current
vs. Case Temperature
D = 0 .5
10
※ N o te s :
1 . Z θ J C( t ) = 5 0 ℃ /W M a x .
2 . D u ty F a c to r , D = t 1 / t 2
3 . T J M - T C = P D M * Z θ J C( t )
0 .2
1
0 .1
0 .0 5
10
0 .0 2
0
PDM
0 .0 1
θ JC
(t), T h e rm a l R e s p o n s e
100
TC, Case Temperature [℃]
-VDS, Drain-Source Voltage [V]
t1
Z
s in g le p u ls e
10
t2
-1
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11. Transient Thermal Response Curve
©2001 Fairchild Semiconductor Corporation
Rev. A, May 2001
FQT3P20
Gate Charge Test Circuit & Waveform
VGS
Same Type
as DUT
50KΩ
12V
Qg
-10V
200nF
300nF
Qgs
VDS
VGS
Qgd
DUT
-3mA
Charge
Resistive Switching Test Circuit & Waveforms
RL
VDS
t on
td(on)
VDD
RG
( 0.5 rated VDS )
Vin
t off
tr
td(off)
tf
10%
DUT
-10V
VDS
90%
Unclamped Inductive Switching Test Circuit & Waveforms
BVDSS
1
EAS = ---- LL IAS2 -------------------2
BVDSS -- VDD
L
VDS
VDD
tp
ID
VDD
RG
Time
VDS (t)
ID (t)
-10V
DUT
IAS
BVDSS
©2001 Fairchild Semiconductor Corporation
Rev. A, May 2001
FQT3P20
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
+
VDS
_
IS
L
Driver
RG
VGS
VGS
( Driver )
Compliment of DUT
(N-Channel)
VDD
• dv/dt controlled by RG
• IS controlled by pulse period
Gate Pulse Width
D = -------------------------Gate Pulse Period
10V
Body Diode Reverse Current
IRM
IS
( DUT )
di/dt
IFM , Body Diode Forward Current
Vf
VDS
( DUT )
Body Diode
Forward Voltage Drop
VDD
Body Diode Recovery dv/dt
©2001 Fairchild Semiconductor Corporation
Rev. A, May 2001
FQT3P20
Package Dimensions
3.00 ±0.10
4.60 ±0.25
6.50 ±0.20
(0.89)
(0.95)
(0.46)
1.60 ±0.20
2.30 TYP
©2001 Fairchild Semiconductor Corporation
0.70 ±0.10
(0.95)
10
+0.10
0.25 –0.05
0°~
7.00 ±0.30
(0.60)
+0.04
0.06 –0.02
(0.60)
3.50 ±0.20
1.75 ±0.20
MAX1.80
0.65 ±0.20
0.08MAX
SOT-223
°
Rev. A, May 2001
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
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Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
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The datasheet is printed for reference information only.
©2001 Fairchild Semiconductor Corporation
Rev. H2