Not Recommended for New Design CAT525 Quad Digitally Programmable Potentiometer (DPP™) with 256 Taps and Microwire Interface FEATURES DESCRIPTION Four 8-bit DPPs configured as programmable voltage sources in DAC-like applications Independent reference inputs Buffered wiper outputs Non-volatile NVRAM memory wiper storage Output voltage range includes both supply rails 4 independently addressable buffered output wipers 1 LSB accuracy, high resolution Serial Microwire-like interface Single supply operation: 2.7V - 5.5V Setting read-back without effecting outputs The CAT525 is a quad 8-bit digitally programmable potentiometer (DPP™) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines and systems capable of self calibration, it is also well suited for applications were equipment requiring periodic adjustment is either difficult to access or located in a hazardous environment. The CAT525 offers four independently programmable DPPs each having its own reference inputs and each capable of rail to rail output swing. The wipers are buffered by rail to rail op amps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DPP’s output. For Ordering Information details, see page 15. APPLICATIONS Automated product calibration Remote control adjustment of equipment Offset, gain and zero adjustments in selfcalibrating and adaptive control systems Tamper-proof calibrations DAC (with memory) substitute Control of the CAT525 is accomplished with a simple 3wire, Microwire-like serial interface. A Chip Select pin allows several CAT525's to share a common serial interface and communications back to the host controller is via a single serial data line thanks to the ¯¯¯¯ CAT525’s Tri-Stated Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of non-volatile NVRAM Memory Erase/ Write cycle. PIN CONFIGURATION The CAT525 is available in the 0°C to 70°C com– mercial and -40°C to 85°C industrial operating temperature ranges and offered in 20-pin plastic DIP and surface mount packages. PDIP 20-Lead (L) SOIC 20-Lead (W) VREFH2 1 20 VREFH3 VREFH1 2 19 VREFH4 VDD 3 18 VOUT1 CLK 4 17 VOUT2 RDY/¯¯¯¯ BSY 5 16 VOUT3 CS 6 15 VOUT4 DI 7 14 VREFL4 DO 8 13 VREFL3 PROG 9 12 VREFL2 GND 10 11 VREFL1 CAT525 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 1 Doc. No. MD-2001 Rev. J CAT525 Not Recommended for New Design FUNCTIONAL DIAGRAM VREFH1 VREFH3 VREFH2 VREFH4 2 RDY/BSY 1 20 19 5 CLK CS DI 4 6 7 PROGRAM CONTROL DATA CONTROLLER PROG 9 WIPER CONTROL REGISTERS AND NVRAM + VOUT1 – + 17 VOUT2 – + 16 – + 24kΩ (ea) H.V. CHARGE PUMP 18 SERIAL DATA OUTPUT REGISTER 15 12 13 VOUT4 – 8 11 VOUT3 DO 14 VREFL2 VREFL4 VREFL1 Doc. No. MD-2001 Rev. J VREFL3 2 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT525 ABSOLUTE MAXIMUM RATINGS Parameters Ratings Supply Voltage* VDD to GND Inputs CLK to GND CS to GND DI to GND ¯¯¯¯ to GND RDY/BSY PROG to GND VREFH to GND VREFL to GND Units -0.5 to +7 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 V V V V V V V V Parameters Outputs D0 to GND VOUT 1– 4 to GND Operating Ambient Temperature Commercial (‘C’ or Blank suffix) Industrial (‘I’ suffix) Junction Temperature Storage Temperature Lead Soldering (10 sec max) Ratings Units -0.5 to VDD +0.5 V -0.5 to VDD +0.5 V 0 to +70 °C -40 to +85 +150 -65 to +150 +300 °C °C °C °C RELIABILITY CHARACTERISTICS Symbol Parameter Test Method Min VZAP(2) ILTH(2)(3) Max Units ESD Susceptibility MIL-STD-883, Test Method 3015 2000 V Latch-Up JEDEC Standard 17 100 mA POWER SUPPLY Symbol Parameter Conditions Min Typ Max Units IDD1 Supply Current (Read) Normal Operating — 400 600 µA IDD2 Supply Current (Write) Programming, VDD = 5V — 1600 2500 µA VDD = 3V — 1000 1600 µA VDD Operating Voltage Range 2.7 — 5.5 V Min Typ Max Units LOGIC INPUTS Symbol Parameter Conditions IIH Input Leakage Current VIN = VDD — — 10 µA IIL Input Leakage Current VIN = 0V — — -10 µA VIH High Level Input Voltage 2 — VDD V VIL Low Level Input Voltage 0 — 0.8 V LOGIC OUTPUTS Symbol Parameter Conditions Min Typ Max Units VOH High Level Output Voltage IOH = -40µA VDD -0.3 — — V VOL Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V IOL = 0.4 mA, VDD = +3V — — 0.4 V Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 3 Doc. No. MD-2001 Rev. J CAT525 Not Recommended for New Design POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol RPOT Parameter Conditions Min Potentiometer Resistance Typ Max 24 RPOT to RPOT Match — Units kΩ ±0.5 Pot Resistance Tolerance ±1 % ±20 % Voltage on VREFH pin 2.7 VDD V Voltage on VREFL pin 0 VDD - 2.7 V Resolution 0.4 % INL Integral Linearity Error 0.5 1 LSB DNL Differential Linearity Error 0.25 0.5 LSB ROUT Buffer Output Resistance 10 Ω IOUT Buffer Output Current 3 mA TCRPOT TC of Pot Resistance 300 ppm/ºC CH/CL Potentiometer Capacitances 8/8 pF AC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units Minimum CS Low Time 150 — — ns tCSS CS Setup Time 100 — — ns tCSH CS Hold Time 0 — — ns tDIS DI Setup Time 50 — — ns 50 — — ns Digital tCSMIN CL = 100pF (1) tDIH DI Hold Time tDO1 Output Delay to 1 — — 150 ns tDO0 Output Delay to 0 — — 150 ns tHZ Output Delay to High-Z — 400 — ns tLZ Output Delay to Low-Z — 400 — ns tBUSY Erase/Write Cycle Time — 4 5 ms PROG Setup Time 150 — — ns tPROG Minimum Pulse Width 700 — — ns tCLKH Minimum CLK High Time 500 — — ns tCLKL Minimum CLK Low Time 300 — — ns Clock Frequency DC — 1 MHz CLOAD = 10 pF, VDD = +5V — 3 10 µs CLOAD = 10 pF, VDD = +3V — 6 10 µs tPS fC Analog tDS DPP Settling Time to 1 LSB Notes: (1) All timing measurements are defined at the point of signal crossing VDD / 2. (2) These parameters are periodically sampled and are not 100% tested. Doc. No. MD-2001 Rev. J 4 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 5 RDY/BSY PROG DO DI CS CLK to to t LZ t DIS t CSS 1 1 t DO1 t DIH 2 2 t PS t CLK H 3 t PROG t CLK L 3 t DO0 4 t BUSY t CSH 4 t HZ t CSMIN 5 5 FROM TIMING TO Rising CS edge to D0 becoming high low impedance (active output) t LZ Rising PROG edge to next falling CLK edge Falling CS edge to D0 becoming high impedance (Tri-State) t BUSY Falling CLK edge after PROG=H to rising RDY/BSY edge t PROG Rising PROG edge to falling PROG edge t PS t HZ Rising CLK edge to D0 = high Rising CLK edge to D0 = low t DO0 t DO1 Rising CLK edge to end of datavalid t DIH Max Min Min (Max) Max (Max) Max Min Min Data valid to first rising CLK edge after CS = high t DIS Min Min Rising CS edge to next rising CLK edge t CSMIN Falling CS edge torising CS edge t CSS Min t CSH Falling CLK edge for last data bit (DI) to falling CS edge Min Min MIN/MAX t CLK L Falling CLK edge to CLKrising edge t CLK H Rising CLK edge tofalling CLK edge PARAM NAME Not Recommended for New Design CAT525 A.C. TIMING DIAGRAM Doc. No. MD-2001 Rev. J CAT525 Not Recommended for New Design PIN DESCRIPTION Pin Name 1 2 3 4 5 6 7 8 VREFH2 VREFH1 VDD CLK ¯¯¯¯ RDY/BSY CS DI DO 9 PROG CDPP/DPP addressing is as follows: Function Maximum DPP 2 output voltage Maximum DPP 1 output voltage Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin A0 A1 VOUT1 0 0 VOUT2 1 0 VOUT3 0 1 VOUT4 1 1 Non-volatile Memory Programming Enable Input 10 GND Power supply ground 11 12 13 14 15 16 17 18 19 20 VREFL1 VREFL2 VREFL3 VREFL4 VOUT4 VOUT3 VOUT2 VOUT1 VREFH4 VREFH3 Minimum DPP 1 output voltage Minimum DPP 2 output voltage Minimum DPP 3 output voltage Minimum DPP 4 output voltage DPP 4 output DPP 3 output DPP 2 output DPP 1 output Maximum DPP 4 output voltage Maximum DPP 3 output voltage “1” as a start bit. The DPP address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. DEVICE OPERATION The CAT525 is a quad 8-bit configured digitally programmable potentiometer (DPP/CDPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each confitured DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT525’s read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP wiper control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in non-volatile memory and switches DO to its high impedance Tri-State mode. DIGITAL INTERFACE The CAT525 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic Doc. No. MD-2001 Rev. J DPP OUTPUT Because CS functions like a reset the CS pin has been desensitized with a 30ns to 90ns filter circuit to 6 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT525 prevent noise spikes from causing unwanted resets and the loss of volatile data. ¯¯¯¯¯ READY/BUSY When saving data to non-volatile memory, the ¯¯¯¯) signals the start and Ready/Busy ouput (RDY/BSY duration of the erase/write cycle. Upon receiving a ¯¯¯¯ command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT525 will ignore any data appearing at DI and no data will be output on DO. CLOCK The CAT525’s clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. ¯¯¯¯ is internally ANDed with a low voltage RDY/BSY detector circuit monitoring VDD. If VDD is below the minimum value required for EEPROM programming, ¯¯¯¯ will remain high following the program RDY/BSY command indicating a failure to record the desired data in non-volatile memory. No clock is necessary upon system power-up. The CAT525’s internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. DATA OUTPUT Data is output serially by the CAT525, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 525s to share a single serial data line and simplifies interfacing multiple 525s to a microprocessor. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. WRITING TO MEMORY Programming the CAT525’s non-volatile memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP wiper control register via the DI pin. Data enters on the clock’s rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. VREF VREF, the voltage applied between pins VREFH & VREFL, sets the configured DPP’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH & VREFL are connected across the power supply rails. When using less than the full supply voltage be mindfull of the limits placed on VREFH and VREFL as specified in the References section of DC Electrical Characteristics. Programming is accomplished by bringing PROG high sometime after the start bit and at least 150 ns prior to the falling edge of the clock cycle immediately Figure 1. Writing to Memory to 1 2 3 4 5 6 A0 A1 D0 D1 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA DI 1 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 PROG RDY/BSY DPP OUTPUT © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice CURRENT DPP VALUE NEW DPP VALUE NEW DPP VALUE NON-VOL ATILE VOLATILE NON-VOL ATILE 7 Doc. No. MD-2001 Rev. J CAT525 Not Recommended for New Design following the D7 bit. Two clock cycles after the D7 bit the DPP control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the non-volatile memory cells. The CAT525’s nonvolatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. control register been different from that stored in nonvolatile memory then a change would occur at the read cycle’s conclusion. TEMPORARILY CHANGE OUTPUT The CAT525 allows temporary changes in DPP’s output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. READING DATA Each time data is transferred into a DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP’s output. This feature allows µPs to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low th before the 13 clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DPP wiper control register. Since this value is the same as that which had been there previously no change in the DPP’s output is noticed. Had the value held in the Figure 3 shows the control and data signals needed to effect a temporary output change. DPP settings may be changed as many times as required and can be made to any of the four DPPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DPPs will return to the output values stored in non-volatile memory. When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DPP control register prior to programming. This is because the CAT525’s internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no PROG signal is received. Figure 3. Temporary Change in Output Figure 2. Reading from Memory to to 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 A0 A1 D0 D1 7 8 9 10 11 12 N N+1 N+2 12 CS CS NEW DPP DATA DI 1 A0 DI A1 1 CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D2 D3 D4 D5 D6 D7 D6 D7 CURRENT DPP DATA D6 DO D7 D0 D1 D2 D3 D4 D5 PROG PROG RDY/BSY RDY/BSY DPP OUTPUT DPP OUTPUT CURRENT DPP VALUE NON-VOL ATILE Doc. No. MD-2001 Rev. J 8 CURRENT DPP VALUE NEW DPP VALUE CURRENT DPP VALUE NON-VOL ATILE VOLATILE NON-VOL ATILE © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT525 APPLICATION CIRCUITS +5V VI RI DPP INPUT RF DPP OUTPUT VDPP = +15V VDD CONTROL & DATA VREFH GND + VDPP CAT525 MSB VOUT – OP 07 -15V VREFL VOUT = LSB VDPP ( RI + RF ) - VI R F RI For R I = RF VOUT = 2VDPP - VI 1111 1111 1000 0000 0111 1111 0000 0001 0000 0000 ANALOG OUTPUT CODE x (VFS - VZERO) + VZERO 255 VFS = 0.99VREF VREF = 5V VZERO = 0.01VREF RI = RF 255 × 0.98VREF + 0.01VREF = 0.990 VREF 255 128 × 0.98VREF + 0.01VREF = 0.502VREF 255 127 × 0.98VREF + 0.01VREF = 0.498 VREF 255 1 × 0.98VREF + 0.01VREF = 0.014 VREF 255 0 × 0.98VREF + 0.01VREF = 0.010 VREF 255 VOUT = +4.90V VOUT = +0.02V VOUT = -0 .02V VOUT = -4.86V VOUT = -4.90V Bipolar DPP Output +5V RI RF +15V VDD CONTROL & DATA VREFH CAT525 GND – VDPP + VOUT OP 07 -15V VREFL R VOUT = (1 + F ) VDPP RI Amplified DPP Output +5V VDD VDD VREFH FINE ADJUST DPP COARSE ADJUST DPP GND +5V VREF 127RC +VREF VREFH 127RC FINE ADJUST DPP RC = +V RC VOFFSET VREFL RC COARSE ADJUST DPP + – GND VREFL R0 = (+VREF) - (VOFFSET+) 1µA (-VREF) + (VOFFSET+) 1µA +V R0 + RC = -VREF VREF 256 x 1µA VOFFSET – -V Fine adjust gives ±1 LSB change in VOFFSET when VOFFSET = VREF/2 Coarse-Fine Offset Control by Averaging DPP Outputs for Single Power Supply Systems © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Coarse-Fine Offset Control by Averaging DPP Outputs for Dual Power Supply Systems 9 Doc. No. MD-2001 Rev. J CAT525 Not Recommended for New Design V+ I > 2mA VREF = 5.000V VDD CONTROL & DATA VREFH LT 1029 CAT525 GND VREFL Digitally Trimmed Voltage Reference 28 ÷ 32V 15kΩ 10µF 10kΩ 1N5231B VDD CONTROL & DATA VREFH 5.1V CAT525 GND + VREFL – MPT3055EL LM 324 OUTPUT 1.00kΩ 4.02kΩ 10µF 35V 0 ÷ 25V @ 1A Digitally Controlled Voltage Reference Doc. No. MD-2001 Rev. J 10 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design +5V VREF CAT525 VIN 1.0µF LM339 + VDD VREFH CAT525 10kΩ +5V WINDOW 1 + VPP CS – – DPP1 +5V + – DI 10kΩ +5V VIN LM339 + WINDOW 2 + VREFH VDD – DO VREF 1.0µF CAT525 VPP – CLK DPP1 – DPP2 + 10kΩ +5V WINDOW 3 DI – – 10kΩ +5V + – WINDOW 4 PROG + – CLK WINDOW 2 + DO 10kΩ +5V DPP3 – DPP4 + + DPP4 – – GND WINDOW 1 CS + DPP3 10kΩ +5V + + DPP2 PROG – +5V VREFL GND 10kΩ VREFL WINDOW 5 10kΩ +5V WINDOW 3 + + – – VREF WINDOW 1 VOUT1 WINDOW 2 VREFH VOUT2 WINDOW 1 WINDOW 3 VOUT1 VOUT2 WINDOW 2 VOUT3 WINDOW 4 VOUT4 VOUT4 VOUT3 WINDOW 3 WINDOW 5 GND GND WINDOW STRUCTURE WINDOW STRUCTURE Staircase Window Comparator © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Overlapping Window Comparator 11 Doc. No. MD-2001 Rev. J CAT525 Not Recommended for New Design +5V 2.2kΩ VDD VREFH 4.7µF LM385-2.5 ISINK = 2 ÷ 255mA +15V + DPP1 1mA steps 2N7000 – +5V CONTROL & DATA 10kΩ 10kΩ CAT525 39Ω 1W 39Ω 1W + DPP2 5µA steps 2N7000 – GND VREFL 5MΩ 5MΩ 3.9kΩ 10kΩ 10kΩ – TIP30 + -15V Current Sink with 4 Decades of Resolution +15V 51kΩ + TIP29 – 10kΩ 10kΩ 5MΩ 39Ω 1W +5V VDD VREFH 5MΩ DPP1 39Ω 1W – CONTROL & DATA CAT525 BS170P + 5MΩ 5MΩ 1mA steps 3.9kΩ DPP2 GND – VREFL BS170P + 5µA steps LM385-2.5 -15V ISOURCE = 2 ÷ 255mA Current Source with 4 Decades of Resolution Doc. No. MD-2001 Rev. J 12 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT525 PACKAGE OUTLINE DRAWINGS PDIP 20-Lead (L)(1)(2) E1 D TOP VIEW E A2 A c A1 e b1 b eB SIDE VIEW SYMBOL MIN A 3.56 NOM END VIEW MAX 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.45 0.55 b1 1.15 1.52 1.77 c 0.21 0.26 0.35 D 24.89 26.16 26.92 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e L 2.54 TYP eB 7.88 L 2.99 10.92 3.30 3.81 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-001. © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 13 Doc. No. MD-2001 Rev. J CAT525 Not Recommended for New Design SOIC 20-Lead 300mils (W)(1)(2) SYMBOL E1 E MIN NOM MAX 2.49 2.64 A 2.36 A1 0.10 A2 2.05 b 0.31 0.41 0.51 c 0.20 0.27 0.33 D 12.60 12.80 13.00 E 10.01 10.30 10.64 E1 7.40 7.50 7.60 e b e PIN#1 IDENTIFICATION 0.30 2.55 1.27 BSC h 0.25 L 0.40 0.75 θ 0° 8° θ1 5° 15° 0.81 1.27 TOP VIEW D h A2 A h θ1 θ θ1 L A1 SIDE VIEW c END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. Doc. No. MD-2001 Rev. J 14 © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice Not Recommended for New Design CAT525 EXAMPLE OF ORDERING INFORMATION(1) Prefix Device # Suffix CAT 525 W Package L: PDIP W: SOIC Optional Company ID I Temperature Range I = Industrial (-40ºC to 85ºC) – T1 Tape & Reel T: Tape & Reel 1: 1000/Reel Product Number 525 ORDERING PART NUMBER CAT525LI CAT525WI Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is Matte-Tin. (3) This device used in the above example is a CAT525WI-T1 (SOIC, Industrial Temperature, Tape & Reel, 1000). © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice 15 Doc. No. MD-2001 Rev. J CAT525 Not Recommended for New Design REVISION HISTORY Date 16-Mar-04 Revision D Description Updated Potentiometer Characteristics 12-Jul-04 E Updated Functional Diagram Updated Potentiometer Characteristics 27-Jul-07 F 31-Oct-07 G 6-Dec-07 H 15-Jul-08 I Add “Not Recommended for New Design” to the top of all pages 25-Nov-08 J Change logo and fine print to ON Semiconductor Added Package Outline Drawings Updated Example of Ordering Information Added MD- to document number Updated Package Outline Drawings Updated Example of Ordering Information Update document title Update Logic Output table Update A.C. Timing Diagram Update Writing to Memory ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] Doc. No. MD-2001 Rev. J N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 16 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative © 2008 SCILLC. All rights reserved. Characteristics subject to change without notice