MOTOROLA Order this document by MCM64PD32/D SEMICONDUCTOR TECHNICAL DATA Advance Information 256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium MCM64PD32 MCM64PD64 160–LEAD CARD EDGE CASE TBD, TOP VIEW 1 The MCM64PD32 (256K) and MCM64PD64 (512K) are designed to provide a burstable, high performance, L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton II chip set. The MCM64PD32 is configured as 32K x 64 bits and the MCM64PD64 is configured as 64K x 64 bits. Both are packaged in a 160 pin card edge memory module. Each module uses Motorola’s 3.3 V 32K x 32 BurstRAMs and two Motorola 3.3 V 32K x 8 FSRAM for the tag RAM. Bursts can be initiated with either address status processor (ADSP) or cache address status (CADS). Subsequent burst addresses are generated internal to the BurstRAM by the cache burst advance (CADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLK0) input. Eight write enables are provided for byte write control. PD0 – PD3 map into the Triton II chip set for auto–configuration of the cache control. • • • • • • • • • • • • • • • • 42 43 Pentium–Style Burst Counter on Chip Pipelined Data Out 160 Pin Card Edge Module Address Pipeline Supported by ADSP Disabled with Ex All Cache Data and Tag I/Os are TTL Compatible Three State Outputs Byte Write Capability Fast Module Clock Rate: 66 MHz Fast SRAM Access Times:15 ns for Tag RAM 8 ns for Data RAMs One–cycle Deselect Data RAMs Decoupling Capacitors for Each Fast Static RAM High Quality Multi–Layer FR4 PWB with Separate Power and Ground Planes Single 3.3 V +10%, – 5% Power Supply Burndy Connector, Part Number: CELP2X80SC3Z48 Intel COAST 3.0 Option III Compliant Burst Order Select (BOSEL) Option 80 BurstRAM is a trademark of Motorola. Pentium is a trademark of Intel Corp. This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice. 6/14/96 Motorola, Inc. 1996 MOTOROLA FAST SRAM MCM64PD32•MCM64PD64 1 MCM64PD32 BLOCK DIAGRAM VDD3 8.2 kΩ 8.2 kΩ 32K x 8 TIO0 – TIO7 TWE A3 – A17 TIO8 TIO9 TIO10 DQ0 – DQ7 W 13 A0 – A12 8.2 kΩ A13 A14 ECS2 ECS1 E G 32K x 32 15 SA0 – SA14 ADSP ADSC ADV K G ADSP CADS CADV CLK0 CG SW SGW BWE GWE SE1 SE2 SE3 LBO 4.7 kΩ CCS VDD VDD BOSEL ZZ SBa – SBd CWE0 – CWE3 DQ0 – DQ31 DQ0 – DQ31 32K x 32 15 SA0 – SA14 ADSP ADSC ADV K G SW SGW CWE4 – CWE7 SE1 SE2 SE3 LBO ZZ SBa – SBd DQ0 – DQ31 MCM64PD32•MCM64PD64 2 DQ32 – DQ63 MOTOROLA FAST SRAM MCM64PD64 BLOCK DIAGRAM VDD3 TIO0 – TIO7 8.2 kΩ 8.2 kΩ 32K x 8 DQ0 – DQ7 TWE 13 A3 – A17 A18 TIO8 TIO9 TIO10 W A0 – A12 8.2 kΩ A13 A14 15 E G CCS 32K x 32 ADSP CADS CADV CLK0 CG BWE GWE CWE0 – CWE3 SA0 – SA14 ADSP ADSC ADV K G SW SGW 32K x 32 SE1 SE2 SE3 LBO ZZ SBa – SBd 15 SA0 – SA14 ADSP ADSC ADV K G SW SGW SE1 SE2 SE3 VDD LBO ZZ SBa – SBd DQ0 – DQ31 DQ0 – DQ31 DQ0 – DQ31 4.7 kΩ CLK1 VDD BOSEL 32K x 32 SA0 – SA14 ADSP ADSC ADV K G SW SGW CWE4 – CWE7 MOTOROLA FAST SRAM 32K x 32 SE1 SE2 SE3 LBO ZZ SA0 – SA14 ADSP ADSC ADV K G SW SE1 SE2 SE3 VDD LBO ZZ SGW SBa – SBd DQ0 – DQ31 SBa – SBd DQ0 – DQ31 DQ32 – DQ63 MCM64PD32•MCM64PD64 3 PIN ASSIGNMENT 160–LEAD CARD EDGE MODULE (DIMM) Pin Name Pin Name Pin Name Pin Name Pin Name 1 VSS TIO0 33 PD1 65 DQ22 97 NC 129 DQ47 2 34 PD3 66 DQ20 98 NC 130 DQ45 3 TIO2 35 DQ18 99 DQ43 36 68 100 132 5 TIO4 37 69 101 A4 133 VDD5 DQ41 6 TIO8 38 VSS DQ62 VDD3 DQ16 VSS RSVD 131 TIO6 VSS CLK1 67 4 70 DQ14 102 A6 134 DQ39 7 VDD3 TWE 39 DQ12 103 A8 135 DQ37 40 VDD3 DQ60 71 8 72 104 A10 136 9 CADS 41 DQ58 73 VSS DQ10 105 137 10 42 DQ56 74 DQ8 106 138 DQ33 11 VSS CWE4 VDD5 A17 VSS DQ35 43 DQ6 107 DQ31 44 76 108 140 13 CWE0 45 DQ52 77 VDD3 DQ4 VSS A9 139 CWE6 VSS DQ54 75 12 109 A14 141 VDD5 DQ29 14 CWE2 46 DQ50 78 DQ2 110 A15 142 DQ27 15 47 DQ48 79 DQ0 111 RSVD 143 DQ25 16 VDD3 CCS 48 PD0 144 49 81 VSS VSS 112 GWE VSS DQ46 80 17 113 PD2 145 VSS DQ23 18 BWE 50 DQ44 82 TIO1 114 BOSEL 146 DQ21 19 51 DQ42 83 TIO7 115 DQ19 52 84 TIO5 116 148 21 A7 53 VDD3 DQ40 VSS CLK0 147 20 VSS A3 85 TIO3 117 149 VDD5 DQ17 22 A5 54 DQ38 86 TIO9 118 VSS DQ63 150 DQ15 23 A11 55 DQ36 87 119 DQ13 A16 56 88 120 152 25 VDD3 A18 57 VSS DQ34 VDD5 DQ61 151 24 VDD5 TIO10 89 CADV 121 DQ59 153 VSS DQ11 58 DQ32 90 DQ57 154 DQ9 59 DQ30 91 VSS CG 122 123 DQ7 60 92 CWE5 124 156 29 A13 61 VDD3 DQ28 VSS DQ55 155 28 VSS A12 93 CWE7 125 DQ53 157 VDD5 DQ5 30 ADSP 62 DQ26 94 CWE1 126 DQ51 158 DQ3 31 ECS1 63 DQ24 95 127 DQ49 159 DQ1 32 ECS2 64 VSS 96 VDD5 CWE3 128 VSS 160 VSS 26 27 TOP VIEW – CASE TBD 81 1 122 42 123 43 160 80 MCM64PD32•MCM64PD64 4 PRESENCE DETECT TABLE Cache Size and Functionality PD0 PD1 PD2 PD3 256K Pipe Burst NC NC VSS NC 512K Pipe Burst VSS VSS NC VSS MOTOROLA FAST SRAM PIN DESCRIPTIONS 160–Lead Card Edge Pin Locations Symbol Type Description 20, 21, 22, 23, 24, 26, 28, 29, 101, 102, 103, 104, 106, 108, 109, 110 A3 – A18 Input Address Inputs: These inputs are registered into data RAMs and must meet setup and hold times. The tag RAM addresses are not registered. 30 ADSP Input Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (Exception–chip deselect dGs not occur when ADSP is asserted and CCS is high. 114 BOSEL Input Burst Order Select: NC for interleaved burst counter. Tie to ground for linear burst counter. 18 BWE Input Byte Write Enable: To be used in future modules. 9 CADS Input Cache Address Status: Initiates READ, WRITE, or chip deselect cycle. 89 CADV Input Cache Burst Advance: Increments address count in accordance with interleaved count style. 16 CCS Input Chip Select: Active low chip enable for data RAMs. 91 CG Input Cache Output Enable: Active low asynchronous input. Low – enables output buffers (DQ pins) High – DQx pins are high impedance. 36, 116 CLK0, CLK1 Input Clock: This signal registers the address, data in, and all control signals except CG. 11, 12, 13, 14, 92, 93, 94, 96 CWE0 – CWE7 Input Cache Data Byte Write Enable: Active low write signal for data RAMs. 38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51, 53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66, 67, 69, 70, 71, 73, 74, 75, 77, 78, 79, 118, 120, 121, 122, 124, 125, 126, 127, 129, 130, 131, 133, 134, 135, 137, 138, 139, 141, 142, 143, 145, 146, 147, 149, 150, 151, 153, 154, 155, 157, 158, 159 DQ0 – DQ63 I/O 31, 32 ECS1, ECS2 Input Expansion Chip Select 17 GWE Input Global Write Enable: To be used in future modules. 33, 34, 112, 113 PD0 – PD3 — Presence Detect: See Presence Detect Table 2, 3, 4, 5, 6, 82, 83, 84, 85, 86, 88 TIO0 – TIO10 I/O Tag RAM I/O: Drives data out during tag compare cycles. Stores data to tag RAM during tag WRITE cycles. 8 TWE Input 7, 15, 25, 39, 52, 60, 68, 76 VDD3 Supply Power Supply: 3.3 V + 10%, – 5%. 87, 95, 105, 119, 132, 140, 148, 156 VDD5 Supply Power Supply: 5.0 V ± 5%. 1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72, 80, 81, 90, 99, 107, 115, 117, 123, 128, 136, 144, 152, 160 VSS Supply Ground. 100, 111 RSVD — No Connection: Reserved for future use. 97, 98 NC — No Connection: There is no connection to the module. MOTOROLA FAST SRAM Synchronous Data I/O: Drives data out of data RAMs during READ cycles. Stores data to data RAMs during WRITE cycles. Tag Write Enable: Active low write signal for tag RAMs. MCM64PD32•MCM64PD64 5 SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3) CCS ADSP CADS CADV CWEx CLK0 Address Used Operation H X L X X L–H N/A Deselected L L X X X L–H External Address Read Cycle, Begin Burst L H L X L L–H External Address Write Cycle, Begin Burst L H L X H L–H External Address Read Cycle, Begin Burst X H H L L L–H Next Address Write Cycle, Continue Burst X H H L H L–H Next Address Read Cycle, Continue Burst X H H H L L–H Current Address Write Cycle, Suspend Burst X H H H H L–H Current Address Read Cycle, Suspend Burst H X H L L L–H Next Address Write Cycle, Continue Burst H X H L H L–H Next Address Read Cycle, Continue Burst H X H H L L–H Current Address Write Cycle, Suspend Burst H X H H H L–H Current Address Read Cycle, Suspend Burst NOTES: 1. X means Don’t Care. 2. All inputs except CG must meet setup and hold times for the low–to–high transition of clock (CLK0/1). 3. Wait states are inserted by suspending burst. ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2) Operation CG I/O Status Read L Data Out Read H High–Z Write X High–Z — Data In Deselected X High–Z NOTES: 1. X means Don’t Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time. DC ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Symbol Value Unit VDD3 – 0.5 to + 4.6 V Voltage Relative to VSS Vin, Vout VSS – 0.5 to VDD3 + 0.5 V Output Current (per I/O) Iout ± 20 mA Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to +70 °C Rating Power Supply Voltage Tstg – 65 to + 150 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Storage Temperature MCM64PD32•MCM64PD64 6 This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TJ = 20 to + 110°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V) Symbol Min Supply Voltage (Operating Voltage Range) VDD Input High Voltage VIH Input Low Voltage VIL Parameter Max Unit Notes 3.135 3.6 V 1 2.0 VDD + 0.3 V 2 – 0.5 0.8 V 3 Notes NOTES: 1. JEDEC specification 8–1A specifies ± 0.3 V tolerance for VDD. 2. VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. 3. VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA. DC CHARACTERISTICS Parameter Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VDD3) Ilkg(I) — ± 1.0 µA Output Leakage Current (CG = VIH) Ilkg(O) — ± 1.0 µA VOL — 0.4 V 1 VOH 2.4 — V 1 TTL Output Low Voltage (IOL = + 8.0 mA) TTL Output High Voltage (IOH = – 4.0 mA) NOTES: 1. Champing diodes exist to VSS and VDD. POWER SUPPLY CURRENTS Parameter Symbol Max Unit AC Supply Current (CG = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min) MCM64PD32 MCM64PD64 IDDA 720 880 mA AC Standby Current (CG = VIH, CCS = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min) MCM64PD32 MCM64PD64 ISB1 200 490 mA Symbol Max Unit CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TJ = 20 to 110°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance MCM64PD32 MCM64PD64 Cin 22 32 pF Input/Output Capacitance (DQ0 – DQ63) MCM64PD32 MCM64PD64 CI/O 8 16 pF MOTOROLA FAST SRAM MCM64PD32•MCM64PD64 7 DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5% TJ = 20 to + 110°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 3 Unless Otherwise Noted OUTPUT LOAD OUTPUT BUFFER TEST POINT (UNLOADED OUTPUT) UNLOADED RISE AND FALL TIME MEASUREMENT INPUT WAVEFORM 2.4 OUTPUT WAVEFORM 2.4 0.4 tr 0.4 tf NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.4 V to 2.4 V unloaded. 3. Fall time is measured from 2.4 V to 0.4 V unloaded. Figure 1. Unloaded Rise and Fall Time Characterization MCM64PD32•MCM64PD64 8 MOTOROLA FAST SRAM DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3) MCM64PD32–66 Parameter Symbol Min Max Unit Notes Cycle Time tKHKH 15 — ns Clock Access Time tKHQV — 8 ns 5 Output Enable to Output Valid tGLQV — 6 ns 5 Clock High to Output Active tKHQX1 0 — ns 5, 7 Clock High to Output Change tKHQX2 2 — ns 5, 7 Output Enable to Output Active tGLQX 0 — ns 5, 7 Output Disable to Q High–Z tGHQZ — 8 ns 6, 7 Clock High to Q High–Z tKHQZ 2 8 ns 6, 7 Clock High Pulse Width tKHKL 5 — ns Clock Low Pulse Width tKLKH 5 — ns Setup Times: Address Address Status Data In Write Address Advance Chip Enable tAVKH tADSVKH tDVKH tWVKH tADVVKH tEVKH 2.5 — ns 4 Hold Times: Address Address Status Data In Write Address Advance Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHEX 0.5 — ns 4 NOTES: 1. Write applies to all SBx, SW, and SGW signals when the chip is selected and ADSP high. 2. Chip Enable applies to all SE1, SE2 and SE3 signals whenever ADSP or ADSC is asserted. 3. All read and write cycle timings are referenced from K or G. 4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle. 5. Tested per AC Test Load. 6. Measured at ± 200 mV from steady state. Tested per High–Z Test Load. 7. This parameter is sampled and is not 100% tested. MOTOROLA FAST SRAM MCM64PD32•MCM64PD64 9 3.6 PULL–UP I (mA) Min I (mA) Max – 0.5 – 40 – 120 0 – 40 – 120 1.4 – 40 – 120 1.65 – 37 – 104 2 –28 – 81 3.135 0 – 20 3.6 0 0 3.135 2.8 VOLTAGE (V) VOLTAGE (V) TEST POINT DC DRIVE POINT 1.65 1.4 AC DRIVE POINT 0 – 80 0 –5 – 40 NOTES: CURRENT (mA) 1. Driver impedance @ 1.65 V = 15.9 to 44.6 Ω. 2. Meets the temperature and voltage range specified in DC Characteristics tables. 3. This drawing is not to scale. Comparisons should be made to the table in Figure 2a. –120 (a) Pull–Up PULL–DOWN I (mA) Min – 0.5 – 34 VDD I (mA) Max AC DRIVE POINT – 126 0 0 0 0.5 17 47 1 35 90 1.65 45 114 1.8 46 120 3.6 46 120 4 46 120 VOLTAGE (V) VOLTAGE (V) 1.8 1.65 DC DRIVE POINT TEST POINT 0.3 0 0 5 46 80 CURRENT (mA) NOTES: 1. Driver impedance @ 1.65 V = 15.9 to 44.6 Ω. 2. Meets the temperature and voltage range specified in DC Characteristics tables. 3. This drawing is not to scale. Comparisons should be made to the table in Figure 2b. 120 (b) Pull–Down Figure 2. Output Buffer Characteristics MCM64PD32•MCM64PD64 10 MOTOROLA FAST SRAM MOTOROLA FAST SRAM MCM64PD32•MCM64PD64 11 DESELECTED tKHQZ Q(n–1) B SINGLE READ tKHQX1 A Q(A) Q(B) tKHQX2 t KHQV tKHKL Note: W low = GWE low and/or BWE and CWEx low. DQx CG W ESC1 CCS CADV CADS ADSP Ax (ADDRESS) CLK0, CLK1 tKHKH Q(B+2) BURST READ Q(B+1) Q(B) tGHQZ Q(B+3) BURST WRAPS AROUND tKLKH C ADSP, Ax ESC1 IGNORED D(C) DATA RAMs READ/WRITE CYCLES D(C+2) BURST WRITE D(C+1) D(C+3) tGLQX D SINGLE READ Q(D) t KHQV TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 0.3 V, TJ = 20 to + 110°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . Figure 3a Unless Otherwise Noted TAG RAM READ CYCLE (See Note 1 and 5) – 15 Symbol Min Max Unit Notes Read Cycle Time Parameter tAVAV 15 — ns 2 Address Access Time tAVQV — 15 ns Output Hold from Address Change tAXQX 4 — ns 3, 4 NOTES: 1. CWE is high for read cycle. 2. All timings are referenced from the last valid address to the first address transition. 3. Transition is measured ±500 mV from steady–state voltage with load of Figure 3b. 4. This parameter is sampled and not 100% tested. 5. Device is continuously selected (CG = VIL). TAG RAM READ CYCLE (See Note 5) tAVAV Ax (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV TIMING LIMITS +3.3 V 317 Ω Z0 = 50 Ω OUTPUT OUTPUT 50 Ω 351 Ω 5 pF VL = 1.5 V (a) (b) The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 3. AC Test Loads MCM64PD32•MCM64PD64 12 MOTOROLA FAST SRAM TAG RAM WRITE CYCLE (See Notes 1 and 2) – 15 Parameter Write Cycle Time Symbol Min Max Unit Notes tAVAV 15 — ns 3 Address Setup Time tAVWL 0 — ns Address Valid to End of Write tAVWH 12 — ns Data Valid to End of Write tDVWH 7 — ns Data Hold Time tWHDX 0 — ns Write Low to Output High–Z tWLQZ 0 7 ns 5,6,7 Write High to Output Active tWHQX 4 — ns 5,6,7 Write Recovery Time tWHAX 0 — ns NOTES: 1. A write occurs when CWE is low. 2. If CG goes low coincident with or after CWE goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first address transition. 4. If CG ≥ VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured ±500 mV from steady–state voltage with load of Figure 3B. 7. This parameter is sampled and not 100% tested. TAG RAM WRITE CYCLE (See Notes 1 and 2) tAVAV AX (ADDRESS) tAVWH tWHAX tWLWH TWE tAVWL tDVWH D (DATA IN) DATA VALID tWLQZ Q (DATA OUT) MOTOROLA FAST SRAM tWHDX HIGH Z tWHQX HIGH Z MCM64PD32•MCM64PD64 13 ORDERING INFORMATION (Order by Full Part Number) MCM 64PD32 64PD64 XX XX Motorola Memory Prefix Speed (66 = 66 MHz) Part Number Package (SG = Gold Pad SIMM) Full Part Number — MCM64PD32SG66 MCM64PD32•MCM64PD64 14 MCM64PD64SG66 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 160–LEAD CARD EDGE MODULE CASE TBD A C NOTE 4 E COMPONENT AREA B MIN .285 inches, MAX .305 inches ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉ 80 –Y– VIEW AA 43 2X 42 V P NOTE 4 1 F AC –X– L M AB NOTE 5 J –T– FRONT VIEW NOTE 6 0.012 (0.3) M SIDE VIEW 160X R R D 0.004 (0.1) ÉÉÉ É É É ÉÉ ÉÉÉ É W 160X 156X L T Y X S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS C AND V DEFINE A DOUBLE–SIDED MODULE. 5. DIMENSION AB DEFINES OPTIONAL SINGLE–SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. H 160X K G (N) VIEW AA ÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉ ÉÉ 160 123 122 81 COMPONENT AREA BACK VIEW DIM A B C D E F G H J K L M N P R V W AB AC INCHES MIN MAX 4.330 4.350 1.120 1.140 ––– 0.454 0.033 0.037 2.265 2.275 0.075 BSC 0.050 BSC ––– 0.030 0.055 0.069 0.210 ––– 1.955 1.965 2.155 2.165 0.110 REF 0.300 ––– 0.492 0.512 0.300 ––– 0.040 0.060 ––– 0.262 0.072 0.076 MILLIMETERS MIN MAX 109.98 110.49 28.45 28.96 ––– 11.53 0.84 0.94 57.53 57.79 1.91 BSC 1.27 BSC ––– 0.51 1.40 1.75 5.33 ––– 49.66 49.91 54.74 54.99 2.79 REF 7.62 ––– 7.24 7.75 7.62 ––– 1.02 1.52 ––– 6.66 1.83 1.93 NOTE: Case Outline number to be determined. MOTOROLA FAST SRAM MCM64PD32•MCM64PD64 15 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MCM64PD32•MCM64PD64 16 ◊ *MCM64PD32/D* MOTOROLAMCM64PD32/D FAST SRAM