WEDC EDI8F8512C25M6C 512kx8 static ram cmos, module Datasheet

EDI8F8512C
White Electronic Designs
512Kx8 STATIC RAM CMOS, MODULE
FEATURES
DESCRIPTION
 512Kx8 bit CMOS Static
The EDI8F8512C is a 4096K bit CMOS Static RAM based on four
128Kx8 or 256Kx4 (high speed) Static RAMs mounted on a multilayered epoxy laminate (FR4) substrate.
 Random Access Memory
• Access Times 20 through 100ns
Functional equivalence to the monolithic four megabit Static RAM
is achieved by utilization of an on-board decoder that interprets the
higher order address(es) to select one of the128Kx8 or 256Kx4 Static
RAMs.
• Data Retention Function (EDI8F8512LP)
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
The 32 pin DIP pinout adheres to the JEDEC standard for the four
megabit device, to ensure compatibility with future monolithics.
 High Density Packaging
• 36 Pin SIP, No. 63
A low power version with data retention (EDI8F8512LP) is also
available.
• 32 Pin DIP, JEDEC Pinout, No. 91 (55-100ns)
• 32 Pin DIP, JEDEC Pinout, No. 183 (20-35ns)
All inputs and outputs are TTL compatible and operate from a single
5V supply. Fully asynchronous, the EDI8F8512C requires no clocks
or refreshing for operation.
 Single +5V (±10%) Supply Operation
*This product is subject to change without notice.
FIG. 1 PIN CONFIGURATIONS
NC
VCC
W#
DQ2
DQ3
DQ0
A1
A2
A3
A4
VSS
DQ5
A10
A11
A5
A13
A14
NC
E#
A15
A16
A12
A18
A6
DQ1
VSS
A0
A7
A8
A9
DQ7
DQ4
DQ6
A17
VCC
G#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN NAMES
VCC
A15
A17
W#
A13
A8
A9
A11
G#
A10
E#
DQ7
DQ6
DQ5
DQ4
DQ3
A0-A18
E#
W#
G#
DQ0-DQ7
VCC
VSS
NC
Address Inputs
Chip Enable
Write Enable
Output Enable
Common Data Input/Output
Power (+5V±10%)
Ground
No Connection
8F8512C Pin Config
8F8512C Pin Config.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
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EDI8F8512C
White Electronic Designs
FIG. 2 BLOCK DIAGRAMS
A0-16
A0-17
128K x 8
W#
W#
G#
256K x 4
DQ0-3
256K x 4
DQ4-7
G#
128K x 8
DQ0-7
128K x 8
256K x 4
128K x 8
256K x 4
55-100ns
A17-A18
E#
20-35ns
A18
DECODER
E#
8F8512C Blk Dia
DECODER
8F8512C Blk Dia2
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July 2002
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EDI8F8512C
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RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Industrial
Storage Temperature
Power Dissipation
Output Current
-0.5V to 7.0V
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
4 Watt
20 mA
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
VCC
4.5
5.0
5.5
V
Supply Voltage
VSS
0
0
0
V
Input High Voltage
VIH
2.2
–
6.0
V
Input Low Voltage
VIL
-0.3
–
0.8
V
AC TEST CONDITIONS
*Stress greater than those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load 20-35ns
70-100ns
VSS to 3.0V
5ns
1.5V
1TTL = 30pF
1TTL, CL = 100pF
(Note: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF)
DC ELECTRICAL CHARACTERISTICS
Parameter
Sym
Conditions
Min
Typ*
Max
Units
≤35
≤55
20-25
35
55-100
340
70
570
390
130
mA
Operating Power Supply Current
ICC1
W#, E# = VIL, II/O = 0mA, Min Cycle
Standby (TTL) Power
Supply Current
ICC2
E# ≥ VIH, VIN ≤ VIL
VIN ≥ VIH
DIP
SIP
–
–
50
–
10
–
85
–
85
–
55
65
mA
Full Standby Power
Supply Current (CMOS)
ICC3
E# ≥ VCC-0.2V
VIN ≥ VCC-0.2V or
VIN ≤ 0.2V
C
LP
–
–
5
–
2
40
40
–
40
–
5
400
mA
µA
Input Leakage Current
ILI
VIN = 0V to VCC
–
–
–
–
±10
±10
±10
µA
Output Leakage Current
ILO
V I/O = 0V to VCC
–
–
–
–
±10
±10
±10
µA
Output High Voltage
VOH
IOH = -1.0mA (≥70), or -4.0 (≤35)
2.4
–
–
–
–
–
–
V
Output Low Voltage
VOL
IOL = 2.1mA (≥70), or 8.0mA (≤35)
–
–
–
–
0.4
0.4
0.4
V
*Typical: TA = 25°C, VCC = 5.0V
CAPACITANCE
TRUTH TABLE
(f=1.0MHz, VIN=VCC or VSS)
G#
E#
W#
Mode
Output
Power
Parameter
X
H
X
Standby
HIGH Z
ICC2/ICC3
Address Lines
H
Output
Deselect
HIGH Z
ICC1
Read
Write
DOUT
DIN
H
L
X
L
L
L
H
L
Data Lines
ICC1
ICC1
Sym
Max
Unit
CI
30
pF
CD/Q
43
pF
Chip Enable Line
CC
10
pF
Write and Output Enable Lines
CW
32
pF
These parameters are sampled, not 100% tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
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EDI8F8512C
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AC CHARACTERISTICS READ CYCLE
Symbol
JEDEC
Alt.
tAVAV
tRC
Parameter
Read Cycle Time
Min.
20
20ns
Max.
Min.
25
25ns
Max.
Min.
35
35ns
Max.
Units
ns
Address Access Time
tAVQV
tAA
20
25
35
ns
Chip Enable Access Time
tELQV
tACS
20
25
35
ns
Chip Enable to Output in Low Z (1)
tELQX
tCLZ
Chip Disable to Output in High Z (1)
tEHQZ
tCHZ
Output Hold from Address Change
tAVQX
tOH
Output Enable to Output Valid
tGLQV
tOE
Output Enable to Output in Low Z (1)
tGLQX
tOLZ
Output Disable to Output in High Z (1)
tGHQZ
tOHZ
3
3
10
3
12
3
3
13
3
15
0
0
10
ns
ns
20
0
8
ns
15
ns
ns
12
ns
Note: Parameter guaranteed, but not tested.
FIG. 3 READ CYCLE 1 - W# HIGH, G#, E# LOW
tAVAV
A
ADDRESS 1
ADDRESS 2
tAVQV
tAVQX
Q
DATA 1
DATA 2
8F8512C Rd Cyc1
FIG. 4 READ CYCLE 2 - W# HIGH
tAVAV
A
tAVQV
E#
tELQV
tEHQZ
tELQX
G#
tGLQV
tGHQZ
tGLQX
Q
8F8512C Rd Cyc2
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July 2002
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EDI8F8512C
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AC CHARACTERISTICS READ CYCLE
Symbol
JEDEC
Alt.
tAVAV
tRC
Parameter
Read Cycle Time
55ns
Min
Max
55
70ns
Min
Max
70
85ns
Min
Max
85
100ns
Min
Max
100
Units
ns
Address Access Time
tAVQV
tAA
55
70
85
100
ns
Chip Enable Access Time
tELQV
tACS
55
70
85
100
ns
Chip Enable to Output in Low Z (1)
tELQX
tCLZ
Chip Disable to Output in High Z (1)
tEHQZ
tCHZ
Output Hold from Address Change
tAVQX
tOH
Output Enable to Output Valid
tGLQV
tOE
Output Enable to Output in Low Z (1)
tGLQX
tOLZ
Output Disable to Output in High Z (1)
tGHQZ
tOHZ
5
5
5
30
30
3
35
3
40
30
ns
50
0
30
ns
3
45
0
ns
40
3
40
0
5
ns
0
35
ns
40
ns
Note 1: Parameter guaranteed, but not tested.
AC CHARACTERISTICS WRITE CYCLE
Write Cycle
Parameter
Symbol
20ns
25ns
Alt.
Min
Write Cycle Time
tAVAV
tWC
20
25
35
ns
Chip Enable to End of Write
tELWH
tELEH
tCW
tCW
15
15
20
20
30
30
ns
ns
Address Setup Time
tAVWL
tAVEL
tAS
tAS
0
0
0
0
0
0
ns
ns
Address Valid to End of Write
tAVWH
tAVEH
tAW
tAW
15
15
20
20
30
30
ns
ns
Write Pulse Width
tWLWH
tWLEH
tWP
tWP
15
15
20
20
25
25
ns
ns
Write Recovery Time
tWHAX
tEHAX
tWR
TWR
0
0
0
0
0
0
ns
ns
tWHDX
tEHDX
tDH
tDH
3
3
3
3
3
3
ns
ns
Write to Output in High Z (1)
tWLQZ
tWHZ
0
Data to Write Time
tDVWH
tDVEH
tDW
tDW
12
12
15
15
20
20
ns
ns
Output Active from End of Write (1)
tWHQX
tWLZ
3
3
3
ns
Data Hold Time
Max
10
Min
35ns
JEDEC
0
Max
12
Min
0
Max
15
Units
ns
Note 1: Parameter guaranteed, but not tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 13A
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EDI8F8512C
White Electronic Designs
AC CHARACTERISTICS WRITE CYCLE
Symbol
Parameter
55ns
70ns
Max
Min
Write Cycle Time
tAVAV
tWC
55
70
85
100
ns
Chip Enable to End of Write
tELWH
tELEH
tCW
tCW
50
50
65
65
70
70
80
80
ns
ns
Address Setup Time
tAVWL
tAVEL
tAS
tAS
0
0
0
0
0
0
0
0
ns
ns
Address Valid to End of Write
tAVWH
tAVEH
tAW
tAW
50
50
65
65
70
70
80
80
ns
ns
Write Pulse Width
tWLWH
tWLEH
tWP
tWP
50
50
65
65
70
70
80
80
ns
ns
Write Recovery Time
tWHAX
tEHAX
tWR
tWR
0
0
0
0
0
0
0
0
ns
ns
Data Hold Time
tWHDX
tEHDX
tDH
tDH
0
0
0
0
0
0
0
0
ns
ns
Write to Output in High Z (1)
tWLQZ
tWHZ
0
Data to Write Time
tDVWH
tDVEH
tDW
tDW
30
30
30
30
35
35
40
40
ns
ns
Output Active from End of Write (1)
tWHQX
tWLZ
5
5
3
5
ns
0
Max
30
Min
100ns
Alt.
30
Min
85ns
JEDEC
0
Max
35
Min
0
Max
40
Units
ns
Note 1: Parameter guaranteed, but not tested.
FIG. 7 WRITE CYCLE 1 - W# CONTROLLED
tAVAV
A
E#
tELWH
tWHAX
tAVWH
tWLWH
W#
tAVWL
tDVWH
D
tWHDX
DATA VALID
tWHQX
tWLQZ
HIGH Z
Q
8F8512C Write Cyc1
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July 2002
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FIG. 8 WRITE CYCLE 2 - E# CONTROLLED
tAVAV
A
tAVEL
tELEH
E#
tEHAX
tAVEH
tWLEH
W#
tDVEH
D
tEHDX
DATA VALID
HIGH Z
Q
8F8512C Write Cyc2
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July 2002
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EDI8F8512C
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LP 70-100ns Only
DATA RETENTION CHARACTERISTICS
Characteristic
Sym
Test Conditions
Data Retention Voltage
VCC
VCC = 0.2V
Data Retention Quiescent Current
ICCDR
Chip Disable to Data Retention Time (1)
tCDR
E# ≥ VCC -0.2V
VIN ≥ VCC -0.2V
or VIN ≤ 0.2V
VCC
Min
Typ
Max
2
–
–
–
V
2V
–
10
125
185
µA
3V
–
20
200
250
µA
0
–
–
–
ns
tAVAV*
–
–
–
ns
70°C
tR
Operation Recovery Time (1)
Unit
85°C
*Read Cycle Time
Note: Parameter guaranteed, but not tested.
FIG. 9 DATA RETENTION E# CONTROLLED
DATA RETENTION MODE
4.5V
VCC
4.5V
VCC
tCDR
tR
E# VCC-0.2V
E#
8F8512C Data Retent.
ORDERING INFORMATION
Standard Power
Speed
(ns)
Package
No.
EDI8F8512C20M6C
20
183
EDI8F8512C25M6C
25
183
EDI8F8512C35M6C
35
183
EDI8F8512C70BSC
70
63
EDI8F8512C85BSC
85
63
EDI8F8512C100BSC
100
63
EDI8F8512C55B6C
55
91
EDI8F8512C70B6C
70
91
EDI8F8512C85B6C
85
91
EDI8F8512C100B6C
100
91
Low Power
with Data Retention
Speed
(ns)
Package
Leads
EDI8F8512LP70BSC
70
63
EDI8F8512LP85BSC
85
63
EDI8F8512LP100BSC
100
63
EDI8F8512LP70B6C
70
91
EDI8F8512LP85B6C
85
91
EDI8F8512LP100B6C
100
91
Note:
To order an Industrial grade product substitute the letter C in the Suffix with
the letter I, e.g., EDI8F8512C70B6C becomes EDI8F8512C70B6I.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 13A
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EDI8F8512C
White Electronic Designs
PACKAGE DESCRIPTIONS
PACKAGE NO. 63: 36 PIN SINGLE-IN-LINE PACKAGE
0.150
Max
4.040 Max.
0.575
0.565
0.125
Min
0.100
0.020
0.016
35 x 0.100 = 3.500
8F8512C Pkg1
PACKAGE NO. 91: 32 PIN DUAL-IN-LINE PACKAGE
1.665 MAX.
U5
R1
R2
.085
.065
NOTE 2
U1
.640
MAX.
U2
.100 TYP.
15 x .100
1.500 REF.
.248
MAX.
.175
.125
.025
.015
.620
.590
8F8512C Pkg 2
PACKAGE NO. 183: 32 PIN DUAL-IN-LINE PACKAGE
1.715 MAX.
.640
MAX.
1
.010
.005
T
NO
C
RE
O
F
ED
ND
E
M
OM
W
E
RN
S
N
G
I
S
DE
.355
MAX.
.175
.125
15 x .100
1.500 REF.
.620
.590
8F8512C Pkg3
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2002
Rev. 13A
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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