Renesas M62352AGP 8-bit 12ch d/a converter with buffer amplifier Datasheet

M62352AGP
8-bit 12ch D/A Converter with Buffer Amplifiers
REJ03D0867-0300
Rev.3.00
Mar 25, 2008
Description
M62352A is a CMOS structured semiconductor integrated circuit integrating 12 channels of built-in D/A converters
with high performance buffer operational amplifier or each channel output.
The 3-wire serial interface (DI, CLK, LD) method is used for the transfer format or digital data to allow connection
with microcomputer with minimum wiring. DO terminal is provided to allow cascading serial use.
Built-in buffer operational amplifiers are designed to operate or full swing in the whole voltage range from VCC to GND
for each input/output. And their higher stability for capacitive load perfectly fits in to the use for electronic volume
(VCA) or the replacement for semi-variable resistor for tuning.
Features
•
•
•
•
•
12-bit serial data input (3 wire serial data transfer method, DI, CLK, LD)
Corresponds to TTL input for digital input (VINH ≥ 2 V, VINL ≤ 0.8 V)
R-2R + segment method high performance 12ch 8-bit D/A converters
12ch buffer operational amplifiers operating in the whole voltage range from VCC to GND
Buffer operational amplifiers with high oscillation stability for capacitive load
Application
Adjustment or control of industrial or home-use electronic equipments such as VTR camera, VTR set, TV, and CRT
display.
Block Diagram
GND
AO2
AO1
DI
CLK
LD
DO
AO12
AO11
VCC
20
19
18
17
16
15
14
13
12
11
12
11
D/A
8-bit
latch
L
Address
decoder
(8)
........
....
+
−
D0 1 2 3 4 5 6 D7 D8 9 10 D11
1
8-bit R-2R
+ segment
D/A converter
+
−
+
−
+
−
Ch2
12-bit shift register
D/A
D/A
L
L
(12)
(12)
8-bit
latch
Ch3
L
4
L
6
L
7
L
8
L
9
L
10
D/A
D/A
D/A
D/A
+
−
+
−
+
−
+
−
D/A
+
−
D/A
+
−
+
−
D/A
+
−
8-bit R-2R
+ segment
D/A converter
L
5
(12)
1
2
3
4
5
6
7
8
9
10
VSS
(VrefL)
AO3
AO4
AO5
AO6
AO7
AO8
AO9
AO10
VDD
(VrefU)
REJ03D0867-0300 Rev.3.00 Mar 25, 2008
Page 1 of 8
M62352AGP
Pin Arrangement
M62352AGP
VSS
(VrefL)
AO3
1
20
2
19
GND
AO2
AO4
3
18
AO1
AO5
4
17
DI
AO6
5
16
CLK
AO7
6
15
LD
AO8
7
14
AO9
8
13
DO
AO12
AO10
9
12
AO11
VDD
(VrefU)
10
11
VCC
(Top view)
Outline: 20P2E-A
Pin Description
Pin No.
Pin Name
17
14
16
DI
DO
CLK
15
18
19
2
3
4
5
6
7
8
9
12
13
11
20
10
1
LD
AO1
AO2
AO3
AO4
AO5
AO6
AO7
AO8
AO9
AO10
AO11
AO12
VCC
GND
VDD
VSS
Function
Serial data input terminal. 12-bit serial data is input to this terminal.
Serial data output terminal. Serial data of 12-bit shift register is output from this terminal.
Serial clock input terminal. Input signal from DI terminal is input to 12-bit shift register
upon the rise of shift clock.
Data is loaded to register when "H" is input to LD terminal.
8-bit D/A converter output terminal.
Built-in buffer amp. is connected to VCC.
D/A converted voltage between VDD and VSS is output to each terminal.
Power supply terminal.
Digital and analog common GND
D/A converter high level reference voltage input terminal.
D/A converter low level reference voltage input terminal.
REJ03D0867-0300 Rev.3.00 Mar 25, 2008
Page 2 of 8
M62352AGP
Block Diagram for Explanation of Terminals
DI
CLK
VCC
GND
11
20
17
12-bit shift register
16
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
Decoder
(8)
(12)
14
DO
15
LD
1 2 3 4 5 6 7 8 9 10 11 12
.....
.....
.....
.....
.....
8-bit latch
8-bit latch
8-bit latch
........... 8-bit latch
8-bit latch
8-bit latch
8-bit D/A
converter
8-bit D/A
converter
8-bit D/A
converter
...........
8-bit D/A
converter
8-bit D/A
converter
8-bit D/A
converter
+
−
+
−
+
−
+
−
+
−
+
−
.....
A1
A4
A5
...........
10
18
AO1
VDD
(VrefU)
19
2
AO2
AO3
A10
.............
A11
A12
9
12
13
AO10
AO11
AO12
1
VSS
(VrefL)
Absolute Maximum Rating
Item
Supply voltage
D/A converter High level reference voltage
Digital input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
REJ03D0867-0300 Rev.3.00 Mar 25, 2008
Page 3 of 8
Symbol
VCC
VDD
VIN
Vout
Pd
Topr
Tstg
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
150
–20 to +85
–40 to +125
Unit
V
V
V
V
mW
°C
°C
M62352AGP
Electrical Characteristics
Digital Part
(VCC, VrefU = 5 V ± 10%, VCC ≥ VrefU, GND, VrefL = 0.0 V, Ta = –20 to +85°C, unless otherwise specified.)
Symbol
Min
Limits
Typ
Max
Unit
Supply voltage
Supply current
VCC
ICC
4.5
—
5.0
1.5
5.5
3.5
V
mA
Input leak current
Digital input Low voltage
Digital input High voltage
Digital output Low voltage
Digital output High voltage
IILK
VIL
VIH
VOL
VOH
–10
—
2.0
—
VCC – 0.4
—
—
—
—
—
10
0.8
—
0.4
—
µA
V
V
V
V
Item
Note:
Conditions
CLK = 1 MHz operation
VCC = 5 V, IAO = 0 µA
VIN = 0 to VCC
IOL = 2.5 mA
IOH = –400 µA
Changes from M62352GP: Digital input voltage corresponds to TTL spec.
Analog Part
(VCC, VrefU = 5 V ± 10%, VCC ≥ VrefU, GND, VrefL = 0.0 V, Ta = –20 to +85°C, unless otherwise specified.)
Item
Symbol
Min
Limits
Typ
Max
Unit
Reference voltage pin
current
IrefU
—
1.5
3.5
mA
D/A converter High level
reference voltage range
VDD
(VrefU)
3.5
—
VCC
V
D/A converter Low level
reference voltage range
VSS
(VrefL)
GND
—
VCC – 3.5
Buffer amplifier output
drive range
VAO
Buffer amplifier output dive
range
IAO
0.1
0.2
–1
—
—
—
VCC – 0.1
VCC – 0.2
1
mA
Differential nonlinearity
Nonlinearity
Zero code error
Full scale error
Output capacitive load
SDL
SL
SZERO
SFULL
CO
Buffer amplifier output
impedance
RO
–1.0
–1.5
–2.0
–2.0
—
—
—
—
—
—
—
5
1.0
1.5
2.0
2.0
0.1
—
LSB
LSB
LSB
LSB
µF
Ω
REJ03D0867-0300 Rev.3.00 Mar 25, 2008
Page 4 of 8
V
Conditions
VrefU = 5 V, VrefL = 0 V, IAO = 0 µA
Data condition: at maximum current
The output does not necessarily be
the Values within the reference
voltage setting range. The output
value is determined by the buffer
amplifier output voltage range (VAO).
IAO = ±100 µA
IAO = ±500 µA
Upper side saturation voltage = 0.3 V
Lower side saturation voltage = 0.2 V
VrefU = 4.79 V
VrefL = 0.95 V (15 mV/LSB)
VCC = 5.5 V
Without load (IAO = +0 µA)
M62352AGP
AC Characteristics
(VCC, VrefU = 5 V ± 10%, VCC ≥ VrefU, GND, VrefL = 0.0 V, Ta = –20 to +85°C, unless otherwise specified.)
Symbol
Min
Limits
Typ
Max
Unit
Clock "L" pulse width
Clock "H" pulse width
Clock rise time
tCKL
tCKH
tCR
200
200
—
—
—
—
ns
ns
—
—
200
ns
Clock fall time
tCF
Data setup time
Data hold time
LD setup time
LD hold time
LD "H" hold time
Data output delay time
D/A output setting time
tDCH
tCHD
tCHL
tLDC
tLDH
tDO
tLDD
30
60
200
100
100
70
—
—
—
—
—
—
—
—
—
—
—
—
—
350
300
ns
ns
ns
ns
ns
ns
µs
Item
Conditions
CL ≤ 100 pF
CL ≤ 100 pF, VAO: 0.5 ↔ 4.5 V
The time until the output becomes
the final value of 1/2 LSB
Measurement Circuit
Input
Output
DUT
CL ≤ 100 pF
Timing Chart
tCR
tCKH
tCF
tCHL
CLK
tCKL
tLDC
DI
tDCH
tCHD
tLDH
tCHL
LD
tLDD
AO1 to AO12
output
tDO
DO output
REJ03D0867-0300 Rev.3.00 Mar 25, 2008
Page 5 of 8
tDO
M62352AGP
Digital Data Format
First
MSB
Last
LSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
DAC data
D9
D10
D11
DAC select data
DAC Data
D0
0
1
0
1
:
0
1
D1
0
0
1
1
:
1
1
D2
0
0
0
0
:
1
1
D3
0
0
0
0
:
1
1
D4
0
0
0
0
:
1
1
D5
0
0
0
0
:
1
1
D6
0
0
0
1
:
1
1
D7
0
0
0
0
:
1
1
D/A Output
(VrefU – VrefL) / 256 × 1 + VrefL [V]
(VrefU – VrefL) / 256 × 2 + VrefL [V]
(VrefU – VrefL) / 256 × 3 + VrefL [V]
(VrefU – VrefL) / 256 × 4 + VrefL [V]
:
(VrefU – VrefL) / 256 × 255 + VrefL [V]
VrefU [V]
Note: VrefU = VDD, VrefL = VSS
DAC Select Data
D8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D10
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D11
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC Selection
Don’t care
AO1 select
AO2 select
AO3 select
AO4 select
AO5 select
AO6 select
AO7 select
AO8 select
AO9 select
AO10 select
AO11 select
AO12 select
Don’t care
Don’t care
Don’t care
Timing Chart (Model)
CLK
SI
D11 D10 D9
D8
LD
AO1
to
AO12
REJ03D0867-0300 Rev.3.00 Mar 25, 2008
Page 6 of 8
D7
D6
D5
D4
D3
D2
D1
D0
(1 LSB)
(2 LSB)
(3 LSB)
(4 LSB)
(255 LSB)
(256 LSB)
M62352AGP
Typical Application
11
10
VCC
VDD
(VrefU)
AO1 18
AO2 19
AO3
2
AO4
3
AO5
4
AO6
5
AO7
6
AO8
7
AO9
8
AO10
9
18 DI
17 CLK
MCU
16 LD
15 DO
AO11 12
AO12 13
GND
VSS
(VrefL)
20
1
Precaution for Use
M62352AGP has 3 terminals (VDD, VCC, and VSS) to which constant voltage is to be applied. Ripple voltage or spike
noise to these terminals may worsen converting precision or cause erroneous operations. So be sure to use this device
by putting capacitor between each terminal and GND to get D/A conversion operation stabilized.
Output buffer amplifiers have high oscillation stability against capacitive load. This means that jitters by wirings
around output terminals or capacitor between output and GND (0.1 µF Max.) do not cause any problems with DAC
operations.
Connect capacitor (0.1 µF or around) between output and GND for protection from spark discharge when this device is
used under such high electric field as that for instance of instruments with cathode ray tube.
REJ03D0867-0300 Rev.3.00 Mar 25, 2008
Page 7 of 8
M62352AGP
Package Dimensions
20P2E-A
Plastic 20pin 225mil SSOP
EIAJ Package Code
SSOP20-P-225-0.65
Weight(g)
0.08
JEDEC Code
—
e
b2
11
E
HE
e1
I2
20
Lead Material
Alloy 42
F
Recommended Mount Pad
Symbol
1
10
A
D
G
b
e
x
A2
M
A1
L
L1
y
c
z
Z1
Detail G
REJ03D0867-0300 Rev.3.00 Mar 25, 2008
Page 8 of 8
Detail F
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
x
y
b2
e1
I2
Dimension in Millimeters
Min
Nom
Max
—
—
1.45
0
0.1
0.2
—
—
1.15
0.17
0.32
0.22
0.13
0.15
0.2
6.4
6.5
6.6
4.3
4.4
4.5
—
—
0.65
6.2
6.4
6.6
0.3
0.5
0.7
—
—
1.0
0.325
—
—
0.475
—
—
0.13
—
—
—
—
0.1
—
0°
10°
—
—
0.35
—
—
5.8
—
—
1.0
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