TI1 LP3996 Dual linear regulator with 300ma and 150ma outputs and power-on-reset Datasheet

LP3996
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SNVS360B – NOVEMBER 2006 – REVISED JANUARY 2008
LP3996 Dual Linear Regulator with 300mA and 150mA Outputs and Power-On-Reset
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FEATURES
•
•
•
APPLICATIONS
1
2
•
•
2 LDO Outputs with Independent Enable
1.5% Accuracy at Room Temperature, 3% over
Temperature
Power-On-Reset Function with Adjustable
Delay
Thermal Shutdown Protection
•
•
•
Stable with Ceramic Capacitors
Cellular Handsets
PDAs
Wireless Network Adaptors
DESCRIPTION
The LP3996 is a dual low dropout regulator with power-on-reset circuit. The first regulator can source 150mA,
while the second is capable of sourcing 300mA and has a power-on-reset function included.
The LP3996 provides 1.5% accuracy requiring an ultra low quiescent current of 35µA. Separate enable pins
allow each output of the LP3996 to be shut down, drawing virtually zero current.
The LP3996 is designed to be stable with small footprint ceramic capacitors down to 1µF. An external capacitor
may be used to set the POR delay time as required.
The LP3996 is available in fixed output voltages and comes in a 10 pin, 3mm x 3mm package. .
Table 1. Key Specifications
VALUE
UNIT
Input Voltage Range
2.0V to 6.0
V
Low Dropout Voltage
210mV at
300mA
Ultra-Low IQ (enabled)
35
µA
Virtually Zero IQ (disabled)
<10
nA
Package available in Lead Free option.
10 pin 3mm x 3mm
Typical Application Circuit
470 k:
LP3996
VIN
VIN
VOUT1
VOUT1
EN1
EN1
VOUT2
VOUT2
EN2
EN2
POR
1 PF
CBYP
10 nF
POR
SET
GND
1 PF
1 PF
Sets delay
for POR
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
LP3996
SNVS360B – NOVEMBER 2006 – REVISED JANUARY 2008
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Functional Block Diagram
VOUT1
LDO1
VIN
EN1
LDO2
VOUT2
EN2
POR
POR
CBYP
1 PA
+
-
VREF
GND
SET
Pin Functions
Pin Descriptions
2
Pin No
Symbol
1
VIN
Voltage Supply Input. Connect a 1µF capacitor between this pin and GND.
Name and Function
2
EN1
Enable Input to Regulator 1. Active high input.
High = On. Low = OFF.
3
EN2
Enable Input to Regulator 2. Active high input.
High = On. Low = OFF.
4
CBYP
Internal Voltage Reference Bypass. Connect a 10nF capacitor from this pin to GND to reduce output
noise and improve line transient and PSRR.
This pin may be left open.
5
SET
Set Delay Input. Connect a capacitor between this pin and GND to set the POR delay time. If left open,
there will be no delay.
6
GND
Common Ground pin. Connect externally to exposed pad.
7
N/C
No Connection. Do not connect to any other pin.
8
POR
Power-On Reset Output. Open drain output. Active low indicates under-voltage output on Regulator 2.
A pull-up resistor is required for correct operation.
9
VOUT2
Output of Regulator 2. 300mA maximum current output. Connect a 1µF capacitor between this pin and
GND.
10
VOUT1
Output of Regulator 1. 150mA maximum current output. Connect a 1µF capacitor between this pin and
GND.
Pad
GND
Common Ground. Connect to Pin 6.
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Connection Diagram
Package
VOUT1
10
VOUT2
9
POR
N/C
GND
8
7
6
GND
1
2
3
4
5
VIN
EN1
EN2
CBYP
SET
Top View
Figure 1.
Table 2. For other voltage options, please contact your local NSC sales office* These parts avaliable
soon.
Output Voltage (V)
Vout1
Vout2
0.8
3.3
1.0
1.8
Order Number
Spec
Package Marking
LP3996SD-0833
NOPB
L167B
LP3996SDX-0833
NOPB
Supplied As
1000 Units, Tapeand-Reel
4500 Units, Tapeand-Reel
LP3996SD-0833
1000 Units, Tapeand-Reel
LP3996SDX-0833
4500 Units, Tapeand-Reel
LP3996SD-1018
NOPB
LP3996SDX-1018
NOPB
L227B
1000 Units, Tapeand-Reel
4500 Units, Tapeand-Reel
LP3996SD-1018
1000 Units, Tapeand-Reel
LP3996SDX-1018
4500 Units, Tapeand-Reel
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Table 2. For other voltage options, please contact your local NSC sales office* These parts avaliable
soon.
(continued)
Output Voltage (V)
Vout1
Vout2
1.5
2.5
1.8
2.5
2.8
3.0
3.0
4
3.3
3.3
2.8
3.0
3.3
Order Number
Spec
Package Marking
LP3996SD-1525
NOPB
L168B
LP3996SDX-1525
NOPB
Supplied As
1000 Units, Tapeand-Reel
4500 Units, Tapeand-Reel
LP3996SD-1525
1000 Units, Tapeand-Reel
LP3996SDX-1525
4500 Units, Tapeand-Reel
LP3996SD-1833
NOPB
LP3996SDX-1833
NOPB
L228B
1000 Units, Tapeand-Reel
4500 Units, Tapeand-Reel
LP3996SD-1833
1000 Units, Tapeand-Reel
LP3996SDX-1833
4500 Units, Tapeand-Reel
LP3996SD-2533
NOPB
LP3996SDX-2533
NOPB
L229B
1000 Units, Tapeand-Reel
4500 Units, Tapeand-Reel
LP3996SDX-2533
1000 Units, Tapeand-Reel
LP3996SD-2533
4500 Units, Tapeand-Reel
LP3996SD-2828
NOPB
LP3996SDX-2828
NOPB
L171B
1000 Units, Tapeand-Reel
4500 Units, Tapeand-Reel
LP3996SD-2828
1000 Units, Tapeand-Reel
LP3996SDX-2828
4500 Units, Tapeand-Reel
LP3996SD-3030
NOPB
LP3996SDX-3030
NOPB
L172B
1000 Units, Tapeand-Reel
4500 Units, Tapeand-Reel
LP3996SD-3030
1000 Units, Tapeand-Reel
LP3996SDX-3030
4500 Units, Tapeand-Reel
LP3996SD-3033
NOPB
LP3996SDX-3033
NOPB
L170B
1000 Units, Tapeand-Reel
4500 Units, Tapeand-Reel
LP3996SD-3033
1000 Units, Tapeand-Reel
LP3996SDX-3033
4500 Units, Tapeand-Reel
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Table 2. For other voltage options, please contact your local NSC sales office* These parts avaliable
soon.
(continued)
Output Voltage (V)
Vout1
Vout2
3.3
0.8
3.3
Order Number
3.3
Spec
Package Marking
LP3996SD-3308
NOPB
L188B
LP3996SDX-3308
NOPB
Supplied As
1000 Units, Tapeand-Reel
4500 Units, Tapeand-Reel
LP3996SD-3308
1000 Units, Tapeand-Reel
LP3996SDX-3308
4500 Units, Tapeand-Reel
LP3996SD-3333
NOPB
LP3996SDX-3333
NOPB
L173B
1000 Units, Tapeand-Reel
4500 Units, Tapeand-Reel
LP3996SD-3333
1000 Units, Tapeand-Reel
LP3996SDX-3333
4500 Units, Tapeand-Reel
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Input Voltage to GND
-0.3V to 6.5V
VOUT1, VOUT2 EN1 and EN2 Voltage to GND
-0.3V to (VIN + 0.3V) with 6.5V (max)
POR to GND
-0.3V to 6.5V
Junction Temperature (TJ-MAX)
Lead/Pad Temp.
150°C
(3)
235°C
Storage Temperature
-65°C to 150°C
Continuous Power Dissipation Internally Limited (4)
ESD Rating (5)
Human Body Model
2.0kV
Machine Model
200V
(1)
(2)
(3)
(4)
(5)
All Voltages are with respect to the potential at the GND pin.
Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the
device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated
test conditions, see the Electrical Characteristics tables.
For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN-1187, Leadless
Leadframe Package.
Internal thermal shutdown circuitry protects the device from permanent damage.
The human body model is 100pF discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor
discharged directly into each pin.
Operating Ratings
(1) (2)
Input Voltage
2.0V to 6.0V
EN1, EN2, POR Voltage
0 to (VIN + 0.3V) to 6.0V (max)
Junction Temperature
(1)
(2)
-40°C to 125°C
Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the
device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated
test conditions, see the Electrical Characteristics tables.
All Voltages are with respect to the potential at the GND pin.
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Operating Ratings (1) (2) (continued)
Ambient Temperature TARange
-40°C to 85°C
(3)
(3)
The maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op) = 125°C), the
maximum power dissipation of the device in the application (PD(max)), and the junction to ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max-op) - (θJA × PD(max)).
Thermal Properties
(1)
Junction To Ambient Thermal Resistance (2)
θJALLP-10 Package
(1)
(2)
6
55°C/W
Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the
device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated
test conditions, see the Electrical Characteristics tables.
Junction to ambient thermal resistance is dependant on the application and board layout. In applications where high maximum power
dissipation is possible, special care must be paid to thermal dissipation issues in board design.
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Electrical Characteristics (1)
(2)
Unless otherwise noted, VEN = 950mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and
VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0µF.
Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in boldface type apply over the full
junction temperature range for operation, −40 to +125°C.
Symbol
Parameter
Input Voltage
ΔVOUT
Output Voltage Tolerance
IOUT = 1mA
ISC
Short Circuit Current Limit
IOUT
Maximum Output Current
PSRR
en
Power Supply Rejection Ratio
Output noise Voltage
TSHUTDOWN
(5)
(5)
Thermal Shutdown
Max
2
6
+2.5
+3.75
VOUT ≤ 1.5V
-2.75
-4
+2.75
+4
Load Regulation Error
Quiescent Current
Min
-2.5
-3.75
VIN = (VOUT(NOM) + 1.0V) to 6.0V
(4)
Limit
1.5V < VOUT ≤ 3.3V
Line Regulation Error
Dropout Voltage
IQ
Typ
(3)
VIN
VDO
Conditions
0.03
0.3
IOUT = 1mA to 150mA
(LDO 1)
85
155
IOUT = 1mA to 300mA
(LDO 2)
26
85
IOUT = 1mA to 150mA
(LDO 1)
110
220
IOUT = 1mA to 300mA
(LDO 2)
210
550
LDO 1 ON, LDO 2 ON
IOUT1= IOUT2 = 0mA
35
100
LDO 1 ON, LDO 2 OFF
IOUT1 = 150mA
45
110
LDO 1 OFF, LDO 2 ON
IOUT2 = 300mA
45
110
LDO 1 ON, LDO 2 ON
IOUT1 = 150mA, IOUT2 = 300mA
70
170
Units
V
%
%/V
µV/mA
mV
µA
VEN1 = VEN2 = 0.4V
0.5
10
LDO 1
420
750
LDO 2
550
840
LDO 1
150
LDO 2
300
f = 1kHz, IOUT =
1mA to 150mA
CBYP = 10nF
LDO1
58
LDO2
70
f = 20kHz, IOUT
= 1mA to
150mA
CBYP = 10nF
LDO1
45
LDO2
60
BW = 10Hz to
100kHz
CBYP = 10nF
VOUT = 0.8V
36
VOUT = 3.3V
75
nA
mA
mA
dB
µVRMS
Temperature
160
Hysteresis
20
VEN = 0.0V
0.005
0.1
2
5
°C
Enable Control Characteristics
IEN
Input Current at VEN1 or VEN2
VEN = 6V
(1)
(2)
(3)
(4)
(5)
µA
All Voltages are with respect to the potential at the GND pin.
Min Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most
likely norm.
VIN(MIN) = VOUT(NOM) + 0.5V, or 2.0V, whichever is higher.
Dropout voltage is voltage difference between input and output at which the output voltage drops to 100mV below its nominal value.
This parameter only for output voltages above 2.0V
This electrical specification is guaranteed by design.
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Electrical Characteristics(1) (2) (continued)
Unless otherwise noted, VEN = 950mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and
VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0µF.
Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in boldface type apply over the full
junction temperature range for operation, −40 to +125°C.
Symbol
Parameter
VIL
Low Input Threshold at VEN1 or
VEN2
VIH
High Input Threshold at VEN1 or
VEN2
Conditions
Typ
Limit
Min
Max
0.4
0.95
Units
V
V
POR Output Characteristics
VTH
Low Threshold % 0f VOUT2 (NOM)
Flag ON
88
High Threshold % 0f VOUT2 (NOM)
Flag OFF
IPOR
Leakage Current
Flag OFF, VPOR = 6.5V
30
nA
VOL
Flag Output Low Voltage
ISINK = 250µA
20
mV
To 95% Level
CBYP = 10nF
300
µs
96
%
Timing Characteristics
(5)
TON
Turn On Time
Transient
Response
Line Transient Response |δVOUT|
Trise = Tfall = 10µs
δVIN = 1VCBYP = 10nF
20
Load Transient Response |δVOUT|
Trise = Tfall =
1µs
LDO 1
IOUT = 1mA to 150mA
175
LDO 2
IOUT = 1mA to 300mA
150
(5)
(5)
mV
(pk - pk)
SET Input Characteristics
ISET
SET Pin Current Source
VSET = 0V
1.3
µA
VTH(SET)
SET Pin Threshold Voltage
POR = High
1.25
V
8
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Output Capacitor, Recommended Specifications
Symbol
COUT
Parameter
Conditions
Output Capacitance
Nom
Capacitance
1.0
(1)
Max
Units
0.7
ESR
(1)
Limit
Min
5
µF
500
mΩ
The Capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be
considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended
capacitor is X7R. However, depending on the application, X5R, Y5V and Z5U can also be used. (See capacitor section in Applications
Hints).
Transient Test Conditions
Figure 2. PSRR Input Signal
VOUT
tr
VOUT ± tolerance
tr
VIN
trise = tfall = 10 Ps
VOUT(NOM) + 1V
Line Step = 1V
ILOAD(LDO1) = 150 mA
ILOAD(LDO2) = 300 mA
Figure 3. Line Transient Input Test Signal
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VOUT
tr
VOUT ± tolerance
tr
VIN
Load Step LDO1 = 1 mA to 150 mA
Load Step LDO2 = 1 mA to 300 mA
Load Rise Time = Fall = 1 Ps
Figure 4. Load Transient Input Signal
10
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Typical Performance Characteristics.
Unless otherwise specified, CIN = 1.0µF Ceramic, COUT1 = COUT2 = 1.0µF Ceramic, CBYP = 10nF, VIN = VOUT2(NOM) + 1.0V, TA =
25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.
Output Voltage Change vs Temperature
Ground Current vs Load Current, LDO1
Ground Current vs Load Current, LDO2
Ground Current vs VIN. ILOAD = 1mA
Dropout Voltage vs ILOAD, LDO1
Dropout Voltage vs ILOAD, LDO2
Short Circuit Current, LDO1
Short Circuit Current, LDO2
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Typical Performance Characteristics. (continued)
Unless otherwise specified, CIN = 1.0µF Ceramic, COUT1 = COUT2 = 1.0µF Ceramic, CBYP = 10nF, VIN = VOUT2(NOM) + 1.0V, TA =
25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.
12
Power Supply Rejection Ratio, LDO1
Power Supply Rejection Ratio, LDO2
Enable Start-up Time, CBYP=0
Enable Start-up Time, CBYP=10nF
Line Transient, CBYP=10nF
Line Transient, CBYP=0
Load Transient, LDO1
Load Transient, LDO2
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Typical Performance Characteristics. (continued)
Unless otherwise specified, CIN = 1.0µF Ceramic, COUT1 = COUT2 = 1.0µF Ceramic, CBYP = 10nF, VIN = VOUT2(NOM) + 1.0V, TA =
25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN.
Noise Density LDO1
Noise Density, LDO2
Power-on-Reset Start-up Operation
Power-on-Reset Shutdown Operation
POR Delay Time
Application Hints
OPERATION DESCRIPTION
The LP3996 is a low quiescent current, power management IC, designed specifically for portable applications
requiring minimum board space and smallest components. The LP3996 contains two independently selectable
LDOs. The first is capable of sourcing 150mA at outputs between 0.8V and 3.3V. The second can source 300mA
at an output voltage of 0.8V to 3.3V. In addition, LDO2 contains power good flag circuit, which monitors the
output voltage and indicates when it is within 8% of its nominal value. The flag will also act as a power-on-reset
signal and, by adding an external capacitor; a delay may be programmed for the POR output.
INPUT CAPACITOR
An input capacitor is required for stability. It is recommended that a 1.0µF capacitor be connected between the
LP3996 input pin and ground (this capacitance value may be increased without limit).
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This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean
analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain
approximately 1.0µF over the entire operating temperature range.
OUTPUT CAPACITOR
The LP3996 is designed specifically to work with very small ceramic output capacitors. A 1.0µF ceramic
capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5mΩ to 500mΩ, is suitable in the LP3996
application circuit.
For this device the output capacitor should be connected between the VOUT pin and ground.
It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as
attractive for reasons of size and cost (see the section Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5mΩ to 500mΩ for stability.
NO-LOAD STABILITY
The LP3996 will remain stable and in regulation with no external load. This is an important consideration in some
circuits, for example CMOS RAM keep-alive applications.
CAPACITOR CHARACTERISTICS
The LP3996 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47µF to 4.7µF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1.0µF ceramic capacitor is in the range of 20mΩ to 40mΩ, which easily meets the ESR
requirement for stability for the LP3996.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type.
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.
The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer
performance figures in general. As an example, Figure 5 shows a typical graph comparing different capacitor
case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result
in the capacitance value falling below the minimum value given in the recommended capacitor specifications
table (0.7µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size
capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for
the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be
suitable in the actual application.
14
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CAP VALUE (% OF NOM. 1 uF)
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0603, 10V, X5R
100%
80%
60%
0402, 6.3V, X5R
40%_
20%
_
0
1.0
2.0
_
3.0
_
4.0
_
5.0
_
DC BIAS (V)
Figure 5. Graph Showing a Typical Variation in Capacitance vs DC Bias
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of -55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R
has a similar tolerance over a reduced temperature range of -55°C to +85°C. Many large value ceramic
capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47µF to 4.7µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to -40°C, so some guard band must be allowed.
ENABLE CONTROL
The LP3996 features active high enable pins for each regulator, EN1 and EN2, which turns the corresponding
LDO off when pulled low. The device outputs are enabled when the enable lines are set to high. When not
enabled the regulator output is off and the device typically consumes 2nA.
If the application does not require the Enable switching feature, one or both enable pins should be tied to VIN to
keep the regulator output permanently on.
To ensure proper operation, the signal source used to drive the enable inputs must be able to swing above and
below the specified turn-on / off voltage thresholds listed in the Electrical Characteristics section under VIL and
VIH.
POWER-ON-RESET
The POR pin is an open-drain output which will be set to Low whenever the output of LDO2 falls out of regulation
to approximately 90% of its nominal value. An external pull-up resistor, connected to VOUT or VIN, is required on
this pin. During start-up, or whenever a fault condition is removed, the POR flag will return to the High state after
the output reaches approximately 96% of its nominal value. By connecting a capacitor from the SET pin to GND,
a delay to the rising condition of the POR flag may be introduced. The delayed signal may then be used as a
Power-on -Reset for a microprocessor within the user's application.
The duration of the delay is determined by the time to charge the delay capacitor to a threshold voltage of 1.25V
at 1.2µA from the SET pin as in the formula below.
Submit Documentation Feedback
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Links: LP3996
15
LP3996
SNVS360B – NOVEMBER 2006 – REVISED JANUARY 2008
www.ti.com
VTH(SET) X CSET
tDELAY =
ISET
A 0.1µF capacitor will introduce a delay of approximately 100ms.
BYPASS CAPACITOR
The internal voltage reference circuit of the LP3996 is connected to the CBYP pin via a high value internal resistor.
An external capacitor, connected to this pin, forms a low-pass filter which reduces the noise level on both outputs
of the device. There is also some improvement in PSSR and line transient performance. Internal circuitry ensures
rapid charging of the CBYP capacitor during start-up. A 10nF, high quality ceramic capacitor with either NPO or
COG dielectric is recommended due to their low leakage characteristics and low noise performance.
SAFE AREA OF OPERATION
Due consideration should be given to operating conditions to avoid excessive thermal dissipation of the LP3996
or triggering its thermal shutdown circuit. When both outputs are enabled, the total power dissipation will be
PD(LDO1) + PD(LDO2) Where PD = (VIN - VOUT) x IOUT for each LDO.
In general, device options which have a large difference in output voltage will dissipate more power when both
outputs are enabled, due to the input voltage required for the higher output voltage LDO. In such cases,
especially at elevated ambient temperature, it may not be possible to operate both outputs at maximum current
at the same time.
16
Submit Documentation Feedback
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Links: LP3996
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Samples
(3)
(Requires Login)
LP3996SD-0833
ACTIVE
SON
DSC
10
1000
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SD-0833/NOPB
ACTIVE
SON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SD-1018/NOPB
ACTIVE
SON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SD-1525
ACTIVE
SON
DSC
10
1000
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SD-1525/NOPB
ACTIVE
SON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SD-1833/NOPB
ACTIVE
SON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SD-2533/NOPB
ACTIVE
SON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SD-2828
ACTIVE
SON
DSC
10
1000
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SD-2828/NOPB
ACTIVE
SON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SD-3030
ACTIVE
SON
DSC
10
1000
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SD-3030/NOPB
ACTIVE
SON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SD-3033
ACTIVE
SON
DSC
10
1000
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SD-3033/NOPB
ACTIVE
SON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SD-3308
ACTIVE
SON
DSC
10
1000
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SD-3308/NOPB
ACTIVE
SON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SD-3333
ACTIVE
SON
DSC
10
1000
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SD-3333/NOPB
ACTIVE
SON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SDX-0833
ACTIVE
SON
DSC
10
4500
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SDX-0833/NOPB
ACTIVE
SON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SDX-1018/NOPB
ACTIVE
SON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SDX-1525
ACTIVE
SON
DSC
10
4500
TBD
CU SNPB
Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2012
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Samples
(3)
(Requires Login)
LP3996SDX-1525/NOPB
ACTIVE
SON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SDX-1833/NOPB
ACTIVE
SON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SDX-2533/NOPB
ACTIVE
SON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SDX-2828
ACTIVE
SON
DSC
10
4500
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SDX-2828/NOPB
ACTIVE
SON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SDX-3030
ACTIVE
SON
DSC
10
4500
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SDX-3030/NOPB
ACTIVE
SON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SDX-3033
ACTIVE
SON
DSC
10
4500
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SDX-3033/NOPB
ACTIVE
SON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SDX-3308
ACTIVE
SON
DSC
10
4500
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SDX-3308/NOPB
ACTIVE
SON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LP3996SDX-3333
ACTIVE
SON
DSC
10
4500
TBD
CU SNPB
Level-1-260C-UNLIM
LP3996SDX-3333/NOPB
ACTIVE
SON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
17-Nov-2012
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP3996SD-0833
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-0833/NOPB
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-1018/NOPB
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-1525
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-1525/NOPB
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-1833/NOPB
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-2533/NOPB
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-2828
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-2828/NOPB
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-3030
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-3030/NOPB
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-3033
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-3033/NOPB
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-3308
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-3308/NOPB
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-3333
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SD-3333/NOPB
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-0833
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP3996SDX-0833/NOPB
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-1018/NOPB
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-1525
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-1525/NOPB
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-1833/NOPB
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-2533/NOPB
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-2828
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-2828/NOPB
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-3030
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-3030/NOPB
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-3033
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-3033/NOPB
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-3308
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-3308/NOPB
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-3333
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
LP3996SDX-3333/NOPB
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP3996SD-0833
SON
DSC
10
1000
203.0
190.0
41.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP3996SD-0833/NOPB
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-1018/NOPB
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-1525
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-1525/NOPB
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-1833/NOPB
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-2533/NOPB
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-2828
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-2828/NOPB
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-3030
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-3030/NOPB
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-3033
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-3033/NOPB
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-3308
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-3308/NOPB
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-3333
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SD-3333/NOPB
SON
DSC
10
1000
203.0
190.0
41.0
LP3996SDX-0833
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-0833/NOPB
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-1018/NOPB
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-1525
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-1525/NOPB
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-1833/NOPB
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-2533/NOPB
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-2828
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-2828/NOPB
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-3030
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-3030/NOPB
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-3033
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-3033/NOPB
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-3308
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-3308/NOPB
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-3333
SON
DSC
10
4500
349.0
337.0
45.0
LP3996SDX-3333/NOPB
SON
DSC
10
4500
349.0
337.0
45.0
Pack Materials-Page 3
MECHANICAL DATA
DSC0010B
TOP SIDE OF PACKAGE
BOTTOM SIDE OF PACKAGE
SDA10B (Rev A)
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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LP3996SD-0833 LP3996SD-1525 LP3996SD-2828 LP3996SD-2828EV LP3996SD-3030 LP3996SD-3030EV
LP3996SD-3033 LP3996SD-3308 LP3996SD-3333 LP3996SD-3333EV LP3996SDX-0833 LP3996SDX-1525
LP3996SDX-2828 LP3996SDX-3030 LP3996SDX-3033 LP3996SDX-3308 LP3996SDX-3333