LTC1854/LTC1855/LTC1856
8-Channel, ±10V Input
12-/14-/16-Bit, 100ksps ADC
Converters with Shutdown
Description
Features
n
n
n
n
n
n
n
n
n
n
n
n
Single 5V Supply
Sample Rate: 100ksps
8-Channel Multiplexer with ±30V Protection
±10V Bipolar Input Range
Single Ended or Differential
±3LSB INL for the LTC1856, ±1.5LSB INL for the
LTC1855, ±1LSB INL for the LTC1854
Power Dissipation: 40mW (Typ)
SPI/MICROWIRE™ Compatible Serial I/O
Power Shutdown: Nap and Sleep
SINAD: 87dB (LTC1856)
Operates with Internal or External Reference
Internal Synchronized Clock
28-Pin SSOP Package
The LTC®1854/LTC1855/LTC1856 are 8-channel, low
power, 12-/14-/16-bit, 100ksps, analog-to-digital converters (ADCs). These ADCs operate from a single 5V
supply and the 8‑channel multiplexer can be programmed
for single-ended inputs, pairs of differential inputs, or
combinations of both. In addition, all channels are fault
protected to ±30V. A fault condition on any channel will not
affect the conversion result of the selected channel.
An onboard precision reference minimizes external components. Power dissipation is 40mW at 100ksps and lower
in two power shutdown modes (27.5mW in Nap mode and
40µW in Sleep mode.) DC specifications include ±3LSB
INL for the LTC1856, ±1.5LSB INL for the LTC1855 and
±1LSB for the LTC1854.
The internal clock is trimmed for 5µs maximum conversion
time and the sampling rate is guaranteed at 100ksps. A
separate convert start input and data ready signal (BUSY)
ease connections to FIFOs, DSPs and microprocessors.
Applications
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Industrial Process Control
Multiplexed Data Acquisition Systems
High Speed Data Acquisition for PCs
Digital Signal Processing
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Typical Application
100kHz, 12-Bit/14-/16-Bit Sampling ADC
1.5
µP
CONTROL
LINES
0.1µF
1.0
10µF
10µF
0.1µF
10µF
3V TO 5V
5V
5V
0.1µF
2.5V
1µF
10µF
0.1µF
INL (LSB)
SOFTWARE-PROGRAMMABLE
SINGLE-ENDED OR
DIFFERENTIAL INPUTS
±10V BIPOLAR INPUT RANGE
COM
CONVST
CH0 LTC1854/ RD
CH1 LTC1855/ SCK
CH2 LTC1856 SDI
CH3
DGND
CH4
SDO
CH5
BUSY
CH6
OVDD
DVDD
CH7
+
AVDD
MUXOUT
MUXOUT–
AGND3
+
ADC
AGND2
ADC–
REFCOMP
AGND1
VREF
LTC1856 Typical INL Curve
2.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–32768
–16384
0
CODE
16384
32767
185456 G01
1854565af
1
LTC1854/LTC1855/LTC1856
Absolute Maximum Ratings
Package/order information
(Notes 1, 2)
TOP VIEW
Supply Voltage (OVDD = DVDD = AVDD = VDD)............. 6V
Ground Voltage Difference
DGND, AGND1, AGND2, AGND3........................ ±0.3V
Analog Input Voltage
ADC+, ADC–
(Note 3)....................(AGND1 – 0.3V) to (AVDD + 0.3V)
CH0-CH7, COM .................................................... ±30V
Digital Input Voltage (Note 4) .......(DGND – 0.3V) to 10V
Digital Output Voltage .....(DGND – 0.3V) to (DVDD + 0.3V)
Power Dissipation................................................. 500mW
Operating Temperature Range
LTC1854C/LTC1855C/LTC1856C............... 0°C to 70°C
LTC1854I/LTC1855I/LTC1856I.............. – 40°C to 85°C
Storage Temperature Range.................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
COM
1
28 CONVST
CH0
2
27 RD
CH1
3
26 SCK
CH2
4
25 SDI
CH3
5
24 DGND
CH4
6
23 SDO
CH5
7
22 BUSY
CH6
8
21 OVDD
CH7
9
20 DVDD
MUXOUT+ 10
19 AVDD
MUXOUT– 11
18 AGND3
ADC+ 12
17 AGND2
ADC– 13
16 REFCOMP
AGND1 14
15 VREF
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 160°C/W
EXPOSED PAD (PIN #) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER
LTC1854CG
LTC1854IG
LTC1855CG
LTC1855IG
LTC1856CG
LTC1856IG
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
converter and multiplexer characteristics
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
MUXOUT connected to ADC inputs. (Notes 5, 6)
LTC1854
PARAMETER
CONDITIONS
MIN
TYP
LTC1855
MAX
MIN
TYP
LTC1856
MAX
MIN
TYP
MAX
UNITS
Resolution
l
12
14
15
Bits
No Missing Codes
l
12
14
15
Bits
Transition Noise
Integral Linearity Error
0.06
(Note 7)
Differential Linearity Error
Bipolar Zero Error
l
(Note 8)
–1
1
±0.1
Bipolar Zero Error Match
Bipolar Full-Scale Error
External Reference (Note 11) l
Internal Reference (Note 11)
Bipolar Full-Scale Error Drift
External Reference
Internal Reference
Input Common Mode Range
Input Common Mode Rejection Ratio
2
–1
1.5
LSBRMS
±3
LSB
4
LSB
±23
LSB
±0.1
ppm/°C
3
4
10
±0.34
±0.45
±0.14
±0.40
±0.1
±0.4
±2.5
±7
5
l
–2
±8
±0.1
±2.5
±7
Bipolar Full-Scale Error Match
1
±1.5
±5
l
Bipolar Zero Error Drift
0.25
±1
l
±2.5
±7
10
LSB
%
%
ppm/°C
ppm/°C
15
LSB
±10
±+10
±10
V
96
96
96
dB
185456fa
LTC1854/LTC1855/LTC1856
analog input
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
PARAMETER
Analog Input Range
CONDITIONS
MIN
TYP
CH0 to CH7, COM
ADC+, ADC– (Note 3)
Impedance
Capacitance
Input Leakage Current
MAX
UNITS
±10
V
ADC – ±2.048
V
CH0 to CH7, COM
31
kΩ
MUXOUT+ , MUXOUT–
5
kΩ
CH0 to CH7, COM
5
pF
Sample Mode ADC+, ADC–
12
pF
Hold Mode ADC+, ADC–
4
pF
ADC+, ADC–, CONVST = Low
±1
l
µA
dynamic accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. MUXOUT connected to ADC inputs. (Note 5)
LTC1854
SYMBOL PARAMETER
CONDITIONS
S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal
THD
MIN
TYP
LTC1855
MAX
MIN
TYP
LTC1856
MAX
MIN
TYP
MAX
UNITS
74
83
87
dB
–102
–95
–101
dB
–99
–99
–103
dB
–120
–120
–120
dB
1
1
1
Aperture Delay
–70
–70
–70
ns
Aperture Jitter
60
60
60
ps
Total Harmonic Distortion
1kHz Input Signal
First Five Harmonics
Peak Harmonic or Spurious Noise
1kHz Input Signal
Channel-to-Channel Isolation
1kHz Input Signal
–3dB Input Bandwidth
Transient Response
Full-Scale Step
(Note 9)
Overvoltage Recovery
(Note 12)
4
150
4
150
MHz
4
150
µs
ns
1854565af
3
LTC1854/LTC1855/LTC1856
internal reference Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
l
VREF Output Temperature Coefficient
IOUT = 0
VREF Output Impedance
–0.1mA ≤ IOUT ≤ 0.1mA
VREFCOMP Output Voltage
IOUT = 0
MIN
TYP
MAX
UNITS
2.475
2.50
2.525
V
±10
ppm/°C
8
kΩ
4.096
V
digital inputs and digital outputs
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
l
VIL
Low Level Input Voltage
VDD = 4.75V
l
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
l
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
MIN
VDD = 4.75V, IO = –10µA, OVDD = VDD
VDD = 4.75V, IO = –200µA, OVDD = VDD
l
VDD = 4.75V, IO = 160µA, OVDD = VDD
VDD = 4.75V, IO = 1.6mA, OVDD = VDD
l
l
TYP
MAX
UNITS
2.4
4
V
5
pF
4.74
V
V
0.05
0.10
0.4
V
V
±10
µA
IOZ
Hi-Z Output Leakage
VOUT = 0V to VDD, RD = High
COZ
Hi-Z Output Capacitance
RD = High
15
pF
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
power requirements
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Voltage
(Notes 9 and 10)
4.75
5.00
5.25
V
CONVST = 0V or 5V
8.0
5.5
8.0
12
7
13
CONVST = 0V or 5V
40.0
27.5
40.0
Positive Supply Current
Nap Mode
Sleep Mode
Power Dissipation
Nap Mode
Sleep Mode
4
l
mA
mA
µA
mW
mW
µW
185456fa
LTC1854/LTC1855/LTC1856
timing Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
fSAMPLE(MAX)
Maximum Sampling Frequency
Through CH0 to CH7 Inputs
Through ADC+ , ADC– Only
tCONV
Conversion Time
tACQ
Acquisition Time
Through CH0 to CH7 Inputs
Through ADC+, ADC– Only
l
fSCK
SCK Frequency
(Note 13)
l
tr
SDO Rise Time
See Test Circuits
6
ns
tf
SDO Fall Time
See Test Circuits
6
ns
t1
CONVST High Time
t2
CONVST to BUSY Delay
l
100
1
l
MAX
0
5
µs
4
µs
µs
20
MHz
40
ns
15
l
UNITS
kHz
kHz
166
4
l
CL = 25pF, See Test Circuits
TYP
30
ns
t3
SCK Period
l
50
ns
t4
SCK High
l
10
ns
t5
SCK Low
l
10
ns
t6
Delay Time, SCK↓ to SDO Valid
CL = 25pF, See Test Circuits
l
t7
Time from Previous SDO Data Remains
Valid After SCK↓
CL = 25pF, See Test Circuits
l
t8
SDO Valid After RD↓
CL = 25pF, See Test Circuits
l
t9
RD↓ to SCK Setup Time
l
20
ns
25
5
45
20
11
ns
ns
30
ns
t10
SDI Setup Time Before SCK↑
l
0
ns
t11
SDI Hold Time After SCK↑
l
7
ns
t12
SDO Valid Before BUSY↑
RD = Low, CL = 25pF, See Test Circuits
l
5
t13
Bus Relinquish Time
See Test Circuits
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND, AGND1,
AGND2 and AGND3 wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above AVDD =
DVDD = OVDD = VDD, they will be clamped by internal diodes. This product
can handle currents of greater than 100mA below ground or above VDD
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle currents of greater
than 100mA below ground without latchup. These pins are not clamped to
VDD.
Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a singleended analog MUX input with respect to ground or ADC+ with respect to
ADC– tied to ground.
20
10
ns
30
ns
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar zero error is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111 for the LTC1856, between 00 0000 0000 0000 and 11
1111 1111 1111 for the LTC1855 and between 0000 0000 0000 and 1111
1111 1111 for the LTC1854.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: Full-scale bipolar error is the worst case of –FS or +FS
untrimmed deviation from ideal first and last code transitions, divided by
the full-scale range, and includes the effect of offset error.
Note 12: Recovers to specified performance after (2 • FS) input
overvoltage.
Note 13: t6 of 45ns maximum allows fSCK up to 10MHz for rising capture
with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns
setup time for the receiving logic).
1854565af
5
LTC1854/LTC1855/LTC1856
Typical Performance Characteristics
LTC1856 Typical INL Curve
2.0
1.5
1.0
1.0
0.5
0.5
0
–0.5
0
–0.5
–1.0
–1.0
–1.5
–1.5
–2.0
–32768
–16384
0
16384
0
MAGNITUDE (dB)
1.5
DNL (LSB)
INL (LSB)
2.0
–2.0
–32768
32767
–16384
0
16384
LTC1855 Typical INL Curve
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
DNL (LSB)
INL (LSB)
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
4096
MAGNITUDE (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
–1
–8192
8191
–4096
0
4096
0
1.0
1.0
0.8
0.8
0.6
0.4
0.2
0.2
DNL (LSB)
0.6
0.4
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
–2048
–1.0
–2048
1024
2047
185456 G07
10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
LTC1854 Nonaveraged
4096-Point FFT Plot
LTC1854 Typical DNL Curve
0
5
185456 G06
MAGNITUDE (dB)
LTC1854 Typical INL Curve
0
CODE
8191
185456 G05
185455 G04
–0.2
10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 83dB
THD = –95dB
CODE
CODE
–1024
5
LTC1855 Nonaveraged
4096-Point FFT Plot
1
–4096
0
185456 G03
LTC1855 Typical DNL Curve
1
–1
–8192
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 87dB
THD = –101dB
185456 G02
185456 G01
INL (LSB)
32767
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
CODE
CODE
6
LTC1856 Nonaveraged
4096-Point FFT Plot
LTC1856 Typical DNL Curve
–1024
0
CODE
1024
2047
185456 G08
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 73.6dB
THD = –102dB
0
10
30
20
FREQUENCY (kHz)
40
50
185456 G09
185456fa
LTC1854/LTC1855/LTC1856
Typical Performance Characteristics
LTC1856 SINAD
vs Input Frequency
–70
TOTAL HARMONIC DISTORTION (dB)
88
SINAD (dB)
86
84
82
80
1.0
CHANNEL-TO-CHANNEL
OFFSET ERROR MATCHING (LSBs)
90
–80
–90
76
1
10
INPUT FREQUENCY (kHz)
–110
100
1
10
INPUT FREQUENCY (kHz)
LTC1855 SINAD
vs Input Frequency
70
65
10
INPUT FREQUENCY (kHz)
100
–70
–80
–90
–100
–110
1
10
INPUT FREQUENCY (kHz)
100
185456 G16
–25
0
25
50
TEMPERATURE (°C)
75
100
0.25
0.20
–70
–80
–90
–100
10
INPUT FREQUENCY (kHz)
–0.5
–50
185456 G15
CHANNEL-TO-CHANNEL OFFSET
ERROR MATCHING (LSB)
65
1
–0.25
LTC1854 Channel-to-Channel
Offset Error Matching vs
Temperature
–60
TOTAL HARMONIC DISTORTION (dB)
SINAD (dB)
100
0
LTC1854 Total Harmonic
Distortion vs Input Frequency
80
100
0.25
185456 G14
LTC1854 SINAD
vs Input Frequency
70
75
0.5
185456 G13
75
0
25
50
TEMPERATURE (°C)
185456 G12
CHANNEL-TO-CHANNEL
OFFSET ERROR MATCHING (LSBs)
TOTAL HARMONIC DISTORTION (dB)
SINAD (dB)
75
–25
LTC1855 Channel-to-Channel
Offset Error Matching vs
Temperature
–60
80
60
–1.0
–50
100
LTC1855 Total Harmonic
Distortion vs Input Frequency
85
1
0
185456 G11
185456 G10
60
0.5
–0.5
–100
78
74
LTC1856 Channel-to-Channel
Offset Error Matching vs
Temperature
LTC1856 Total Harmonic
Distortion vs Input Frequency
–110
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
1
10
INPUT FREQUENCY (kHz)
100
185456 G17
–0.25
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
185456 G18
1854565af
7
LTC1854/LTC1855/LTC1856
Typical Performance Characteristics
LTC1856 Channel-to-Channel Gain
Error Matching vs Temperature
LTC1854 Channel-to-Channel Gain
Error Matching vs Temperature
LTC1855 Channel-to-Channel Gain
Error Matching vs Temperature
0.25
0.5
1.0
0.5
0
–0.5
CHANNEL-TO-CHANNEL GAIN
ERROR MATCHING (LSB)
CHANNEL-TO-CHANNEL
GAIN ERROR MATCHING (LSBs)
CHANNEL-TO-CHANNEL
GAIN ERROR MATCHING (LSBs)
0.20
0.25
0
–0.25
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–1.0
–50
–25
0
25
50
TEMPERATURE (°C)
75
–0.5
–50
100
–25
0
25
50
TEMPERATURE (°C)
Internal Reference Voltage
vs Temperature
–10
2.505
2.500
2.495
2.490
2.485
–25
0
50
25
TEMPERATURE (°C)
75
100
POWER SUPPLY FEEDTHROUGH (dB)
CHANGE IN REFCOMP VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE (V)
2.510
0.02
0
–0.02
–0.04
–50
–40
–30
–20
–10
LOAD CURRENT (mA)
Supply Current vs Supply Voltage
POSITIVE SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
8.5
8.0
7.5
5
5.25
4.75
SUPPLY VOLTAGE (V)
5.5
185454 G25
75
100
10
fSAMPLE = 100kHz
VRIPPLE = 60mV
–30
–40
–50
–60
–70
–80
100
1k
10k
100k
RIPPLE FREQUENCY (Hz)
1M
185456 G24
Supply Current vs Temperature
9.0
fSAMPLE = 100kHz
7.0
4.5
0
–20
185456 G23
185456 G22
9.0
25
50
0
TEMPERATURE (°C)
LTC1856 Power Supply
Feedthrough vs Ripple Frequency
0.04
2.515
–25
185456 G21
Change in REFCOMP Voltage
vs Load Current
2.520
8
100
185456 G20
185456 G19
2.480
–50
75
–0.25
–50
fSAMPLE = 100kHz
8.5
8.0
7.5
7.0
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
185456 G26
185456fa
LTC1854/LTC1855/LTC1856
Pin Functions
COM (Pin 1): Common Input. This is the negative reference
point for all single-ended inputs. It must be free of noise
and is usually connected to the analog ground plane.
AGND1 (Pin 14): Analog Ground.
CH0 (Pin 2): Analog MUX Input.
REFCOMP (Pin 16): Reference Buffer Output. Bypass to
analog ground with a 10µF tantalum and a 0.1µF ceramic
capacitor. Nominal output voltage is 4.096V.
CH1 (Pin 3): Analog MUX Input.
CH2 (Pin 4): Analog MUX Input.
CH3 (Pin 5): Analog MUX Input.
CH4 (Pin 6): Analog MUX Input.
CH5 (Pin 7): Analog MUX Input.
CH6 (Pin 8): Analog MUX Input.
CH7 (Pin 9): Analog MUX Input.
MUXOUT + (Pin 10): Positive MUX Output. Output of the
analog multiplexer. Connect to ADC+ for normal operation.
MUXOUT – (Pin 11): Negative MUX Output. Output of the
analog multiplexer. Connect to ADC– for normal operation.
ADC + (Pin 12): Positive Analog Input to the Analog-toDigital Converter.
VREF (Pin 15): 2.5V Reference Output. Bypass to analog
ground with a 1µF tantalum capacitor.
AGND2 (Pin 17): Analog Ground.
AGND3 (Pin 18): Analog Ground. This is the substrate
connection.
AVDD (Pin 19): 5V Analog Supply. Bypass to analog ground
with a 0.1µF ceramic and a 10µF tantalum capacitor.
DVDD (Pin 20): 5V Digital Supply. Bypass to digital ground
with a 0.1µF ceramic and a 10µF tantalum capacitor.
OVDD (Pin 21): Positive Supply for the Digital Output
Buffers (3V to 5V). Bypass to digital ground with a 0.1µF
ceramic and a 10µF tantalum capacitor.
BUSY (Pin 22): Output shows converter status. It is low
when a conversion is in progress.
SDO (Pin 23): Serial Data Output.
ADC– (Pin 13): Negative Analog Input to the Analog-toDigital Converter.
1854565af
9
LTC1854/LTC1855/LTC1856
pin functions
RD (Pin 27): Read Input. This active low signal enables
the digital output pin SDO and enables the serial interface,
SDI and SCK are ignored when RD is high.
DGND (Pin 24): Digital Ground.
SDI (Pin 25): Serial Data Input.
SCK (Pin 26): Serial Data Clock.
CONVST (Pin 28): Conversion Start. The ADC starts a
conversion on CONVST’s rising edge.
functional block diagram
CH0
CH1
COM
DVDD
19
20
MUX ADDRESS
2
28
3
25
CONTROL
LOGIC
22
INTERNAL
CLOCK
•
•
•
CH7
AVDD
INPUT MUX
26
+
9
1
–
27
12-/14-/16-BIT
SAMPLING ADC
DATA OUT
21
SERIAL I/O
23
CONVST
SDI
BUSY
SCK
RD
OVDD
SDO
4.096V
2.5V
REFERENCE
8k
MUXOUT–
14
AGND1
MUXOUT+
11 10
ADC+
1.6384X
ADC–
12 13
15
VREF
16
REFCOMP
17
18
24
AGND2 AGND3 DGND
18545 BD
10
185456fa
LTC1854/LTC1855/LTC1856
test circuits
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
1k
1k
DN
DN
DN
1k
25pF
25pF
25pF
25pF
(A) VOH TO Hi-Z
(B) Hi-Z TO VOL AND VOH TO VOL
(A) Hi-Z TO VOH AND VOL TO VOH
DN
1k
(B) VOL TO Hi-Z
18545 TC02
18545 TC01
TIMING Diagrams
t2 (CONVST to BUSY Delay)
t2
t1 (For Short Pulse Mode)
CONVST
2.4V
t1
50%
50%
CONVST
BUSY
0.4V
18545 TD02
18545 TD01
t6 (Delay Time, SCK↓ to SDO Valid)
t7 (Time from Previous Data Remains Valid After SCK↓)
t6
t7
t3, t4, t5 (SCK Timing)
t4
SCK
t5
0.4V
SCK
t3
2.4V
0.4V
SDO
18545 TD03
18545 TD04
t9 (RD↓ to SCK Setup Time)
t8 (SDO Valid After RD↓)
t8
RD
SDO
t9
RD
0.4V
Hi-Z
2.4V
0.4V
SCK
18545 TD05
0.4V
2.4V
18545 TD06
1854565af
11
LTC1854/LTC1855/LTC1856
timing diagrams
t11 (SDI Hold Time After SCK↑)
t10 (SDI Setup Time Before SCK↑)
t11
t10
2.4V
SCK
SDI
2.4V
SCK
2.4V
0.4V
2.4V
0.4V
SDI
18545 TD08
18545 TD07
t13 (BUS Relinquish Time)
t12 (SDO Valid Before BUSY↑, RD = 0)
t13
t12
2.4V
BUSY
SDO
2.4V
RD
SDO
B15
2.4V
90%
10%
Hi-Z
18545 TD10
18545 TD09
12
185456fa
LTC1854/LTC1855/LTC1856
Applications Information
Overview
The LTC1854/LTC1855/LTC1856 are innovative, multichannel ADCs. The on-chip resistors provide attenuation
and offset for each channel. The precisely trimmed attenuators ensure an accurate input range. Because they precede
the multiplexer, errors due to multiplexer on-resistance
are eliminated.
The input word selects the single ended or differential
inputs for each channel or pair of channels. Overrange
protection is provided for unselected channels. An overrange condition on an unused channel will not affect the
conversion result on the selected channel.
Conversion Details
The LTC1854/LTC1855/LTC1856 use a successive approximation algorithm and an internal sample-and-hold
circuit to convert an analog signal to a 12-/14-/16-bit serial
output respectively. The ADCs are complete with a precision
reference and an internal clock. The control logic provides
easy interface to microprocessors and DSPs. (Please refer
to the Digital Interface section for the data format.)
The analog signals applied at the MUX input channels are
rescaled by the resistor divider network formed by R1, R2
and R3 as shown below. The rescaled signals appear on
the MUXOUT (Pins 10, 11) which are also connected to
the ADC inputs (Pins 12, 13) under normal operation.
REFCOMP
MUX
INPUT
R1
25k
R3
10k
CH SEL
MUXOUT
R2
17k
185456 AI01
Before starting a conversion, an 8-bit data word is clocked
into the SDI input on the first eight rising SCK edges to
select the MUX address and power down mode. The ADC
enters acquisition mode on the falling edge of the sixth
clock in the 8-bit data word and ends on the rising edge
of the CONVST signal which also starts a conversion (see
Figure 7). A minimum time of 4µs will provide enough time
for the sample-and-hold capacitors to acquire the analog
signal. Once a conversion cycle has begun, it cannot be
restarted.
During the conversion, the internal differential 12-/14-/16bit capacitive DAC output is sequenced by the SAR from
the most significant bit (MSB) to the least significant bit
(LSB). The input is successively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a high speed comparator. At
the end of a conversion, the DAC output balances the analog
input (ADC + – ADC–). The SAR contents (a 12-/14-/16-bit
data word) which represents the difference of ADC+ and
ADC– are loaded into the 12-/14-/16-bit shift register.
Driving the Analog Inputs
The input range for the LTC1854/LTC1855/LTC1856 is
±10V and the MUX inputs are overvoltage protected to
± 30V. The input impedance is typically 31kΩ; therefore, it
should be driven with a low impedance source. Wideband
noise coupling into the input can be minimized by placing
a 3000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If
an amplifier is to be used to drive the input, care should
be taken to select an amplifier with adequate accuracy,
linearity and noise for the application. The following list is
a summary of the op amps that are suitable for driving the
LTC1854/LTC1855/LTC1856. More detailed information is
available in the Linear Technology data books and online
at www.linear.com.
LT®1007: Low noise precision amplifier. 2.7mA supply
current ±5V to ±15V supplies. Gain bandwidth product
8MHz. DC applications.
1854565af
13
LTC1854/LTC1855/LTC1856
applications information
AVDD
DVDD
MUX ADDRESS
CH0
CONVST
CONTROL
LOGIC
CH1
SDI
INTERNAL
CLOCK
•
•
•
BUSY
INPUT MUX
SCK
+
CH7
–
COM
12-/14-/16-BIT
SAMPLING ADC
RD
DATA OUT
SERIAL I/O
OVDD
SDO
4.096V
2.5V
REFERENCE
8k
MUXOUT–
MUXOUT+
AGND1
ADC+
1.6384X
ADC–
18545 F01
VREF
REFCOMP
AGND2 AGND3 DGND
Figure 1. LTC1854/LTC1855/LTC1856 Simplified Equivalent Circuit
AIN+
AIN–
LT1792: Single, low noise JFET input op amp, ±5V supplies.
CH0
3000pF
CH1
•
•
•
•
MUXOUT+
MUXOUT–
ADC+
ADC–
18545 F02
Figure 2. Analog Input Filtering
LT1227: 140MHz video current feedback amplifier. 10mA
supply current. ±5V to ±15V supplies. Low noise and low
distortion.
LT1468/LT1469: Single and dual 90MHz, 16-bit accurate
op amp. Good AC/DC specs. ±5V to ±15V supplies.
LT1677: Single, low noise op amp. Rail-to-rail input and
output. Up to ±15V supplies.
14
LT1793: Single, low noise JFET input op amp, 10pA bias
current, ±5V supplies.
LT1881/LT1882: Dual and quad, 200pA bias current, railto-rail output op amps. Up to ±15V supplies.
LT1844/LT1885: Dual and quad, 400pA bias current,
rail-to-rail output op amps. Up to ±15V supplies. Faster
response and settling time.
Internal Voltage Reference
The LTC1854/LTC1855/LTC1856 have an on-chip, temperature compensated, curvature corrected, bandgap
reference, which is factory trimmed to 2.50V. The full-scale
range of the LTC1854/LTC1855/LTC1856 is equal to ±10V.
The output of the reference is connected to the input of a
gain of 1.6384x buffer through an 8k resistor (see Figure
3). The input to the buffer or the output of the reference
185456fa
LTC1854/LTC1855/LTC1856
Applications Information
is available at VREF (Pin 15). The internal reference can be
overdriven with an external reference if more accuracy is
needed. The buffer output drives the internal DAC and is
available at REFCOMP (Pin 16). The REFCOMP pin can be
used to drive a steady DC load of less than 2mA. Driving
an AC load is not recommended because it can cause the
performance of the converter to degrade.
15 VREF
2.5V
8k
1µF
2.5V
REFERENCE
12-/14-/16-BIT
CAPACITIVE DAC
1.6384X BUFFER
16 REFCOMP
4.096V
0.1µF
18545 F03
10µF
Figure 3. Internal or External Reference Source
For minimum code transition noise the VREF pin and the
REFCOMP pin should each be decoupled with a capacitor to
filter wideband noise from the reference and the buffer.
FULL SCALE AND OFFSET
Figure 4 shows the ideal input/output characteristics for
the LTC1856. The code transitions occur midway be-
1 LSB =
FS − ( − FS) 20V
=
= 305.2µV
65566
65536
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero during a
calibration sequence. Offset error must be adjusted before
full-scale error. Zero offset is achieved by adjusting the
offset applied to the “–” input. For single-ended inputs, this
offset should be applied to the COM pin. For differential
inputs, the “–” input is dictated by the MUX address.
For zero offset error, apply – 0.5LSB to the “+” input and
adjust the offset at the “–” input until the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 for the LTC1856, between 00 0000 0000 0000 and
11 1111 1111 1111 for the LTC1855 and between 0000
0000 0000 and 1111 1111 1111 for the LTC1854.
For full-scale adjustment, an input voltage of FS – 1.5LSBs
should be applied to the “+” input and the appropriate
reference adjusted until the output code flickers between
0111 1111 1111 1110 and 0111 1111 1111 1111 for the
LTC1856, between 01 1111 1111 1110 and 01 1111 1111
1111 for the LTC1855 and between 0111 1111 1110 and
0111 1111 1111 for the LTC1854.
These adjustments as well as the factory trims affect all
channels. The channel-to-channel offset and gain error
matching are guaranteed by design to meet the specifications in the Converter Characteristics table.
011...111
011...110
OUTPUT CODE
tween successive integer LSB values (i.e., –FS+0.5LSB,
–FS+1.5LSB, –FS+2.5LSB, … FS–1.5LSB, FS–0.5LSB).
The output is two’s complement binary with:
000...001
000...000
111...111
111...110
100...001
100...000
FS – 1LSB
–(FS – 1LSB)
INPUT VOLTAGE (V)
185456 F04
Figure 4. Bipolar Transfer Characteristics
1854565af
15
LTC1854/LTC1855/LTC1856
applications information
DC Performance
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where
a DC signal is applied to the input of the MUX and the
resulting output codes are collected over a large number
of conversions. For example in Figure 5 the distribution
of output code is shown for a DC input that has been
digitized 4096 times. The distribution is Gaussian and the
RMS code transition is about 1LSB for the LTC1856.
Digital Interface
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 4µs. No external adjustments
are required and, with the maximum acquisition time of
4µs, throughput performance of 100ksps is assured.
3V Input/Output Compatible
The LTC1854/LTC1855/LTC1856 operate on a 5V supply,
which makes the devices easy to interface to 5V digital
systems. These devices can also interface to 3V digital
systems: the digital input pins (SCK, SDI, CONVST and
RD) of the LTC1854/LTC1855/LTC1856 recognize 3V or 5V
inputs. The LTC1854/LTC1855/LTC1856 have a dedicated
output supply pin (OVDD) that controls the output swings
of the digital output pins (SDO, BUSY) and allows the part
to interface to either 3V or 5V digital systems. The SDO
output is two’s complement.
Timing and Control
Conversion start and data read are controlled by two digital
inputs: CONVST and RD. To start a conversion and put the
sample-and-hold into the hold mode bring CONVST high
for at least 40ns. Once initiated it cannot be restarted until
the conversion is complete. Converter status is indicated
by the BUSY output, which goes low while the conversion
is in progress.
Figures 6a and 6b show two different modes of operation for the LTC1856. For the 12-bit LTC1854 and 14-bit
LTC1855, the last four and two bits of the SDO will output
zeros, respectively. In mode 1 (Figure 6a), RD is tied low.
The rising edge of CONVST starts the conversion. The data
outputs are always enabled. The MSB of the data output
is available after the conversion. In mode 2 (Figure 6b),
CONVST and RD are tied together. The rising edge of the
CONVST signal starts the conversion. Data outputs are in
three-state at this time. When the conversion is complete
(BUSY goes high), CONVST and RD go low to enable the
data output for the previous conversion.
1800
1600
1400
COUNT
1200
1000
800
600
400
200
0
–4
–3
–2
–1
1
0
CODE
2
3
4
185456 F05
Figure 5. LTC1856 Histogram for 4096 Conversions
16
185456fa
Hi-Z
DON’T
CARE
Hi-Z
DON’T
CARE
DON’T
CARE
SGL/
DIFF
t4
1
SGL/
DIFF
t4
1
t8
SELECT
1
3
SELECT
0
4
X
5
B12
B11
B14
B10
X
6
B9
t7
t6
NAP
7
B8
SLEEP
8
tACQ
B1
DON’T CARE
15
B0
16
t2
t1
tCONV
t12
B15 (MSB)
SGL/
DIFF
1
B14
ODD/
SIGN
2
SELECT
0
4
X
5
X
6
NAP
7
SLEEP
8
B13
B12
B11
B10
B9
B8
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
SELECT
1
3
SELECT
1
3
SELECT
0
4
B13
B12
B11
X
5
B10
X
6
B9
t7
t6
NAP
7
B8
SLEEP
8
tACQ
B1
DON’T CARE
15
B0
16
t2
Hi-Z
tCONV
t13
B15 (MSB)
SGL/
DIFF
1
B14
ODD/
SIGN
2
SELECT
0
4
X
5
X
6
NAP
7
SLEEP
8
B13
B12
B11
B10
B9
B8
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
SELECT
1
3
Figure 6a. Mode 1 for the LTC1856*. CONVST Starts a Conversion, Data Output is Always Enabled (RD = 0)
B13
SHIFT CONFIGURATION WORD IN
ODD/
SIGN
t11
2
B14
SHIFT CONFIGURATION WORD IN
ODD/
SIGN
t11
2
SELECT
1
3
SELECT
0
4
X
5
B14
B13
B12
B11
SHIFT CONFIGURATION WORD IN
ODD/
SIGN
t11
2
B10
X
6
B9
t7
t6
NAP
7
B8
SLEEP
8
tACQ
B0
16
t2
Hi-Z
tCONV
t1
B15 (MSB)
SGL/
DIFF
1
B14
ODD/
SIGN
2
Figure 7. Operating Sequence for the LTC1856*
B1
DON’T CARE
15
t13
SELECT
0
4
X
5
X
6
NAP
7
SLEEP
8
B13
B12
B11
B10
B9
B8
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
SELECT
1
3
Figure 6b. Mode 2 for the LTC1856*. CONVST and RD Tied Together. CONVST Starts a Conversion, Data is Read by RD
t5
t10
t3
B15 (MSB)
t9
t8
t5
t10
t3
B15 (MSB)
t9
t12
B15 (MSB)
t5
t10
t3
SGL/
DIFF
t4
1
*For the 12-bit LTC1854 and the LTC1855 the last four and two bits of the SDO will output zeros, respectively.
BUSY
CONVST
SDO
SDI
SCK
RD
BUSY
SDO
SDI
SCK
CONVST = RD
BUSY
CONVST
SDO
SDI
SCK
RD = 0
16
B1
15
B1
B0
DON’T CARE
16
B0
DON’T CARE
16
B0
DON’T CARE
15
B1
15
185456 F07
Hi-Z
185456 F06b
Hi-Z
18545 F06a
LTC1854/LTC1855/LTC1856
Applications Information
17
1854565af
LTC1854/LTC1855/LTC1856
applications information
Serial DATA INPUT (sdi) Interface
conversion is delayed by one conversion from the input
word requesting it.
The LTC1854/LTC1855/LTC1856 communicate with microprocessors and other external circuitry via a synchronous,
full duplex, 3‑wire serial interface (see Figure 7). The shift
clock (SCK) synchronizes the data transfer with each bit
being transmitted on the falling SCK edge and captured
on the rising SCK edge in both transmitting and receiving
systems. The data is transmitted and received simultaneously (full duplex).
SDI
SDI WORD 1
SDI WORD 2
SDI WORD 3
SDO
SDO WORD 0
SDO WORD 1
SDO WORD 2
tCONV
A/D
CONVERSION
DATA
TRANSFER
DATA
TRANSFER
185456 AI02
tCONV
A/D
CONVERSION
Input Data Word
An 8-bit input word is shifted into the SDI input which
configures the LTC1854/LTC1855/LTC1856 for the next
conversion. Simultaneously, the result of the previous
conversion is output on the SDO line. At the end of the
data exchange the requested conversion begins by applying a rising edge on CONVST. After tCONV, the conversion is complete and the results will be available on the
next data transfer cycle. As shown below, the result of a
The LTC1854/LTC1855/LTC1856 8-bit data word is clocked
into the SDI input on the first eight rising SCK edges. Further inputs on the SDI pin are then ignored until the next
conversion. The eight bits of the input word are defined
as follows:
SGL/
DIFF
ODD
SIGN
SELECT
1
SELECT
0
DON'T
CARE
DON'T
CARE
NAP
SLEEP
POWER DOWN
SELECTION
MUX ADDRESS
185456 AI03
Table 1. Multiplexer Channel Selection
MUX ADDRESS
SGL/
DIFF
DIFFERENTIAL CHANNEL SELECTION
ODD SELECT
SIGN 1 0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
+
–
2
+
0,1
{
2,3
{
4,5
{
6,7
{
+ (–)
– (+)
+ (–)
– (+)
+ (–)
– (+)
+ (–)
– (+)
4
5
6
7
–
+
–
–
+
–
+
–
+
–
8 Single-Ended
CHANNEL
0
1
2
3
4
5
6
7
+
+
+
+
+
+
+
+
COM (–)
SINGLE-ENDED CHANNEL SELECTION
SGL/ ODD SELECT
DIFF SIGN 1 0
–
+
4 Differential
CHANNEL
3
MUX ADDRESS
+
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
0,1
{
+
–
2,3
{
–
+
+
+
+
+
4
5
6
7
COM (–)
3
4
5
6
7
COM
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
Combinations of
Differential and Single-Ended
CHANNEL
2
–
Changing the
MUX Assignment “On the Fly”
4,5
{
6,7
{
+
–
+
–
COM (UNUSED)
1ST CONVERSION
4,5
{
–
+
6
7
+
+
COM (–)
2ND CONVERSION
18545 F08
Figure 8. Examples of Multiplexer Options on the LTC1854/LTC1855/LTC1856
18
185456fa
LTC1854/LTC1855/LTC1856
Applications Information
MUX Address
The first four bits of the input word assign the MUX
configuration for the requested conversion. For a given
channel selection, the converter will measure the voltage
between the two channels indicated by the + and – signs in
the selected row of Table 1. Note that in differential mode
(SGL/DIFF = 0) measurements are limited to four adjacent
input pairs with either polarity. In single-ended mode, all
input channels are measured with respect to COM. Both
the “+” and “–” inputs are sampled simultaneously so
common mode noise is rejected. Bits 5 and 6 of the input
words are Don’t Care bits.
Power Down Selection (NAP, SLEEP)
The last two bits of the input word (Nap and Sleep) determine the power shutdown mode of the LTC1854/LTC1855/
LTC1856. See Table 2. Nap mode is selected when Nap =
1 and Sleep = 0. The previous conversion result will be
clocked out and a conversion will occur before entering
the Nap mode. The Nap mode starts at the end of the
conversion which is indicated by the rising edge of the
BUSY signal. Nap mode lasts until the falling edge of the
2nd SCK (see Figure 9). Automatic nap will be achieved
if Nap = 1 is selected each time an input word is written
to the ADC.
Table 2. Power Down Selection
NAP
SLEEP
POWER DOWN MODE
0
0
Power On
1
0
Nap
X
1
Sleep
Sleep mode will occur when Sleep = 1 is selected,
regardless of the selection of the Nap input. The previous conversion result can be clocked out and the Sleep
mode will start on the falling edge of the last (16th) SCK.
Notice that the CONVST should stay either high or low in
sleep mode (see Figure 10). To wake up from the sleep
mode, apply a rising edge on the CONVST signal and
then apply Sleep = 0 on the next SDI word and the part
will wake up on the falling edge of the last (16th) SCK
(see Figure 11).
In Sleep mode, all bias currents are shut down and only the
power on reset circuit and leakage currents (about 10µA)
remain. Sleep mode wake-up time is dependent on the value
of the capacitor connected to the REFCOMP (Pin 16). The
wake-up time is typically 40ms with the recommended
10µF capacitor connected on the REFCOMP pin.
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental. Figure 12 shows
a typical LTC1856 FFT plot which yields a SINAD of 87dB
and THD of – 101dB.
1854565af
19
20
Hi-Z
DON’T
CARE
tCONV
DON’T
CARE
tCONV
DON’T
CARE
B15 (MSB)
SGL/
DIFF
1
SGL/
DIFF
1
B15 (MSB)
SGL/
DIFF
1
3
SELECT
0
4
X
5
X
6
B13
B14
ODD/
SIGN
2
B14
ODD/
SIGN
2
SELECT
0
4
B10
X
5
B9
X
6
B8
B11
B10
B9
A/D RESULT FROM PREVIOUS CONVERSION
B12
NAP
7
SELECT
1
3
SELECT
0
4
X
5
X
6
B13
B12
B11
SLEEP
A/D RESULT NOT VALID
B10
NAP
B15 MSB
SELECT
1
3
B8
SLEEP = 1
8
B1
DON’T CARE
15
B0
16
B8
SLEEP = 0
8
B1
DON’T CARE
15
B0
16
WAKE-UP
TIME
READY
tCONV
SELECT
0
4
X
5
X
6
NAP
7
SLEEP
8
15
B14
B13
B15 (MSB)
SGL/
DIFF
1
B14
ODD/
SIGN
2
B12
SELECT
0
4
B10
X
5
B9
X
6
B8
NAP
7
SLEEP
8
tACQ
B1
B13
B12
B11
B10
B9
B8
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
SELECT
1
3
SLEEP
B11
16
B0
DON’T CARE
SHIFT A/D RESULT OUT FROM PREVIOUS CONVERSION AND NEW CONFIGURATION WORD IN
ODD/
SIGN
2
Figure 11. Wake Up from Sleep Mode for the LTC1856*
B9
tCONV
Hi-Z
SGL/
DIFF
1
Figure 10. Sleep Mode Operation for the LTC1856*
NAP
7
B0
16
Figure 9. Nap Mode Operation for the LTC1856*
tACQ
B1
DON’T CARE
15
CONVST SHOULD STAY EITHER HIGH OR LOW IN SLEEP MODE
B13
SHIFT SLEEP CONFIGURATION WORD IN
SELECT
1
3
B11
8
NAP = 1 SLEEP = 0
7
SHIFT WAKE-UP CONFIGURATION WORD IN
B12
SHIFT CONFIGURATION WORD IN
SELECT
1
B15 (MSB)
B14
ODD/
SIGN
2
*For the 12-bit LTC1854 and the LTC1855 the last four and two bits of the SDO will output zeros, respectively.
BUSY
CONVST
SDO
SDI
SCK
RD
BUSY
CONVST
SDO
SDI
SCK
RD
BUSY
CONVST
SDO
SDI
SCK
RD
16
B1
B0
DON’T CARE
15
18545 F10
18545 F11
18545 F09
Hi-Z
LTC1854/LTC1855/LTC1856
applications information
185456fa
LTC1854/LTC1855/LTC1856
Applications Information
Signal-to-Noise AND DISTORTION Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 12 shows a typical SINAD of 87dB with
a 100kHz sampling rate and a 1kHz input.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = 20log
V2 2 + V3 2 + V4 2 ... + VN 2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through Nth harmonics.
MAGNITUDE (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
Board Layout, Power Supplies
and Decoupling
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1854/LTC1855/LTC1856, a
printed circuit board is required. Layout for the printed
circuit board should ensure the digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by AGND.
In applications where the MUX is connected to the ADC, it is
possible to get noise coupling into the ADC from the trace
connecting the MUXOUT to the ADC. Therefore, reducing
the length of the traces connecting the MUXOUT pins (Pins
10, 11) to the ADC pins (Pins 12, 13) can minimize the
problem. The unused MUX inputs should be grounded to
prevent noise coupling into the inputs.
Figure 13 shows the power supply grounding that will help
obtain the best performance from the 12-bit/14-bit/16-bit
ADCs. Pay particular attention to the design of the analog
and digital ground planes. The DGND pin of the LTC1854/
fSAMPLE = 100kHz
fIN = 1kHz
SINAD = 87dB
THD = –101dB
0
5
10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
185456 F12
Figure 12. LTC1856 Nonaveraged 4096 Point FFT Plot
1854565af
21
LTC1854/LTC1855/LTC1856
applications information
LTC1855/LTC1856 can be tied to the analog ground plane.
Placing the bypass capacitor as close as possible to the
power supply pins, the reference and reference buffer output is very important. Low impedance common returns for
these bypass capacitors are essential to low noise operation
of the ADC, and the foil width for these tracks should be
as wide as possible. Also, since any potential difference in
+
–
grounds between the signal source and ADC appears as
an error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedance
as much as possible. The digital output latches and the
onboard sampling clock have been placed on the digital
ground plane. The two ground planes are tied together at
the ADC through a wide, low inductance path.
LTC1854/
LTC1855/
CH0 LTC1856
10 12
CH1
MUXOUT+
ADC+
CH2
LTC1854/LTC1855/LTC1856
CH3
–
–
CH4
ADC
MUXOUT
VREF
REFCOMP AGND
AVDD
DVDD
DGND
11 13
CH5
CH6
15
16
14, 17, 18 19
20
24
CH7
10µF
10µF
10µF
1 µF
COM
ANALOG GROUND PLANE
DIGITAL
SYSTEM
OVDD
21
10µF
DIGITAL
GROUND PLANE
18545 F13
Figure 13. Power Supply Grounding Practice
22
185456fa
LTC1854/LTC1855/LTC1856
Package Description
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
0.42 ±0.03
7.40 – 8.20
(.291 – .323)
0.65 BSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
TYP
0.05
(.002)
MIN
G28 SSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1854565af
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1854/LTC1855/LTC1856
Typical Application
5V
5V
10µF
0.1µF
10µF
19
DVDD
AVDD
1 COM
CONVST 28
MUX ADDRESS
2 CH0
SINGLE-ENDED
OR DIFFERENTIAL
CHANNEL
SELECTION
(SEE TABLE 1)
INPUT RANGE:
±10V
SDI 25
CONTROL
LOGIC
3 CH1
BUSY 22
INTERNAL
CLOCK
•
•
•
0.1µF
20
INPUT MUX
SCK 26
16 SHIFT CLOCK CYCLES
+
9 CH7
12-/14-/16-BIT
SAMPLING ADC
–
RD 27
DATA OUT
OVDD 21
SERIAL I/O
10µF
4.096V
16-BIT SERIAL DATA OUT
1.6384X
8k
MUXOUT–
14
MUXOUT+
11
ADC+
10
12
ADC–
VREF
13
15
3V TO 5V
0.1µF
SDO 23
2.5V
REFERENCE
AGND1
8-BIT SERIAL
DATA INPUT
AGND2 AGND3 DGND
REFCOMP
16
1µF
10µF
17
18
18545 TA03
24
0.1µF
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
14-Bit, 200ksps, Single 5V or ±5V ADC
15mW, Serial/Parallel I/O
Sampling ADCs
LTC1418
LTC1604
16-Bit, 333ksps, ± 5V ADC
90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608
LTC1605
16-Bit, 100ksps, Single 5V ADC
±10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606
LTC1606
16-Bit, 250ksps, Single 5V ADC
±10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605
LTC1608
16-Bit, 500ksps, ±5V ADC
90dB SINAD, 270mW Power Dissipation, Pin Compatible with LTC1604
LTC1609
16-Bit, 200ksps Serial ADC
Configurable Unipolar/Bipolar Input, Up to 10V Single 5V Supply
LTC1850/LTC1851
10-Bit/12-Bit, 8-Channel, 1.25Msps ADC
Programmable MUX and Sequencer, Parallel I/O
LTC1859/LTC1858/
LTC1857
16-Bit, 14-Bit, 12-Bit, 100ksps, SoftSpan ADCs
Software-Selectable Spans, Pin Compatible with
LTC1864/LTC1865
16-Bit, 1-/2-Channel, 250ksps ADC in MSOP
Single 5V Supply, 850µA with Autoshutdown
LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP
Single 3V Supply, 450µA with Autoshutdown
LTC1856/LTC1855/LTC1854
DACs
LTC1588/LTC1589
LTC1592
12-/14-/16-Bit, Serial, SoftSpan IOUT DACs
Software-Selectable Spans, ±1LSB INL/DNL
LTC1595
16-Bit Serial Multiplying IOUT DAC in SO-8
± 1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
LTC1596
16-Bit Serial Multiplying IOUT DAC
±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade
LTC1597
16-Bit Parallel, Multiplying DAC
±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors
LTC1650
16-Bit Serial VOUT ±5V DAC
Low Power, Low Glitch, 4-Quadrant Multiplication
LTC2704-16/
LTC2704-14/
LTC2704-12
16-Bit, 14-Bit, 12-Bit, Serial, Quad SoftSpan
VOUT DACs
Software-Selectable Spans, ±2LSB INL, ±1LSB INL,
Force/Sense Output
24 Linear Technology Corporation
185456fa
LT 0407 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2006