IDT IDT71V633S11PF 64k x 32 3.3v synchronous sram flow-through outputs burst counter, single cycle deselect Datasheet

64K x 32
3.3V Synchronous SRAM
Flow-Through Outputs
Burst Counter, Single Cycle Deselect
IDT71V633
Features
◆
◆
◆
◆
◆
◆
◆
◆
64K x 32 memory configuration
Supports high performance system speed
Commercial:
— 11 11ns Clock-to-Data Access (50 MHz)
Commercial and Industrial:
— 12 12ns Clock-to-Data Access (50 MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC64K32B2LG-XX)
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
tecture provides cost-effective 2-1-1-1 performance for processors up to
50 MHz.
The IDT71V633 SRAM contains write, data-input, address and control
registers. There are no registers in the data output path (flow-through
architecture). Internal logic allows the SRAM to generate a self-timed write
based upon a decision which can be left until the extreme end of the write
cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V633 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses will be
defined by the internal burst counter and the LBO input pin.
The IDT71V633 SRAM utilizes IDT's high-performance 3.3V CMOS
process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin
thin plastic quad flatpack (TQFP).
Description
The IDT71V633 is a 3.3V high-speed 2,097,152-bit (2-Mbit) SRAM
organized as 64K x 32 with full support of various processor interfaces
including the Pentium™ and PowerPC™. The flow-through burst archi-
Pin Description
A0–A15
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS0, CS1
Chips Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW1–BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock Input
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O0–I/O31
Data Input/Output
I/O
Synchronous
VDD, VDDQ
Core and I/O Power Supply (3.3V)
Power
N/A
VSS, VSSQ
Array Ground, I/O Ground
Power
N/A
3780 tbl 01
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
AUGUST 2001
1
©2000 Integrated Device Technology, Inc.
DSC-3780/05
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
A0–A15
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of
the rising edge of CLK and ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input
that is used to load the address registers with new addresses. ADSC is NOT gated
by CE.
ADSP
Address Status (Processor)
I
LOW
Synchronous Address Status from Processor. ADSP is an active LOW input that is
used to load the address registers with new addresses. ADSP is gated by CE.
ADV
Burst Address Advance
I
LOW
Synchronous Address Advance. ADV is an active LOW input that is used to advance
the internal burst counter, controlling burst access after the initial address is loaded.
When this input is HIGH the burst counter is not incremented; that is, there is no
address advance.
BWE
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1–BW4. If BWE is
LOW at the rising edge of CLK then BWX inputs are passed to the next stage in
the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of
CLK. If ADSP is HIGH and BWX is LOW at the rising edge of CLK then data will
be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked
and only GW can initiate a write cycle.
Individual Byte Write
Enables
I
LOW
Synchronous byte write enables. BW1 controls I/O(7:0), BW2 controls I/O(15:8), etc.
Any active byte write causes all outputs to be disabled. ADSP LOW disables all byte
writes. BW1–BW4 must meet specified setup and hold tim es with respect to CLK.
CE
Chip Enable
I
LOW
Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V633.
CE also gates ADSP.
CLK
Clock
I
N/A
This is the clock input. All timing references for the device are made with respect
to this input.
CS0
Chip Select 0
I
HIGH
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the
chip.
CS1
Chip Select 1
I
LOW
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the
chip.
GW
Global Write Enable
I
LOW
Synchronous global write enable. This input will write all four 8-bit data bytes when
LOW on the rising edge of CLK. GW supercedes individual byte write enables.
I/O0–I/O31
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. Only the data input path is registered and
triggered by the rising edge of CLK. Outputs are Flow-Through.
LBO
Linear Burst
I
LOW
When LBO is HIGH the Interleaved Order (Intel) burst sequence is selected. When
LBO is LOW the Linear (PowerPC) burst sequence is selected. LBO has an internal
pull-up resistor.
OE
Output Enable
I
LOW
Asynchronous output enable. When OE is HIGH the I/O pins are in a high-impedence
state. When OE is LOW the data output drivers are enabled if the chip is also
selected.
VDD
Power Supply
N/A
N/A
3.3V core power supply inputs.
VDDQ
Power Supply
N/A
N/A
3.3V I/O power supply inputs.
VSS
Ground
N/A
N/A
Core ground pins.
VSSQ
Ground
N/A
N/A
I/O ground pins.
NC
No Connect
N/A
N/A
NC pins are not electrically connected to the chip.
ZZ
Sleep Mode
I
HIGH
BW1–BW4
Description
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power
down the IDT71V633 to its lowest pow er consumption level. Data retention is
guaranteed in Sleep Mode. ZZ has an internal pull-down resistor.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
2
3780 tbl 02
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
ADV
CLK
2
Binary
Counter
ADSC
INTERNAL
ADDRESS
Burst
Sequence
CE
Burst
Logic
Q0
CLR
ADSP
Q1
CLK EN
ADDRESS
REGISTER
A0–A15
GW
BWE
2
A0, A1
64K x 32
BIT
MEMORY
ARRAY
16
A0*
A1*
A2–A15
32
32
16
Byte 1
Write Register
Byte 1
Write Driver
BW1
8
Byte 2
Write Register
Byte 2
Write Driver
BW2
8
Byte 3
Write Register
Byte 3
Write Driver
BW3
8
Byte 4
Write Register
Byte 4
Write Driver
BW4
8
CE
D
CS0
CS1
Q
Enable
Register
DATA INPUT
REGISTER
CLK EN
ZZ
Powerdown
OE
OE
OUTPUT
BUFFER
32
I/O0–I/O31
3780 drw 01
3
6.42
.
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Absolute Maximum DC Ratings(1)
Symbol
Value
Unit
Terminal Voltage with
Respect to GND
–0.5 to +4.6
V
Terminal Voltage with
Respect to GND
–0.5 to VDD+0.5
TA
Operating Temperature
0 to +70
o
TBIAS
Temperature Under Bias
–55 to +125
o
–55 to +125
o
VTERM (2)
VTERM
(3)
Rating
Recommended Operating
Temperature and Supply Voltage
V
Grade
Temperature
VSS
VDD
VDDQ
Commercial
0°C to +70°C
0V
3.3V+10/-5%
3.3V+10/-5%
Industrial
–40°C to +85°C
0V
3.3V+10/-5%
3.3V+10/-5%
3780 tbl 03
TSTG
Storage Temperature
C
C
Recommended DC Operating
Conditions
C
PT
Power Dissipation
1.2
W
IOUT
DC Output Current
50
mA
Symbol
3780 tbl 05
VDD
VDDQ
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD, VDDQ and input terminals only.
3. I/O terminals.
VIH
VIL
CIN
Input Capacitance
CI/O
I/O Capacitance
Conditions
Max.
Unit
VIN = 3dV
4
pF
VOUT = 3dV
8
Typ.
Max.
Unit
Core Supply Voltage
3.135
3.3
3.63
V
I/O Supply Voltage
3.135
3.3
3.63
V
0
0
Input High Voltage
Input Low Voltage
0
2.0
(1)
–0.5
(3)
____
____
VDDQ+0.3
V
(2)
0.8
V
V
3780 tbl 04
NOTES:
1. VIH and VIL as indicated is for both input and I/O pins.
2. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.
3. VIL (min) = –1.0V for pulse width less than tCYC/2, once per cycle.
(TA = +25°C, f = 1.0MHz, TQFP package)
Parameter(1)
Min.
VSS, VSSQ Ground
Capacitance
Symbol
Parameter
pF
3780 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
4
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
A6
A7
CE
CS0
BW4
BW3
BW2
BW1
CS1
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configuration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
I/O16
I/O17
VDDQ
VSSQ
I/O18
I/O19
I/O20
I/O21
VSSQ
VDDQ
I/O22
I/O23
VSS(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSSQ
I/O26
I/O27
I/O28
I/O29
VSSQ
VDDQ
I/O30
I/O31
NC
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
71
10
11
70
12
69
13
68
14
67
15
PK100-1
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
NC
I/O15
I/O14
VDDQ
VSSQ
I/O13
I/O12
I/O11
I/O10
VSSQ
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ(2)
I/O7
I/O6
VDDQ
VSSQ
I/O5
I/O4
I/O3
I/O2
VSSQ
VDDQ
I/O1
I/O0
NC
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Top View TQFP
NOTES
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is ≤ VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
5
6.42
3780 drw 02
.
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1, 2)
Address
Used
CE
CS0
CS 1
ADSP
ADSC
ADV
GW
BWE
BWX
OE (3)
CLK
I/O
Deselected Cycle, Power Down
None
H
X
X
X
L
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
X
H
L
X
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
L
X
L
X
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
X
H
X
L
X
X
X
X
X
↑
Hi-Z
Deselected Cycle, Power Down
None
L
L
X
X
L
X
X
X
X
X
↑
Hi-Z
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
H
↑
Hi-Z
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
H
X
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
H
↑
Hi-Z
Write Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L
X
↑
DIN
Write Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
X
X
↑
DIN
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
L
↑
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
H
↑
Hi-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
L
↑
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
H
↑
Hi-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
L
↑
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
H
↑
Hi-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
L
↑
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
H
↑
Hi-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L
X
↑
DIN
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
X
X
↑
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L
X
↑
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
X
X
↑
DIN
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
L
↑
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
H
↑
Hi-Z
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
L
↑
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
H
↑
Hi-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
L
↑
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
H
↑
Hi-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
L
↑
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
H
↑
Hi-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L
X
↑
DIN
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
X
X
↑
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L
X
↑
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
X
X
↑
Operation
DIN
3780 tbl 07
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. ZZ = LOW for this table.
3. OE is an asynchronous input.
6
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1)
GW
BWE
BW1
BW2
BW3
BW4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
Write Byte 1
(2)
H
L
L
H
H
H
Write Byte 2
(2)
H
L
H
L
H
H
Write Byte 3
(2)
H
L
H
H
L
H
Write Byte 4
(2)
H
L
H
H
H
L
Operation
3780 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table(1)
OE
ZZ
I/O Status
Power
Read
L
L
Data Out (I/O0–I/O31)
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z — Data In (I/O 0–I/O31)
Active
Deselected
X
L
High-Z
Standby
Sleep Mode
X
H
High-Z
Sleep
Operation
3780 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
1
0
0
1
0
0
3780 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
(1)
Fourth Address
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
7
6.42
3780 tbl 11
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +10/-5%)
Symbol
Min.
Max.
Unit
VDD = Max., VIN = 0V to VDD
___
5
µA
VDD = Max., VIN = 0V to VDD
___
30
µA
5
µA
Parameter
Test Conditions
|ILI|
Input Leakage Current
|ILI|
ZZ & LBO Input Leakage Current
(1)
|ILO|
Output Leakage Current
CE > VIH or OE > VIH, VOUT = 0V to VDD, VDD = Max.
___
VOL
Output Low Voltage
IOL = 5mA, VDD = Min.
___
0.4
V
VOH
Output High Voltage
IOH = –5mA, VDD = Min.
2.4
___
V
3780 tbl 12
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to V SS if not actively driven.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VHD = VDDQ–0.2V, VLD = 0.2V)
IDT71V633S11(3)
Symbol
Parameter
Test Conditions
IDT71V633S12
Com'l
Ind'l
Com'l
Ind'l
Unit
IDD
Operating Core Power
Supply Current
Device Selected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)
160
—
150
150
mA
ISB
Standby Core Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)
45
—
40
40
mA
ISB1
Full Standby Core Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2)
15
—
15
15
mA
IZZ
Full Sleep Mode Core
Power Supply Current
ZZ > VHD, VDD = Max.
15
—
15
15
mA
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. 0°C to +70°C temperature range only.
+3.3V
AC Test Loads
VDDQ/2
317Ω
50Ω
DATA
OUT
3780 tbl 13
DATA OUT
351Ω
Z0 = 50Ω
5pF*
3780 drw 03
Figure 1. AC Test Load
3780 drw 04
* Including scope and jig capacitance.
6
Figure 2. High-Impedence Test Load
(for tOHZ, tCHZ, tOLZ, and tDC1)
5
4
AC Test Conditions
3
∆tCD
(Typical, ns)
2
Input Pulse Levels
1
20 30 50
80 100
Capacitance (pF)
200
2ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
AC Test Load
3780 drw 05
Figure 3. Lumped Capacitive Load, Typical Derating
0 to 3.0V
Input Rise/Fall Times
1.5V
See Figures 1 and 2
3780 tbl 14
8
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
71V633S11(5)
Symbol
Parameter
71V633S12
Min.
Max.
Min.
Max.
Unit
20
____
20
____
ns
6
____
ns
____
ns
Clock Parameters
tCYC
Clock Cycle Time
(1)
Clock High Pulse Width
6
____
(1)
Clock Low Pulse Width
6
____
6
____
11
____
12
ns
3
____
3
____
ns
0
____
ns
tCH
tCL
Output Parameters
tCD
Clock High to Valid Data
tCDC
tCLZ
Clock High to Data Change
(2)
Clock High to Output Active
0
____
(2)
Clock High to Data High-Z
3
6
3
6
ns
____
4
____
4
ns
tCHZ
tOE
Output Enable Access Time
tOLZ(2)
Output Enable Low to Data Active
0
____
0
____
ns
tOHZ (2)
Output Enable High to Data High-Z
____
6
____
6
ns
Address Setup Time
2.5
____
2.5
____
ns
2.5
____
ns
Setup Times
tSA
tSS
Address Status Setup Time
2.5
____
tSD
Data in Setup Time
2.5
____
2.5
____
ns
tSW
Write Setup Time
2.5
____
2.5
____
ns
2.5
____
2.5
____
ns
Chip Enable/Select Setup Time
2.5
____
2.5
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
ns
tHS
Address Status Hold Time
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.5
____
0.5
____
ns
0.5
____
0.5
____
ns
0.5
____
0.5
____
ns
0.5
____
0.5
____
ns
tSAV
Address Advance Setup Time
tSC
Hold Times
tHW
Write Hold Time
tHAV
Address Advance Hold Time
tHC
Chip Enable/Select Hold Time
Sleep Mode and Configuration Parameters
tZZPW
ZZ Pulse Width
100
____
100
____
ns
tZZR(3)
ZZ Recovery Time
100
____
100
____
ns
80
____
80
____
tCFG
(4)
Configuration Set-up Time
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. 0°C to +70°C temperature range only.
9
6.42
ns
3780 tbl 15
10
Output
Disabled
tSC
tSA
tSS
tHS
tOLZ
tOE
O1(Ax)
tHC
Flow-through
Read
Ax
tHA
tOHZ
Ay
(1)
tCH
O1(Ay)
tCDC
tCD
tSW
tCL
tSAVtHAV
O3(Ay)
O4(Ay)
(Burst wraps around
to its initial state)
ADV inserts a wait-state
Burst Flow-through Read
O2(Ay)
tHW
O1(Ay)
tCHZ
O2(Ay)
3780 drw 06
Timing Waveform of Read Cycle(1,2)
.
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base
address Ay, etc., where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don’t Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
OE
ADV
(Note 3)
CE, CS1
GW, BWE, BWx
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
11
6.42
Ax
(2)
Single Read
tSA
tHA
tSS
tHS
tCLZ
tCD
tOE
O1(Ax)
tOHZ
tSW
Ay
tCH
Write
I1(Ay)
tSD tHD
tCL
tHW
Az
tCDC
tOLZ
O2(Az)
O3(Az)
Flow-through Burst Read
O1(Az)
3780 drw 07
O4(Az)
.
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay. O1 (Az) represents the first output from the external address Az; O2 (Az) represents
the next output data in the burst sequence of the base address Az, etc., where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
DATAOUT
DATAIN
OE
ADV
GW
ADDRESS
ADSP
CLK
tCYC
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
12
O3(Aw)
tSC
tHC
tSA
tHA
tSS
tHS
Ax
O4(Aw)
(1)
.
Ay
tCL
tOHZ
I1(Ax)
I1(Ay)
BWE is ignored when ADSP initiates burst
tCH
I2(Ay)
(ADV suspends burst)
tSAV
I2(Ay)
(3)
I3(Ay)
tHAV
I4(Ay)
tSD
I1(Az)
tHW
tSW
Az
I3(Az)
3780 drw 08
I2(Az)
tHD
NOTES:
1. ZZ input is LOW, BWE is HIGH, and LBO is Don’t Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address
Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc., where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)
13
6.42
Burst
Read
O3(Aw)
tSC
tHC
tSA
tHA
tSS
tHS
O4(Aw)
Ax
.
(ADV suspends burst)
I2(Ay)
I3(Ay)
tSD
Single
Write
tOHZ
I1(Ax)
I1(Ay)
Burst Write
I2(Ay)
I4(Ay)
Extended
Burst Write
I1(Az)
tSAV
tHW
tSW
BWx is ignored when ADSP initiates burst
Az
tHW
tSW
Ay
tCL
BWE is ignored when ADSP initiates burst
tCH
I2(Az)
tHD
3780 drw 09
I3(Az)
NOTES:
1. ZZ input is LOW, GW is HIGH, and LBO is Don’t Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address
Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc., where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
BWx
BWE
ADDRESS
ADSC
ADSP
CLK
tCYC
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 — Byte Controlled(1,2,3)
14
tSS
tSC
tSA
tHS
tOLZ
Ax
O1(Ax)
Single Read
tOE
tHC
tHA
tCH
tCL
tZZPW
Snooze Mode
.
t ZZR
NOTES:
1. Device must power up in deselected mode.
2. LBO input is Don’t Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
ZZ
DATAOUT
OE
ADV
(Note 4)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
Az
3780 drw 10
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
GW, BWE, BWx
CE, CS1
CS0
OE
DATAOUT
(Av)
(Aw)
(Ax)
(Ay)
.
3780 drw 11
NOTES:
1 ZZ input is LOW, ADV is HIGH, and LBO is Don’t Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
15
6.42
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
(Ax)
(Ay)
(Az)
GW
CE, CS1
CS0
DATAIN
(Av)
(Aw)
3780 drw 12
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
16
.
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
100-pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline
17
6.42
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Ordering Information
IDT
71V633
S
X
PF
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
PF
Plastic Thin Quad Flatpack, 100 pin (PK100-1)
11*
12
tCD in nanoseconds
* Commercial only.
PART NUMBER
SPEED IN MEGAHERTZ
tCD PARAMETER
CLOCK CYCLE TIME
71V633S11PF
50 MHz
11 ns
20 ns
71V633S12PF
50 MHz
12 ns
20 ns
3780 drw 13
18
.
IDT71V633, 64K x 32, 3.3V Synchronous SRAM with
Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Datasheet Document History
9/9/99
9/30/99
10/8/99
04/04/00
08/09/00
08/17/01
Pg. 6–8
Pg. 10–14
Pg. 18
Pg. 1, 4, 8, 9, 17
Pg. 1
Pg. 17
Updated to new format
Reordered pages, updated notes
Updated notes
Added Datasheet Document History
Added Industrial temperature range offering
Corrected –12 speed
Added 100pinTQFP Package Diagram Outline
Not recommended for new designs
Removed “Not recommended for new designs” from the background on the datasheet
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19
6.42
for TECH SUPPORT:
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