TI CDC2510APWRG4 3.3-v phase-lock loop clock driver Datasheet

SCAS604C− APRIL 1998 − REVISED DECEMBER 2004
D Use CDCVF2510A as a Replacement for
D
D
D
D
D
D
D
D
D
D
PW PACKAGE
(TOP VIEW)
this Device
Spread Spectrum Clock Compatible
100-MHz Maximum Frequency
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to One Bank of
Ten Outputs
Single Output Enable Terminal Controls All
Ten Outputs
External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3-V VCC
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
G
FBOUT
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CLK
AVCC
VCC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
VCC
FBIN
description
The CDC2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDC2510A operates at 3.3-V VCC and provides
integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510A does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510A requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDC2510A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
OUTPUTS
INPUTS
G
CLK
1Y
(0:9)
X
L
L
L
L
H
L
H
H
H
H
H
FBOUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
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1
SCAS604C− APRIL 1998 − REVISED DECEMBER 2004
functional block diagram
G
11
3
4
5
8
9
15
16
CLK
24
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÁÁÁÁÁÁ
ÎÎÎÎÎÎÎ
ÁÁÁÁÁÁ
ÎÎÎÎÎÎÎ
17
PLL
FBIN
AVCC
13
20
21
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
1Y9
23
12
AVAILABLE OPTIONS
PACKAGE
2
1Y0
TA
SMALL OUTLINE
(PW)
0°C to 70°C
CDC2510A
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• DALLAS, TEXAS 75265
FBOUT
SCAS604C− APRIL 1998 − REVISED DECEMBER 2004
Terminal Functions
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
CLK
24
I
Clock input. CLK provides the clock signal to be distributed by the CDC2510A clock driver. CLK is
used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK
must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock
the feedback signal to its reference signal.
FBIN
13
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
G
11
I
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same
frequency as CLK.
FBOUT
12
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
and integrated 25-Ω series-damping resistor.
1Y (0:9)
3, 4, 5, 8, 9
15, 16, 17, 20,
21
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
Each output has an integrated 25-Ω series-damping resistor.
AVCC
23
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK is buffered directly to the device outputs.
AGND
1
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
GND
2, 10, 14, 22
Power
Power supply
6, 7, 18, 19
Ground
Ground
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SCAS604C− APRIL 1998 − REVISED DECEMBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, AVCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVCC < VCC +0.7 V
Supply voltage range, VCC, AVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high
or low state, VO (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. AVCC must not exceed VCC.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
recommended operating conditions (see Note 5)
MIN
MAX
Supply voltage, VCC, AVCC
3
3.6
High-level input voltage, VIH
2
Low-level input voltage, VIL
0
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
0
NOTE 5: Unused inputs must be held high or low to prevent them from floating.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
V
0.8
Input voltage, VI
UNIT
V
VCC
−12
mA
V
12
mA
70
°C
SCAS604C− APRIL 1998 − REVISED DECEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
II = −18 mA
IOH = −100 µA
VOH
IOH = −12 mA
IOH = − 6 mA
VOL
II
ICC§
∆ICC
Ci
Co
AVCC, VCC
3V
MIN
MIN to MAX
3V
VCC −0.2
2.1
3V
2.4
IOL = 100 µA
IOL = 12 mA
IO = 0, Outputs: low or high
Other inputs at VCC or GND
MAX
UNIT
−1.2
V
V
MIN to MAX
0.2
3V
0.8
3V
0.55
IOL = 6 mA
VI = VCC or GND
VI = VCC or GND,
One input at VCC − 0.6 V,
TYP‡
3.6 V
±5
µA
3.6 V
10
µA
500
µA
3.3 V to 3.6 V
VI = VCC or GND
VO = VCC or GND
V
3.3 V
4
pF
3.3 V
6
pF
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ For ICC of AVCC, see Figure 5.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
fclk
Clock frequency
Input clock duty cycle
Stabilization time†
MAX
UNIT
80
100
MHz
40%
60%
1
ms
† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Note 6 and Figures 1 and 2)‡
PARAMETER
tphase error, reference
(see Note 7, Figure 3)
tphase error− jitter
(see Note 8)
tsk(o)§
Jitter(pk-pk)
(see Figure 4)
Duty cycle reference
(see Figure 4)
FROM
(INPUT)/CONDITION
TO
(OUTPUT)
80 MHz < CLKIN↑ ≤ 100 MHz
FBIN↑
CLKIN↑ = 100 MHz
FBIN↑
Any Y or FBOUT
Any Y or FBOUT
Clkin = 100 MHz
Any Y or FBOUT
F(clkin > 80 MHz)
Any Y or FBOUT
VCC, AVCC = 3.3 V
± 0.165 V
VCC, AVCC = 3.3 V
± 0.3 V
MIN
MIN
TYP
MAX
TYP
−700
−750
−350
−300
−540
• DALLAS, TEXAS 75265
ps
ps
200
ps
−150
150
ps
45%
55%
tr
Any Y or FBOUT
1.3
1.9
0.8
2.1
tf
Any Y or FBOUT
1.7
2.5
1.2
2.7
‡ These parameters are not production tested.
§ The tsk(o) specification is only valid for equal loading of all outputs.
NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. This is considered as static phase error.
8. Phase error does not include jitter. The total phase error is − 900 ps to −200 ps for the 5% VCC range.
POST OFFICE BOX 655303
UNIT
MAX
ns
ns
5
SCAS604C− APRIL 1998 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
3V
Input
50% VCC
0V
tpd
From Output
Under Test
500 W
Output
30 pF
2V
0.4 V
tr
LOAD CIRCUIT FOR OUTPUTS
50% VCC
VOH
2V
0.4 V
VOL
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CLKIN
FBIN
tphase error
FBOUT
Any Y
tsk(o)
Any Y
Any Y
tsk(o)
Figure 2. Phase Error and Skew Calculations
6
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SCAS604C− APRIL 1998 − REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
JITTER (PEAK-TO-PEAK)
vs
CLOCK FREQUENCY
−300
−350
550
AVCC, VCC = 3.3 V
TA = 25°C
450
Jitter (Peak-to-Peak) − ps
Static Phase Error − ps
−400
−450
−500
−550
−600
−650
400
350
300
250
200
−700
−750
60
AVCC, VCC = 3.3 V
RL = 500 Ω
CL = 30 pF
TA = 25°C
All Outputs Switching
500
150
70
80
90
100
110
120
100
60
130
70
fclk − Clock Frequency − MHz
Figure 3
60
80
100
120
fclk − Clock Frequency − MHz
140
100
110
SUPPLY CURRENT
vs
CLOCK FREQUENCY
14
250
AVCC, VCC = 3.3 V
TA = 25°C
VCC = 3.6 V
TA = 25°C
CLY = CLF = 30 pF
200
I CC − Supply Current − mA
AICC − Analog Supply Current − mA
130
90
Figure 4
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
12
120
80
fclk − Clock Frequency − MHz
10
8
6
4
150
100
50
2
0
30
50
70
90
110
130
0
20
40
fclk − Clock Frequency − MHz
Figure 5
Figure 6
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7
SCAS604C− APRIL 1998 − REVISED DECEMBER 2004
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°−ā 8°
0,75
0,50
A
Seating Plane
1,20 MAX
0,10
0,05 MIN
PINS **
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064 / E 08/96
NOTES: A.
B.
C.
D.
8
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDC2510APWR
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDC2510APWRG4
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
CDC2510APWR
23-May-2007
Package Pins
PW
24
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
MLA
330
16
6.95
8.3
1.6
8
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
CDC2510APWR
PW
24
MLA
342.9
336.6
28.58
Pack Materials-Page 2
W
Pin1
(mm) Quadrant
16
Q1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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