INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40373B MSI Octal transparent latch with 3-state outputs Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF40373B MSI Octal transparent latch with 3-state outputs EO causes the outputs to assume a high impedance OFF-state. The device features hysteresis on the E input to improve noise rejection. Schmitt-trigger action in the E input makes the circuit highly tolerant to slower input rise and fall times. DESCRIPTION The HEF40373B is an 8-bit transparent latch with 3-state buffered outputs. The output stages have high current output capability suitable for driving highly capacitive loads. The latch outputs follow the data inputs when the latch enable (E) is HIGH. When E is LOW, the data that meets the set-up times is latched. The 3-state outputs are controlled by the output enable input EO. A HIGH on The HEF40373B is pin and functionally compatible with the TTL ‘373’ device. Supply voltage range: 3 to 15 V. Fig.1 Functional diagram. Fig.2 Pinning diagram. PINNING HEF40373BP(N): 20-lead DIL; plastic HEF40373BD(F): HEF40373BT(D): D0 to D7 data inputs (SOT146-1) E latch enable input 20-lead DIL; ceramic (cerdip) EO output enable input (active LOW) (SOT152) O0 to O7 3-state buffered outputs 20-lead SO; plastic (SOT163-1) FAMILY DATA, IDD LIMITS category MSI ( ): Package Designator North America January 1995 See Family Specifications 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors 3 Product specification HEF40373B MSI Fig.4 Logic diagram (one latch). Octal transparent latch with 3-state outputs January 1995 Fig.3 Logic diagram. Philips Semiconductors Product specification HEF40373B MSI Octal transparent latch with 3-state outputs FUNCTION TABLE INPUTS EO E Dn INTERNAL REGISTER L H L L L L H H H H L L I L L L L h H H H L I L Z H L h H Z OPERATING MODES enable & read register latch & read register latch register & disable outputs Notes 1. H = HIGH state (the more positive voltage) h = HIGH state (one set-up time prior to the HIGH-to-LOW enable transition) L = LOW state (the less positive voltage) I = LOW state (one set-up time prior to the HIGH-to-LOw enable transition) Z = high impedance OFF-state January 1995 4 OUTPUTS O0 TO O7 Philips Semiconductors Product specification HEF40373B MSI Octal transparent latch with 3-state outputs RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) See Family Specifications, except for: D.C. current into any input ± II max. 10 mA D.C. source or sink current into any output ± IO max. 25 mA D.C. current into the supply terminals ±I max. 100 mA DC CHARACTERISTICS VSS = 0 V VDD V VOH V VOL V Tamb (°C) SYMBOL −40 MIN. Output current HIGH Output current HIGH Output current LOW 5 4,6 10 9,5 15 13,5 5 3,6 10 8,4 15 13,2 −IOH 5 0,4 10 0,5 15 1,5 Hysteresis 5 voltage at 10 enable input (E) 15 MIN. TYP. 0,6 1,2 0,45 mA 1,5 3,0 1,1 mA 15,5 mA 15 50 9,3 10 24 10,7 mA 14,4 15 46 15,0 mA 19,5 20 62 19,8 mA 9,5 30,0 VH TYP. 0,75 2,9 IOL MIN. + 85 1,85 14,5 −IOH TYP. + 25 2,3 7,6 25 5,4 17 45 1,75 mA 5,50 mA 19,0 220 mV 250 mV 320 mV (1) P-channel MOS transistor conducting. (2) P-channel MOS transistor and bipolar n-p-n transistor conducting. Fig.5 Typical output source current characteristic. January 1995 Fig.6 Schematic diagram of output stage. 5 mA Philips Semiconductors Product specification HEF40373B MSI Octal transparent latch with 3-state outputs AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays E → On HIGH to LOW 5 10 tPHL 15 E → On LOW to HIGH 5 10 tPLH 15 Output transition times HIGH to LOW LOW to HIGH 5 150 300 ns 138 ns + (0,24 ns/pF) CL 60 120 ns 59 ns + (0,01 ns/pF) CL 40 80 ns 36 ns + (0,07 ns/pF) CL 125 250 ns 122 ns + (0,06 ns/pF) CL 50 100 ns 48 ns + (0,03 ns/pF) CL 40 80 ns 39 ns + (0,02 ns/pF) CL 40 80 ns 20 40 ns 15 15 30 ns 5 30 60 ns 20 40 ns 15 15 30 ns 5 65 130 ns 30 60 ns 10 10 tTHL tTLH 3-state propagation delays Output disable times EO → On HIGH LOW 10 tPHZ 15 25 50 ns 5 75 150 ns 40 80 ns 15 30 60 ns 5 65 130 ns 10 tPLZ Output enable times EO → On HIGH LOW 10 tPZH 30 60 ns 15 25 50 ns 5 85 170 ns 35 70 ns 25 50 ns 10 tPZL 15 Set-up time Dn → E 5 10 tsu 15 7 ns 10 5 ns 15 10 5 ns Hold time 5 25 15 ns Dn → E 10 15 4 ns thold 15 10 3 ns Minimum latch enable 5 60 30 ns pulse width LOW 10 30 15 ns 20 10 ns 15 January 1995 tWEL 6 see Fig.7 Philips Semiconductors Product specification HEF40373B MSI Octal transparent latch with 3-state outputs AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns Dynamic power VDD V TYPICAL FORMULA FOR P (µW) 5 3 325 fi + ∑ (foCL) × VDD2 dissipation per 10 14 200 fi + ∑ (foCL) × VDD package (P) 15 37 425 fi + ∑ (foCL) × VDD2 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) tTLH − − − − tTHL Fig.7 Output transition times as a function of the load capacitance. . January 1995 7