LINER LTC2222-11 11-bit, 105msps adc Datasheet

LTC2222-11
11-Bit, 105Msps ADC
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FEATURES
DESCRIPTIO
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The LTC®2222-11 is a 105Msps, sampling 11-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2222-11 is perfect for
demanding communications applications with AC performance that includes 65.4dB SNR and 80dB spurious free
dynamic range for signals up to 150MHz. Ultralow jitter of
0.15psRMS allows undersampling of IF frequencies with
excellent noise performance.
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Sample Rate: 105Msps
65.4dB SNR up to 140MHz Input
80dB SFDR up to 150MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 475mW
CMOS Outputs
Selectable Input Ranges: ±0.5V or ±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
48-Pin 7mm × 7mm QFN Package
DC specs include ±0.15LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSBRMS.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.3V.
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APPLICATIO S
The ENC+ and ENC – inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
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TYPICAL APPLICATIO
SFDR vs Input Frequency
3.3V
VDD
REFL
FLEXIBLE
REFERENCE
+
ANALOG
INPUT
INPUT
S/H
–
11-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
0.5V TO 3.3V
90
OVDD
85
D10
•
•
•
D0
OUTPUT
DRIVERS
4th OR HIGHER
SFDR (dBFS)
REFH
95
80
75
2nd OR 3rd
70
65
OGND
CLOCK/DUTY
CYCLE
CONTROL
60
55
50
0
222211 TA01
ENCODE
INPUT
100
200
300
400
500
INPUT FREQUENCY (MHz)
600
222211 TA01b
222211f
1
LTC2222-11
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
OVDD = VDD (Notes 1, 2)
TOP VIEW
48 GND
47 VDD
46 VDD
45 GND
44 VCM
43 SENSE
42 MODE
41 OF
40 D10
39 D9
38 OGND
37 OVDD
Supply Voltage (VDD) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ............... –0.3V to (OVDD + 0.3V)
Power Dissipation ............................................ 1500mW
Operating Temperature Range
LTC2222-11C .......................................... 0°C to 70°C
LTC2222-11I .......................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
AIN+ 1
AIN– 2
REFHA 3
REFHA 4
REFLB 5
REFLB 6
REFHB 7
REFHB 8
REFLA 9
REFLA 10
VDD 11
VDD 12
36 D8
35 D7
34 D6
33 OVDD
32 OGND
31 D5
30 D4
29 D3
28 OVDD
27 OGND
26 D2
25 D1
GND 13
VDD 14
GND 15
ENC + 16
ENC – 17
SHDN 18
OE 19
CLOCKOUT 20
NC 21
OGND 22
OVDD 23
D0 24
49
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
EXPOSED PAD IS GND (PIN 49),
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 29°C/W
ORDER PART NUMBER
UK PART MARKING*
LTC2222CUK-11
LTC2222IUK-11
LTC2222UK-11
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
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CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
11
Integral Linearity Error
Differential Analog Input (Note 5)
●
–1
±0.15
1
LSB
Differential Linearity Error
Differential Analog Input
●
–0.8
±0.1
0.8
LSB
Integral Linearity Error
Single-Ended Analog Input (Note 5)
±0.5
LSB
Differential Linearity Error
Single-Ended Analog Input
±0.1
LSB
Offset Error
(Note 6)
●
–37
±3
37
Gain Error
External Reference
●
–2.5
±0.5
2.5
Resolution (No Missing Codes)
Offset Drift
Bits
mV
%FS
±10
µV/°C
Full-Scale Drift
Internal Reference
External Reference
±30
±15
ppm/°C
ppm/°C
Transition Noise
SENSE = 1V
0.25
LSBRMS
222211f
2
LTC2222-11
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A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (AIN+ – AIN–)
3.1V < VDD < 3.5V
●
VIN, CM
Analog Input Common Mode (AIN+
Differential Input Drive
●
1
1.6
1.9
Single Ended Input Drive
●
0.5
1.6
2.1
V
IIN
Analog Input Leakage Current
0 < AIN+, AIN– < VDD
●
–1
1
µA
ISENSE
SENSE Input Leakage
0V < SENSE < 1V
●
–1
1
µA
IMODE
MODE Pin Pull-Down Current to GND
10
µA
tAP
Sample and Hold Acquisition Delay Time
0
ns
tJITTER
Sample and Hold Acquisition Delay Time Jitter
CMRR
+ AIN–)/2
MIN
MAX
UNITS
V
0.15
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
TYP
±0.5 to ±1
Figure 8 Test Circuit
V
psRMS
80
dB
775
MHz
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DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
30MHz Input (1V Range)
30MHz Input (2V Range)
SFDR
SFDR
S/(N+D)
Spurious Free Dynamic Range
Spurious Free Dynamic Range
4th Harmonic or Higher
Signal-to-Noise Plus
Distortion Ratio
MIN
TYP
64.3
62.5
65.7
dB
dB
70MHz Input (1V Range)
70MHz Input (2V Range)
62.5
65.7
dB
dB
140MHz Input (1V Range)
140MHz Input (2V Range)
62.2
65.4
dB
dB
250MHz Input (1V Range)
250MHz Input (2V Range)
61.8
64.9
dB
dB
84
84
dB
dB
70MHz Input (1V Range)
70MHz Input (2V Range)
84
84
dB
dB
140MHz Input (1V Range)
140MHz Input (2V Range)
81
81
dB
dB
250MHz Input (1V Range)
250MHz Input (2V Range)
77
77
dB
dB
30MHz Input (1V Range)
30MHz Input (2V Range)
88
88
dB
dB
70MHz Input (1V Range)
70MHz Input (2V Range)
88
88
dB
dB
140MHz Input (1V Range)
140MHz Input (2V Range)
88
88
dB
dB
250MHz Input (1V Range)
250MHz Input (2V Range)
85
85
dB
dB
62.5
65.6
dB
dB
62.5
65.6
dB
dB
81
dBc
30MHz Input (1V Range)
30MHz Input (2V Range)
30MHz Input (1V Range)
30MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
IMD
Intermodulation Distortion
fIN1 = 138MHz, fIN2 = 140MHz
●
●
●
71
64
MAX
UNITS
222211f
3
LTC2222-11
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I TER AL REFERE CE CHARACTERISTICS
(Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
VCM Output Voltage
IOUT = 0
1.575
1.600
1.625
±25
VCM Output Tempco
UNITS
V
ppm/°C
VCM Line Regulation
3.1V < VDD < 3.5V
3
mV/V
VCM Output Resistance
–1mA < IOUT < 1mA
4
Ω
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2.5
V
V
ENCODE INPUTS (ENC +, ENC –)
VID
Differential Input Voltage
VICM
Common Mode Input Voltage
RIN
Input Resistance
CIN
Input Capacitance
●
Internally Set
Externally Set (Note 7)
●
0.2
1.1
(Note 7)
V
1.6
1.6
6
kΩ
3
pF
LOGIC INPUTS (OE, SHDN)
VIH
High Level Input Voltage
VDD = 3.3V
●
VIL
Low Level Input Voltage
VDD = 3.3V
●
IIN
Input Current
VIN = 0V to VDD
●
CIN
Input Capacitance
(Note 7)
2
V
–10
0.8
V
10
µA
3
pF
LOGIC OUTPUTS
OVDD = 3.3V
COZ
Hi-Z Output Capacitance
OE = High (Note 7)
3
pF
ISOURCE
Output Source Current
VOUT = 0V
50
mA
ISINK
Output Sink Current
VOUT = 3.3V
50
mA
VOH
High Level Output Voltage
IO = –10µA
IO = –200µA
●
IO = 10µA
IO = 1.6mA
●
VOL
Low Level Output Voltage
3.1
3.295
3.29
0.005
0.09
V
V
0.4
V
V
OVDD = 2.5V
VOH
High Level Output Voltage
IO = –200µA
2.49
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
VOH
High Level Output Voltage
IO = –200µA
1.79
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
OVDD = 1.8V
222211f
4
LTC2222-11
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POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
VDD
Analog Supply Voltage
OVDD
IVDD
CONDITIONS
MIN
TYP
MAX
UNITS
●
3.1
3.3
3.5
V
Output Supply Voltage
●
0.5
3.3
3.6
V
Analog Supply Current
●
144
162
mA
PDISS
Power Dissipation
●
475
535
mW
PSHDN
Shutdown Power
SHDN = High, OE = High, No CLK
2
mW
PNAP
Nap Mode Power
SHDN = High, OE = Low, No CLK
35
mW
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TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fS
Sampling Frequency
●
1
tL
ENC Low Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
●
4.5
3
4.76
4.76
105
MHz
500
500
ns
ns
tH
ENC High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
●
4.5
3
4.76
4.76
500
500
ns
ns
tAP
Sample-and-Hold Aperture Delay
tOE
Output Enable Delay
(Note 7)
●
5
10
ns
tD
ENC to DATA Delay
(Note 7)
●
1.3
2.1
4
ns
tC
ENC to CLOCKOUT Delay
(Note 7)
●
1.3
2.1
4
ns
DATA to CLOCKOUT Skew
(tC - tD) (Note 7)
●
–0.6
0
0.6
0
Pipeline Latency
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 105MHz, differential
ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive,
unless otherwise noted.
5
ns
ns
Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from a
“best straight line” fit to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 000 0000 0000 and 111 1111 1111 in 2’s
complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 105MHz, differential
ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive,
output CLOAD = 5pF.
222211f
5
LTC2222-11
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TYPICAL PERFOR A CE CHARACTERISTICS
DNL, 2V Range
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0
– 0.2
–0.2
–0.4
–0.6
– 0.8
–0.8
– 1.0
–1.0
1024
1536
100000
0
– 0.6
512
127161
120000
0.2
– 0.4
0
Noise Histogram
140000
COUNT
ERROR (LSB)
ERROR (LSB)
INL, 2V Range
1.0
2048
80000
60000
40000
20000
0
512
OUTPUT CODE
1024
1536
1020
2048
OUTPUT CODE
222211 G01
70
100
67
69
95
68
90
63
66
65
64
60
61
60
100
300
200
400
500
INPUT FREQUENCY (MHz)
60
600
55
0
100
222211 G04
300
400
500
200
INPUT FREQUENCY (MHz)
600
0
95
95
95
90
90
90
85
85
85
SFDR (dBFS)
100
SFDR (dBFS)
100
75
75
80
75
70
70
70
65
65
65
60
60
60
55
55
55
0
100
200
300
400
500
INPUT FREQUENCY (MHz)
600
222211 G07
600
SFDR (HD4+) vs Input Frequency,
–1dB, 1V Range
100
80
200
300
400
500
INPUT FREQUENCY (MHz)
222211 G06
SFDR (HD4+) vs Input Frequency,
–1dB, 2V Range
80
100
222211 G05
SFDR (HD2 and HD3) vs Input
Frequency, –1dB, 1V Range
SFDR (dBFS)
75
65
62
61
80
70
63
62
1024
85
SFDR (dBFS)
SNR (dBFS)
SNR (dBFS)
67
64
1023
SFDR (HD2 and HD3) vs Input
Frequency, –1dB, 2V Range
68
65
1022
0
222211 G03
SNR vs Input Frequency, –1dB,
1V Range
66
1021
2725
CODE
222211 G02
SNR vs Input Frequency, –1dB,
2V Range
0
1186
0
0
0
100
200
300
400
500
INPUT FREQUENCY (MHz)
600
222211 G08
0
100
200
300
400
500
INPUT FREQUENCY (MHz)
600
222211 G09
222211f
6
LTC2222-11
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TYPICAL PERFOR A CE CHARACTERISTICS
SFDR and SNR vs Sample Rate,
1V Range, fIN = 30MHz, –1dB
SFDR and SNR vs Sample Rate,
2V Range, fIN = 30MHz, –1dB
90
90
SFDR
160
SFDR
85
80
75
70
SNR
65
80
140
75
70
110
SNR
60
80
60
100
40
SAMPLE RATE (Msps)
10
120
140
100
0
20
222211 G10
80
60
100
40
SAMPLE RATE (Msps)
120
140
0
20
222211 G11
80
120
60
100
40
SAMPLE RATE (Msps)
222211 G12
SFDR vs Input Level,
f IN = 70MHz, 2V Range
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB, OVDD = 1.8V
100
90
80
8
SFDR (dBc AND dBFS)
20
IOVDD (mA)
0
130
120
65
60
150
IVDD (mA)
SFDR AND SNR (dBFS)
85
SFDR AND SNR (dBFS)
IVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB
6
4
dBFS
70
60
dBc
50
40
30
20
2
10
0
0
20
40
60
80
SAMPLE RATE (Msps)
100
120
222211 G13
0
–60
–50
–30
–20
–40
INPUT LEVEL (dBFS)
–10
0
222211 F14
222211f
7
LTC2222-11
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TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT,
f IN = 30MHz, –1dB, 2V Range
0
0
–10
–10
–20
–20
–30
–30
–40
–40
AMPLITUDE (dB)
AMPLITUDE (dB)
8192 Point FFT,
f IN = 5MHz, –1dB, 2V Range
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–110
–110
–120
0
5
–120
10 15 20 25 30 35 40 45 50
222211 G15
FREQUENCY (MHz)
0
0
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–110
–110
–120
10 15 20 25 30 35 40 45 50
FREQUENCY (MHz)
222211 G16
8192 Point FFT,
f IN = 140MHz, –1dB, 2V Range
AMPLITUDE (dB)
AMPLITUDE (dB)
8192 Point FFT,
f IN = 70MHz, –1dB, 2V Range
5
–120
0
5
10 15 20 25 30 35 40 45 50
FREQUENCY (MHz)
222211 G17
0
5
10 15 20 25 30 35 40 45 50
FREQUENCY (MHz)
222211 G18
222211f
8
LTC2222-11
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PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input.
AIN– (Pin 2): Negative Differential Analog Input.
REFHA (Pins 3, 4): ADC High Reference. Bypass to Pins
5, 6 with 0.1µF ceramic chip capacitor, to Pins 9, 10 with
a 2.2µF ceramic capacitor and to ground with a 1µF
ceramic capacitor.
REFLB (Pins 5, 6): ADC Low Reference. Bypass to Pins 3,
4 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 9, 10.
REFHB (Pins 7, 8): ADC High Reference. Bypass to Pins
9, 10 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 3, 4.
REFLA (Pins 9, 10): ADC Low Reference. Bypass to Pins
7, 8 with 0.1µF ceramic chip capacitor, to Pins 3, 4 with a
2.2µF ceramic capacitor and to ground with a 1µF ceramic
capacitor.
VDD (Pins 11, 12, 14, 46, 47): 3.3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors. Adjacent pins
can share a bypass capacitor.
GND (Pins 13, 15, 45, 48): ADC Power Ground.
ENC + (Pin 16): Encode Input. The input is sampled on the
positive edge.
ENC – (Pin 17): Encode Complement Input. The input is
sampled on the negative edge. Bypass to ground with
0.1µF ceramic for single-ended ENCODE signal.
SHDN (Pin 18): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
OE (Pin 19): Output Enable Pin. Refer to SHDN pin
function.
CLOCKOUT (Pin 20): Data Valid Output. Latch data on the
falling edge of CLOCKOUT.
NC (Pin 21): Do Not Connect This Pin.
D0 – D10 (Pins 24, 25, 26, 29, 30, 31, 34, 35, 36, 39,
40): Digital Outputs. D10 is the MSB.
OGND (Pins 22, 27, 32, 38): Output Driver Ground.
OVDD (Pins 23, 28, 33, 37): Positive Supply for the
Output Drivers. Bypass to ground with 0.1µF ceramic chip
capacitors.
OF (Pin 41): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 42): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3 VDD selects offset
binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
SENSE (Pin 43): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pin 44): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
Exposed Pad (Pin 49): ADC Power Ground. The exposed
pad on the bottom of the package needs to be soldered to
ground.
222211f
9
LTC2222-11
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FUNCTIONAL BLOCK DIAGRA
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U
AIN+
AIN–
VCM
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
1.6V
REFERENCE
2.2µF
SHIFT REGISTER
AND CORRECTION
RANGE
SELECT
REFH
SENSE
FIFTH PIPELINED
ADC STAGE
REFL
INTERNAL CLOCK SIGNALS
OVDD
REF
BUF
OF
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DIFF
REF
AMP
CONTROL
LOGIC
•
•
•
OUTPUT
DRIVERS
D10
D0
CLOCKOUT
REFLB REFHA
2.2µF
0.1µF
1µF
222211 F01
REFLA REFHB
OGND
+
ENC
–
ENC
M0DE
SHDN
OE
0.1µF
1µF
Figure 1. Functional Block Diagram
222211f
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LTC2222-11
W
UW
TI I G DIAGRA S
Timing Diagram
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
N+1
tL
ENC –
ENC +
tD
N–5
D0-D10, OF
N–4
N–3
N–2
N–1
tC
222211 TD01
CLOCKOUT
OE
t OE
DATA
t OE
OF, D0-D10, CLOCKOUT
222211f
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LTC2222-11
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The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Signal-to-Noise Ratio
Spurious Free Dynamic Range (SFDR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log √(V22 + V32 + V42 + . . . Vn2)/V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
Full Power Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC+ equals the ENC– voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π) • fIN • tJITTER
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CONVERTER OPERATION
As shown in Figure 1, the LTC2222-11 is a CMOS pipelined
multistep converter. The converter has five pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section).
For optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
analog inputs can be driven single-ended with slightly
worse harmonic distortion. The encode input is differential for improved common mode noise immunity. The
LTC2222-11 has two phases of operation, determined by
the state of the differential ENC+/ENC– input pins. For
brevity, the text will refer to ENC+ greater than ENC– as ENC
high and ENC+ less than ENC– as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
stage residue that is sent to the fifth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2222-11
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (CSAMPLE) through
NMOS transistors. The capacitors shown attached to each
input (CPARASITIC) are the summation of all other capacitance associated with each input.
LTC2222-11
VDD
AIN+
CSAMPLE
1.6pF
15Ω
CPARASITIC
1pF
VDD
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth
AIN–
CSAMPLE
1.6pF
15Ω
CPARASITIC
1pF
VDD
1.6V
6k
ENC+
ENC–
6k
1.6V
222211 F02
Figure 2. Equivalent Input Circuit
222211f
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During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to, and track the differential input voltage.
When ENC transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when ENC is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.6V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.6V. The VCM output pin (Pin
44) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2222-11 can be influenced by the input drive circuitry, particularly the second
and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC, the
sample-and-hold circuit will connect the 1.6pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally the input
circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2222-11 being driven by an RF
transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input
VCM
2.2µF
0.1µF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
AIN+
LTC2222-11
0.1µF
12pF
25Ω
25Ω
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
222211 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
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signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedance seen by the ADC does not exceed 100Ω
for each ADC input. A disadvantage of using a transformer
is the loss of low frequency response. Most small RF
transformers have poor performance at frequencies below 1MHz.
former gives better high frequency response than a flux
coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.6V. In
Figure 8 the series inductors are impedance matching
elements that maximize the ADC bandwidth.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input
frequencies.
Figure 9 shows the LTC2222-11 reference circuitry consisting of a 1.6V bandgap reference, a difference amplifier
and switching and control circuit. The internal voltage
reference can be configured for two pin selectable input
ranges of 2V (±1V differential) or 1V (±0.5V differential).
Tying the SENSE pin to VDD selects the 2V range; tying the
SENSE pin to VCM selects the 1V range.
Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be
decreased to prevent excessive signal loss.
Reference Operation
The 1.6V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.6V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
For input frequencies above 100MHz the input circuits of
Figure 6, 7 and 8 are recommended. The balun transVCM
VCM
HIGH SPEED
DIFFERENTIAL
25Ω
AMPLIFIER
ANALOG
INPUT
+
AIN+
0.1µF
LTC2222-11
ANALOG
INPUT
2.2µF
1k
12pF
12pF
–
LTC6600-20,
LT1993
25Ω
AIN+ LTC2222-11
25Ω
+
CM
–
1k
2.2µF
25Ω
AIN–
AIN–
0.1µF
222211 F05
222211 F04
Figure 4. Differential Drive with an Amplifier
Figure 5. Single-Ended Drive
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and REFLB for the low reference. The multiple output pins
are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9.
VCM
2.2µF
0.1µF
AIN+
12Ω
ANALOG
INPUT
25Ω
T1
0.1µF
LTC2222-11
0.1µF
8pF
25Ω
AIN–
12Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
222211 F06
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 100MHz and 250MHz
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
VCM
LTC2222-11
2.2µF
0.1µF
AIN+
ANALOG
INPUT
25Ω
4Ω
VCM
1.6V
LTC2222-11
1.6V BANDGAP
REFERENCE
2.2µF
0.1µF
1V
0.5V
T1
0.1µF
25Ω
RANGE
DETECT
AND
CONTROL
AIN–
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
222211 F07
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 250MHz and 500MHz
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
SENSE
REFLB
0.1µF
REFHA
1µF
VCM
BUFFER
INTERNAL ADC
HIGH REFERENCE
2.2µF
DIFF AMP
2.2µF
0.1µF
25Ω
1µF
REFLA
LTC2222-11
0.1µF
T1
0.1µF
AIN+
4.7nH
ANALOG
INPUT
0.1µF
2pF
25Ω
4.7nH
INTERNAL ADC
LOW REFERENCE
REFHB
AIN–
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
222211 F09
222211 F08
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 500MHz
Figure 9. Equivalent Reference Circuit
1.6V
VCM
2.2µF
12k
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has four pins: two each of REFHA
and REFHB for the high reference and two each of REFLA
0.8V
12k
SENSE
LTC2222-11
1µF
222211 F10
Figure 10. 1.6V Range ADC
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Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 3.2dB. See the Typical Performance Characteristics section.
Driving the Encode Inputs
The noise performance of the LTC2222-11 can depend on
the encode signal quality as much as on the analog input.
The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from common mode
noise sources. Each input is biased through a 6k resistor
to a 1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequencies) take the following into consideration:
1. Differential drive should be used.
VDD
LTC2222-11
TO INTERNAL
ADC CIRCUITS
VDD
1.6V BIAS
6k
ENC+
0.1µF
1:4
CLOCK
INPUT
VDD
50Ω
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at both
inputs as common mode noise. The encode inputs have a
common mode range of 1.1V to 2.5V. Each input may be
driven from ground to VDD for single-ended drive.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2222-11 is 105Msps.
For the ADC to operate properly, the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 4.5ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise
50% duty cycle is easy with differential sinusoidal drive
using a transformer or using symmetric differential logic
such as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the ENC+ pin to sample the analog
input. The falling edge of ENC+ is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 20% to 80% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require one
hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3VDD or 2/3VDD using external
resistors.
The lower limit of the LTC2222-11 sample rate is determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operating frequency for the LTC2222-11 is 1Msps.
1.6V BIAS
6k
ENC–
222211 F11
Figure 11. Transformer Driven ENC+/ENC–
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DIGITAL OUTPUTS
Digital Output Buffers
Figure 13 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, which
are isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows
operation down to voltages as low as 0.5V. The internal
resistor in series with the output makes the output appear
as 50Ω to external circuitry and may eliminate the need for
external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2222-11 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. For full speed
operation the capacitive load should be kept under 5pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs and improve the SNR.
Data Format
The LTC2222-11 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
ENC+
VTHRESHOLD = 1.6V
selected with the MODE pin. Connecting MODE to GND or
1/3VDD selects offset binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 1 shows the logic
states for the MODE pin.
Table 1. MODE Pin Function
Output Format
Clock Duty
Cycle Stablizer
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
MODE Pin
Overflow Bit
The converter is either overranged or underranged when
OF outputs a logic high.
Output Clock
The ADC has a delayed version of the ENC+ input available
as a digital output, CLOCKOUT. The CLOCKOUT pin can be
used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. Data
will be updated just after CLOCKOUT rises and can be
latched on the falling edge of CLOCKOUT.
Output Driver Power
1.6V ENC– LTC2222-11
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
0.1µF
222211 F12a
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
LTC2222-11
OVDD
VDD
3.3V
MC100LVELT22
VDD
0.5V
TO 3.6V
0.1µF
3.3V
130Ω
Q0
130Ω
OVDD
ENC+
D0
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
ENC– LTC2222-11
Q0
TYPICAL
DATA
OUTPUT
OE
83Ω
OGND
83Ω
222211 F12b
222211 F13
Figure 12b. ENC Drive Using a CMOS to PECL Translator
Figure 13. Digital Output Buffer
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to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage up to 3.6V. OGND
can be powered with any voltage from GND up to 1V and
must be less than OVDD. The logic outputs will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF and
CLOCKOUT. The data access and bus relinquish times are
too slow to allow the outputs to be enabled and disabled
during full speed operation. The output Hi-Z state is intended
for use during long periods of inactivity.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
35mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap mode all digital outputs are disabled and enter the
Hi-Z state.
GROUNDING AND BYPASSING
The LTC2222-11 requires a printed circuit board with a clean
unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside an
analog signal or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB pins
as shown on the schematic on Page 20 of this data sheet.
Bypass capacitors must be located as close to the pins as
possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and REFLA.
These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are
recommended. The 2.2µF capacitor between REFHA and
REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and
should be made as wide as possible.
The LTC2222-11 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
HEAT TRANSFER
Most of the heat generated by the LTC2222-11 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad should
be soldered to a large grounded pad on the PC board. It is
critical that all ground pins are connected to a ground plane
of sufficient area.
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Evaluation Circuit Schematic of the LTC2222-11
VCC
VCC
CLOCKOUT JP1
34
45
VCC
R19
OPT
ANALOG
INPUT
C1
0.1µF
42
R1*
T1*
25
R2
24.9k
J1
48
C2*
24
R4
24.9k
C3
0.1µF
VCM
1
47
R6*
1
C4
0.1µF
R5
50Ω
2
3
4
13
C6
0.1µF
C5
1µF
15
5
C7
2.2µF
6
7
8
C9
0.1µF
C8
1µF
9
10
VDD
46
VDD
47
11
12
14
CLK
SHDN
C10
0.1µF
C12
0.1µF
16
C11
33pF
17
CLK
VDD
18
JP2
GND
19
44
C13
0.1µF
C15
2.2µF
43
42
JP3
SENSE
VDD
U1 LTC2222-11
20
AIN+
CLOCKOUT
21
AIN–
NC
24
REFHA
D0
25
REFHA
D1
26
GND
D2
29
GND
D3
30
REFLB
D4
31
REFLB
D5
34
REFHB
D6
35
REFHB
D7
36
REFLA
D8
39
REFLA
D9
40
VDD
D10
41
VDD
OF
37
VDD
OVDD
33
VDD
OVDD
28
VDD
OVDD
23
+
ENC
OVDD
38
ENC–
OGND
32
SHDN
OGND
27
OE
OGND
22
VCM
OGND
48
SENSE
GND
45
MODE
GND
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
U3
GND
GND
VCC
GND
GND
VCC
GND
2LE
VCC
1LE
GND
2OE
GND
1OE
VCC
1D1
1Q1
1D2
1Q2
1D3
1Q3
1D4
1Q4
1D5
1Q5
1D6
1Q6
1D7
1Q7
1D8
1Q8
2D1
2Q1
2D2
2Q2
2D3
28
31
2D4
4
7
39
40
2
37
38
3
35
36
5
RN1D 33Ω
D0
33
34
6
RN1C 33Ω
D1
31
32
8
RN1B 33Ω
D2
29
30
9
RN1A 33Ω
D3
27
28
11
RN2D 33Ω
D4
25
26
12
RN2C 33Ω
D5
23
24
13
RN2B 33Ω
D6
21
22
14
RN2A 33Ω
D7
19
20
16
RN3D 33Ω
D8
17
18
17
RN3C 33Ω
D9
15
16
19
RN3B 33Ω
D10
13
14
20
RN3A 33Ω
D11
11
12
22
9
10
23
7
8
5
6
3
4
1
2
2Q5
2D6
2Q6
2D7
2Q7
2D8
EXT
REF
R12
1k
2/3VDD
EXT
REF
R13
1k
1/3VDD
R14
1k
2Q8
PI74VCX16373A
C17
0.1µF
VCC
NC7SV865X
4
5
1
U5
C16
0.1µF
3
C28
0.01µF
3201S-40G1
222211 AI01
VCC
VDD
GND
Assembly Type
GND
C19
0.1µF
VCC
VDD
3.3V
C29
0.1µF
C30
0.1µF
C31
0.1µF
C32
0.1µF
VDD
ENCODE
INPUT
C23
J3 0.1µF
R1, R6
C2
T1
LTC2222CUK-11
24.9Ω
12pF
ETC1-1T
DC751A-N
LTC2222CUK-11
12.4Ω
8.2pF
ETC1-1-13
CLK
T2
ETC1-1T
R16
100Ω
U1
DC751A-M
*Version Type
C18
0.1µF
R18
100k
R8
10k
24LC025
C20
0.1µF
VCC
C27
10µF
6.3V
R9
10k
C21
0.1µF
C24
0.1µF
U6 LT1763
1
8
OUT
IN
2
7
ADJ GND
3
6
GND GND
4
5
BYP SHDN
R10
10k
1
8
A0 U4 VCC
2
7
A1
WP
3
6
A2
SCL
4
5
A3
SDA
2
C25
4.7µF
PWR
GND
C22
0.1µF
R17
105k
R3
33Ω
10
2Q4
2D5
5 NC7SV865X
4
U2
3
C33
0.1µF
18
VDD
VCM
2
15
VDD
VCM
1
21
2Q3
GND
49
JP4
MODE
VDD
39
GND
CLOCKOUT
R15
100Ω
CLK
C34
1µF
C26
0.1µF
222211f
20
LTC2222-11
U
W
U U
APPLICATIO S I FOR ATIO
Silkscreen Top
Layer 1 Component Side
Layer 2 GND Plane
222211f
21
LTC2222-11
U
W
U U
APPLICATIO S I FOR ATIO
Layer 3 Power Plane
Layer 4 Bottom Side
222211f
22
LTC2222-11
U
PACKAGE DESCRIPTIO
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704)
0.70 ±0.05
5.15 ±0.05
6.10 ±0.05 7.50 ±0.05
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220
VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT
INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT
EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON
THE TOP AND BOTTOM OF PACKAGE
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
7.00 ± 0.10
(4 SIDES)
0.75 ± 0.05
R = 0.115
TYP
47 48
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
PIN 1
CHAMFER
2
5.15 ± 0.10
(4-SIDES)
0.25 ± 0.05
0.200 REF
(UK48) QFN 1103
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
222211f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2222-11
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DESCRIPTION
COMMENTS
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LTC2229
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230mW, 71.6dB SNR, 5mm x 5mm QFN Package
LTC2230
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890mW, 61dB SNR, 9mm x 9mm QFN Package
LTC2231
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LTC2232
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475mW, 61dB SNR, 7mm x 7mm QFN Package
LTC2233
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366mW, 61dB SNR, 7mm x 7mm QFN Package
LTC2234
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660mW, 61dB SNR, 7mm x 7mm QFN Package
LTC2248
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210mW, 74dB SNR, 5mm x 5mm QFN Package
LTC2249
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230mW, 73dB SNR, 5mm x 5mm QFN Package
LTC2250
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320mW, 61.6dB SNR, 5mm x 5mm QFN Package
LTC2251
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395mW, 61.6dB SNR, 5mm x 5mm QFN Package
LTC2252
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320mW, 70.2dB SNR, 5mm x 5mm QFN Package
LTC2253
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395mW, 70.2dB SNR, 5mm x 5mm QFN Package
LTC2254
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320mW, 72.5dB SNR, 5mm x 5mm QFN Package
LTC2255
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395mW, 72.4dB SNR, 5mm x 5mm QFN Package
LTC2292
Dual 12-Bit, 40Msps ADC
240mW, 71dB SNR, 9mm x 9mm QFN Package
LTC2293
Dual 12-Bit, 65Msps ADC
410mW, 71dB SNR, 9mm x 9mm QFN Package
LTC2294
Dual 12-Bit, 80Msps ADC
445mW, 70.6dB SNR, 9mm x 9mm QFN Package
LTC2297
Dual 14-Bit, 40Msps ADC
240mW, 74dB SNR, 9mm x 9mm QFN Package
LTC2298
Dual 14-Bit, 65Msps ADC
410mW, 74dB SNR, 9mm x 9mm QFN Package
LTC2299
Dual 14-Bit, 80Msps ADC
445mW, 73dB SNR, 9mm x 9mm QFN Package
LT5512
DC-3GHz High Signal Level Downconverting Mixer
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514
Ultralow Distortion IF Amplifier/ADC Driver with Digitally
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450MHz 1dB BW, 47dB OIP3, Digital Gain Control
10.5dB to 33dB in 1.5dB/Step
LT5522
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4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
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222211f
24
Linear Technology Corporation
LT/TP 0805 500 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005