INNOVASIC CDP6805E2CQ Microprocessor unit Datasheet

IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Form, Fit, and Function Compatible with the Harris  CDP6805E2CE and
Motorola  MC146805E2
Internal 8-bit Timer with 7-Bit
Programmable Prescaler
On-chip Clock
Memory Mapped I/O
Versatile Interrupt Handling
True Bit Manipulation
Bit Test and Branch Instruction
Vectored Interrupts
Power-saving STOP and WAIT Modes
Fully Static Operation
112 Bytes of RAM
The IA6805E2 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces
replacement ICs using its MILESTM , or Managed IC Lifetime Extension System, cloning technology. This
technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible
with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon
technology advances. MILESTM also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA6805E2 including functional and I/O descriptions, electrical characteristics, and applicable
timing.
(7)
(34)
PB2
PA6
(9)
PA6
(8)
(33)
PB3
PA5
(10)
PA5
(9)
(32)
PB4
PA4
(11)
PA4
(10)
(31)
PB5
PA3
PA3
(11)
(30)
PB6
PA2
PA2
(12)
(29)
PB7
PA1
(13)
(28)
PA0
(14)
A12
PB0
PA7
TIMER
(8)
(40)
PA7
OSC2
PB1
(41)
(7)
(35)
OSC1
AS
(6)
(42)
PB0
AS
VDD
(36)
(43)
(5)
RESET_N
TIMER
RW_N
(44)
(37)
IRQ_N
(4)
(1)
OSC2
DS
LI
(38)
40 Pin DIP
(2)
OSC1
(3)
DS
LI
(3)
VDD
(39)
RW_N
(40)
IA6805E2
(4)
(2)
NC
(1)
IRQ_N
(5)
RESET_N
(6)
Package Pinout
IA6805E2
(39)
PB1
(38)
PB2
(37)
PB3
(36)
PB4
(35)
PB5
(12)
(34)
PB6
(13)
(33)
PB7
PA1
(14)
(32)
B0
B0
PA0
(15)
(31)
B1
(27)
B1
NC
(16)
(30)
B2
(15)
(26)
B2
NC
(17)
(29)
B3
A11
(16)
(25)
B3
A10
(17)
(24)
B4
A9
(18)
(23)
B5
A8
(19)
(22)
B6
VSS
(20)
(21)
B7
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(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
A12
A11
A10
A9
A8
VSS
B7
B6
B5
B4
NC
44 Pin LCC
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
Description
The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low cost, low power MPU. It features a
CPU, on-chip RAM, parallel I/O compatibility with pins programmable as input or output. The
following paragraphs will further describe this system block diagram and design in more detail.
TIMER
PRESCALER
OSC1
TIMER/
COUNTER
OSC2
RESET_N
TIMER CONTROL
OSCILLATOR
LI
IRQ_N
PA0
B0
PA0
ACCUMULATOR
PA1
8
CPU
CONTROL
A
PA2
PORT
A
I/O
LINES
PA3
PA4
PORT
A
REG
DATA
DIR
REG
PA5
PA6
PA7
X
6
PB1
PB2
PB3
PB4
PORT
B
REG
DATA
DIR
REG
B4
MULTIPLEXED
ADDRESS
DATA
BUS
B6
B7
CPU
SP
PROGRAM
COUNTER
HIGH
5
PCH
PB0
B3
B5
CONDITION
CODE
REGISTER
5
CC
STACK
POINTER
PORT
B
I/O
LINES
B2
MUX
BUS
DRIVE
INDEX
REGISTER
8
B1
A8
A9
PROGRAM
COUNTER
LOW
8
PCL
ADDRESS
DRIVE
A10
ADDRESS
BUS
A11
ALU
A12
PB5
PB6
PB7
AS
112x8
RAM
BUS
CONTROL
DS
RW_N
ADDRESS STROBE
DATA STROBE
READ/WRITE
Figure 1. System Block Diagram
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
I/O Signal Description
The table below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
SIGNAL
NAME
V D D a n d V SS
(Power and Ground)
I/O
DESCRIPTION
N/A
Source: These t w o pins provide power to the chip. V D
and V SS is ground.
D
provides + 5 volts (±0.5) p o w e r
RESET_n
(Reset)
I
T T L : I n p u t pin t h a t c a n b e u s e d t o r e s e t t h e M P U ' s i n t e r n a l s t a t e b y p u l l i n g t h e r e s e t _ n
pin low.
IRQ_n
(Interrupt Request)
I
T T L : I n p u t pin t h a t i s l e v e l a n d e d g e s e n s i t i v e . C a n b e u s e d t o r e q u e s t a n i n t e r r u p t
sequence.
LI
(Load Instruction)
O
DS
(Data Strobe)
O
RW_n
(Read/Write)
AS
(Address Strobe)
PA0-PA7/PB0-PB7
(Input/Output Lines)
B0-B7
(Address/Data Bus)
T T L w i t h s l e w r a t e c o n t r o l : O u t p u t p i n u s e d to t r a n s f e r d a t a t o o r f r o m a p e r i p h e r a l o r
m e m o r y . D S occurs a n y t i m e the M P U d o e s a d a t a read o r write a n d during data transfer
t o o r f r o m i n t e r n a l m e m o r y . D S is a v a i l a b l e a t f O S C ÷ 5 w h e n t h e M P U is n o t in t h e W A I T
or STOP mode. This output is capable of driving one standard TTL load and 130pF.
O
T T L w i t h s l e w r a t e c o n t r o l : O u t p u t pin u s e d to i n d i c a t e t h e d i r e c t i o n o f d a t a t r a n s f e r
from internal m e m o r y , I / O registers, and external peripheral d e v i c e s a n d m e m o r i e s .
I n d i c a t e s t o a s e l e c t e d p e r i p h e r a l w h e t h e r t h e M P U i s to r e a d ( R W _ n h i g h ) o r w r i t e
( R W _ n l o w ) data o n t h e n e x t data strobe. This o u t p u t is c a p a b l e o f d r i v i n g o n e standard
TTL load and 130pF.
O
T T L w i t h s l e w r a t e c o n t r o l : O u t p u t s t r o b e u s e d to i n d i c a t e t h e p r e s e n c e o f a n a d d r e s s
o n t h e 8 - b i t m u l t i p l e x e d b u s . T h e A S l i n e i s u s e d to d e m u l t i p l e x t h e e i g h t l e a s t s i g n i f i c a n t
a d d r e s s bits f r o m t h e data b u s . A S is a v a i l a b l e a t f O S C ÷ 5 w h e n t h e M P U is n o t in t h e
W A I T o r S T O P m o d e s . This o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d T T L load a n d
130pF.
I/O
A8-A12
(High Order Address Lines)
T T L w i t h s l e w r a t e c o n t r o l : O u t p u t pin u s e d to i n d i c a t e t h a t a n e x t o p c o d e f e t c h i s in
p r o g r e s s . U s e d o n l y f o r c e r t a i n d e b u g g i n g a n d t e s t s y s t e m s . N o t c o n n e c t e d in n o r m a l
o p e r a t i o n . O v e r l a p s D a t a S t r o b e ( D S ) signal. T h i s o u t p u t is c a p a b l e o f d r i v i n g o n e
standard TTL load and 50pF.
T T L with s l e w rate c o n t r o l : T h e s e 1 6 l i n e s c o n s t i t u t e I n p u t / O u t p u t p o r t s A a n d B .
E a c h l i n e is i n d i v i d u a l l y p r o g r a m m e d to b e e i t h e r a n i n p u t o r o u t p u t u n d e r s o f t w a r e
c o n t r o l o f t h e D a t a D i r e c t i o n R e g i s t e r ( D D R ) a s s h o w n b e l o w in T a b l e 1 a n d F i g u r e 2 .
T h e p o r t I / O is p r o g r a m m e d b y w r i t i n g t h e c o r r e s p o n d i n g b i t i n t h e D D R to a " 1 " f o r
o u t p u t a n d a " 0 " f o r i n p u t . In t h e o u t p u t m o d e t h e b i t s a r e l a t c h e d a n d a p p e a r o n t h e
c o r r e s p o n d i n g o u t p u t p i n s . A l l t h e D D R ' s a r e i n i t i a l i z e d to a " 0 " o n r e s e t . T h e o u t p u t
p o r t registers a r e n o t initialized o n reset. E a c h o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d
TTL load and 50pF.
O
T T L with s l e w rate control: T h e s e five outputs constitute the higher order n o n m u l t i p l e x e d a d d r e s s lines. E a c h o u t p u t is capable o f d r i v i n g o n e s t a n d a r d T T L l o a d a n d
130pF.
I/O
T T L with slew rate c o n t r o l : T h e s e b i - d i r e c t i o n a l l i n e s c o n s t i t u t e t h e l o w e r o r d e r
a d d r e s s e s and data. T h e s e lines are multiplexed with address present a t address s t r o b e
t i m e a n d data p r e s e n t a t data s t r o b e t i m e . W h e n in t h e d a t a m o d e , t h e s e l i n e s a r e b i directional, transferring data to and from m e m o r y a n d peripheral devices a s indicated by
t h e R W _ n p i n . A s o u t p u t s , these lines are capable o f driving o n e standard T T L load and
130pF.
Timer
I
T T L : Input used to control the internal timer/counter circuitry.
T T L O s c i l l a t o r i n p u t / o u t p u t : These p i n s provide c o n t r o l i n p u t f o r the on-chip clock
o s c i l l a t o r c i r c u i t s . E i t h e r a c r y s t a l o r e x t e r n a l c l o c k i s c o n n e c t e d to t h e s e p i n s to p r o v i d e
a s y s t e m c l o c k . T h e c r y s t a l c o n n e c t i o n i s s h o w n i n F i g u r e 3 . T h e O S C 1 to b u s
transitions for system designs using oscillators slower than 5MHz is shown in Figure 4 .
OSC1, OSC2
(System Clock)
I/O
Crystal
External Clock
T h e c i r c u i t s h o w n i n F i g u r e 3 is r e c o m m e n d e d w h e n u s i n g a c r y s t a l . A n e x t e r n a l C M O S
o s c i l l a t o r is r e c o m m e n d e d w h e n u s i n g c r y s t a l s o u t s i d e t h e s p e c i f i e d r a n g e s . T o m i n i m i z e
o u t p u t distortion a n d start-up stabilization time, the crystal a n d c o m p o n e n t s should b e
mounted as close to the input pins as possible.
W h e n a n e x t e r n a l c l o c k i s u s e d , i t s h o u l d b e a p p l i e d to t h e O S C 1 i n p u t w i t h t h e O S C 2
input not connected, as shown in Figure 3 .
Table 1
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
I/O Pin Functions
R/W-n DDR
I/O Pin Functions
0
0
The I/O pin is in input mode. Data is
written into the output data latch.
0
1
Data is written into the output data latch and
output to the I/O pin.
1
0
The state of the I/O pin is read.
1
1
the I/O pin is in an output mode. The
output data latch is read.
I/O Port Circuitry and Register Configuration:
DATA DIRECTION
REGISTER
BIT
TO
AND
LATCHED
OUTPUT
DATA BIT
FROM
I/O
PIN
OUTPUT
CPU
INPUT
REG
BIT
INPUT
I/O
PIN
7
6
5
4
3
2
1
0
DATA DIRECTION
DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0
A(B)
(DDB7) (DDB6) (DDB5) (DDB4) (DDB3) (DDB2) (DDB1) (DDB0)
REGISTER
PORT A(B)
REGISTER
PIN
$0004 ($0005)
$0000 ($0001)
PA7
(PB7)
PA6
(PB6)
PA5
(PB5)
PA4
(PB4)
PA3
(PB3)
PA2
(PB2)
PA1
(PB1)
PA0
(PB0)
Figure 2. PA0-PA7/PB0-PB7 (Input/Output Lines)
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
Crystal Parameters Representative Frequencies:
5.0 MHz
50Ω
8 pF
0.02 pF
50 k
15-30 pF
15-25 pF
RS max
C0
C1
Q
COSC1
COSC2
4.0 MHz
75Ω
7 pF
0.012 pF
40 k
15-30 pF
15-25 pF
1.0 MHz
400Ω
5 pF
0.008 pF
30 k
15-40 pF
15-30 pF
Oscillator Connections:
CRYSTAL CIRCUIT
CRYSTAL OSCILLATOR CONNECTIONS
L
C1
38
OSC2
RS
39
OSC1
C0
38
NC
10 MΩ
38
OSC2
39
OSC2
39
OSC2
OSC1
ia6805E2
39
38
IA6805E2
OSC1
C OSC2
OSC1
C OSC1
tOH
tOL
OSC1 PIN
t
tOLOL
Figure 3. OSC1, OSC2 (System Clock)
OSC1 to Bus Transitions Timing Waveforms:
OSC1
AS
DS
RW_n
A[12:8]
B[7:0]
MPU
READ
DATA*
MUX ADDR
MPU READ
B[7:0]
MUX ADDR
MPU WRITE
MPU WRITE DATA
*READ DATA "LATCHED" ON DS FALL
Figure 4. OSC1, OSC2 (System Clock)
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
Functional Description
Memory:
The MPU is capable of addressing 8192 bytes of memory and I/O registers. The locations
are divided into internal memory space and external memory space as shown in Figure 5.
The first 128 bytes of memory contain internal port I/O locations, timer locations, and 112
bytes of RAM. The MPU can read from or write to any of these locations. During program
reads from on chip locations, the MPU accepts data only from the addressed on chip
location. Any read data appearing on the input bus is ignored. The shared stack area is used
during interrupts or subroutine calls. A maximum of 64 bytes of RAM is available for stack
usage. The stack pointer is set to $7f at power up. The unused bytes of the stack can be used
for data storage or temporary work locations, but care must be taken to prevent it from
being overwritten due to stacking from an interrupt or subroutine call.
0
$0000
I/O PORTS
TIMER RAM
127
ACCESS VIA
PAGE 0
DIRECT
ADDRESS
$007F
128
$0080
0
PORT A DATA REGISTER
1
PORT B DATA REGISTER
2
EXTERNAL MEMORY SPACE
3
EXTERNAL MEMORY SPACE
4
PORT A DATA DIRECTION REGISTER
5
PORT B DATA DIRECTION REGISTER
6
EXTERNAL MEMORY SPACE
7
EXTERNAL MEMORY SPACE
255
$00FF
8
TIMER DATA REGISTER
256
$0100
9
TIMER CONTROL REGISTER
10
EXTERNAL MEMORY SPACE
15
EXTERNAL MEMORY
SPACE (8064 BYTES)
16
63
64
INTERRUPT
VECTORS
8191
TIMER INTERRUPT FROM WAIT STATE ONLY
$1FF6 - $1FF7
TIMER INTERRUPT
$1FF8 - $1FF9
EXTERNAL INTERRUPT
$1FFA - $1FFB
SWI
$1FFC - $1FFD
RESET
$1FFE - $1FFF
RAM
(112 BYTES)
STACK
(64 BYTES MAX)
127
Figure 5. Memory Map
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
Registers:
The following paragraphs describe the registers contained in the MPU. Figure 6 shows the
programming model and Figure 7 shows the interrupt stacking order.
7
0
A
ACCUMULATOR
7
0
X
12
8
7
0
PCL
PCH
12
0
0
0
INDEX REGISTER
0
0
PROGRAM COUNTER
6
1
0
0
SP
4
H
STACK POINTER
0
CC
I
N
Z
C
CONDITION CODE REGISTER
CARRY/BORROW
ZERO
NEGATIVE
INTERRUPT MASK
HALF CARRY
Figure 6. Programming Model
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
STACK
1
INCREASING MEMORY
ADDRESSES
R
E
T
U
R
N
1
1
CONDITION CODE
REGISTER
ACCUMULATOR
INDEX REGISTER
0
0
0
PCH
PCL
I
N
T
E
R
R
U
P
T
DECREASING MEMORY
ADDRESSES
UNSTACK
Figure 7. Interrupt Stacking Order
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
A(Accumulator):
The accumulator is an 8-bit register used to hold operands and results of arithmetic
calculations or data manipulations.
X(Index Register):
The index register is an 8-bit register used during the indexed addressing mode. It contains
an 8-bit value used to create an effective address. The index register may also be used as a
temporary storage area when not performing addressing operations.
PC(Program Counter):
The program counter is a 13-bit register that holds the address of the next instruction to be
performed by the MPU.
SP(Stack Pointer):
The stack pointer is a 13-bit register that holds the address of the next free location on the
stack. During an MPU reset or the reset stack pointer (RSP) instruction, the stack pointer is
set to location $007f. The seven most significant bits of the stack pointer are permanently
set to 0000001. They are appended to the six least significant register bits to produce an
address range down to location $0040. The stack pointer gets decremented as data is pushed
onto the stack and incremented as data is removed from the stack. The stack area of RAM is
used to store the return address on subroutine calls and the machine state during interrupts.
The maximum number of locations for the stack pointer is 64 bytes. If the stack goes
beyond this limit the stack pointer wraps around and points to its upper limit thereby losing
the previously stored information. Subroutine calls use 2 bytes of RAM on the stack and
interrupts use 5 bytes.
CC(Condition code Register):
The condition code register is a 5-bit register that indicates the results of the instruction just
executed. The bit is set if it is high. A program can individually test these bits and specific
actions can be taken as a result of their states. Following is an explanation of each bit.
C(Carry Bit):
The carry bit indicates that a carry or borrow out of the Arithmetic Logical Unit (ALU)
occurred during the last arithmetic instruction. This bit is also modified during bit test, shift,
rotate, and branch types of instructions.
Z(Zero Bit):
The zero bit indicates the result of the last arithmetic, logical, or data manipulation was zero.
N(Negative Bit):
The negative bit indicates the result to the last arithmetic, logical, or data manipulation was
negative (bit 7 in the result is high).
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
I(Interrupt Mask Bit)
The interrupt mask bit indicates that both the external interrupt and the timer interrupt are
disabled (masked). If an interrupt occurs while this bit is set, the interrupt is latched and is
processed as soon as the interrupt bit is cleared.
H(Half Carry Bit)
The half carry bit indicates that a carry occurred between bits 3 and 4 of the ALU during an
ADD or ADC operation.
Resets:
The MPU can be reset by initial power up or by the external reset pin (reset_n).
POR(Power On Reset)
Power on reset occurs on initial power up. It is strictly for power initialization conditions
and should not be used to detect drops in the power supply voltage. There is a 1920 tCYC
time out delay from the time the oscillator is detected. If the reset_n pin is still low at the
end of the delay, the MPU will remain in the reset state until the external pin goes high.
Reset_n
The reset_n pin is used to reset the MPU. The reset pin must stay low for a minimum of tcyc
to guarantee a reset. The reset_n pin is provided with a Schmitt Trigger to improve noise
immunity capability.
Interrupts:
The MPU can be interrupted with the external interrupt pin (irq_n), the internal timer
interrupt request, or the software interrupt instruction. When any of these interrupts occur,
normal processing is suspended at the end of the current instruction execution. The
processor registers are saved on the stack (stacking order shown in Figure 7) and the
interrupt mask (I) is set to prevent additional interrupts. Normal processing resumes after
the RTI instruction causes the register contents to be recovered from the stack. When the
current instruction is completed, the processor checks all pending hardware interrupts and if
unmasked (I bit clear) proceeds with interrupt processing. Otherwise, the next instruction is
fetched and executed. Masked interrupts are latched for later interrupt service. External
interrupts hold higher priority than timer interrupts. At the end of an instruction execution,
if both an external interrupt and timer interrupt are pending, the external interrupt is
serviced first. The SWI gets executed with the same priority as any other instruction if the
hardware interrupts are masked (I bit set). Figure 8 shows the Reset and Interrupt processing
flowchart.
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Microprocessor Unit
RESET
SET
Data Sheet
As of Production Version 00
I BIT
?
CLEAR
I_CC <= 1
SP <= $007F
DDRs <= 0
CLR IRQ_N LOGIC
TIMER <= $FF
PRESCALER <= $7F
TCR <= $7f
STACK
PC, X, A, CC
IRQ_N
EDGE
?
Y
IRQ_N
N
I <= 1
TCR6=0
AND
TCR7=1?
PUT 1FFE,1FFF ON
ADDRESS BUS
CLEAR
IRQ_N
REQUEST
LATCH
Y
TIMER
N
LOAD PC FROM:
SWI: 1FFC/1FFD
IRQ_N: 1FFA/1FFB
TIMER: 1FF8/1FF9
TIMER WAIT:1FF6/
1FF7
FETCH
INSTRUCTION
Y
RESET_N
PIN = LOW
IN
RESET
?
N
RESET_N
PIN = LOW
LOAD PC
FROM
1FFE/1FFF
IS FETCHED
INSTRUCTION
AN SWI?
Y
PC+1=>PC
SWI
N
EXECUTE ALL
INSTRUCTION
CYCLES
Figure 8. Reset and Interrupt Processing Flowchart
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External Interrupt:
If the external interrupt pin irq_n is “low” and the interrupt mask bit of the condition code
register is cleared, the external interrupt occurs. When the interrupt is recognized, the
current state of the machine is pushed onto the stack and the condition code register I-bit
gets set masking further interrupts until the present one is serviced. The program counter is
then loaded with the contents of the interrupt vector, which contains the location of the
interrupt service routine. The contents of $1FFA and $1FFB specify the address for this
service routine. A functional diagram of the external interrupt is shown in Figure 9 and a
mode diagram of the external interrupt is shown in Figure 10. The timing diagram shows
two different treatments of the interrupt line (irq_n) to the processor. The first shows
several interrupt lines “wire ORed” to form the interrupts at the processor. If the interrupt
line (irq_n) remains low after servicing an interrupt, the next interrupt is recognized. The
second shows single pulses on the interrupt line spaced far enough apart to be serviced. The
minimum time between pulses is a function of the length of the interrupt service. After a
pulse occurs, the next pulse should not occur until an RTI has occurred. The time between
pulses (tILIL) is obtained by adding 20 instruction cycles to the total number of cycles it takes
to complete the service routine including the RTI instruction.
VDD
D
INTERRUPT PIN
EXTERNAL
INTERUPT
REQUEST
Q
C
Q
I BIT (CCR)
R
POWER-ON RESET
EXTERNAL RESET
EXTERNAL INTERRUPT
BEING SERVICED
Figure 9. Interrupt Functional Diagram
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Figure 10. Interrupt Mode Diagram
Timer Interrupt:
If the timer mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are
cleared, each time the timer decrements to zero ($01 to $00 transition) an interrupt request is
generated. When the interrupt is recognized, the current state of the machine is pushed onto
the stack and the condition code register I-bit gets set masking further interrupts until the
present one is serviced. The program counter is then loaded with the contents of the timer
interrupt vector, which contains the location of the timer interrupt service routine. The
contents of $1FF8 and $1FF9 specify the address for this service routine. If the MPU is in
the wait mode and a timer interrupt occurs, then the contents of $1FF6 and $1FF7 specify
the service routine. When the timer interrupt service routine is complete, the software
executes an RTI instruction to restore the machine state and starts executing the interrupt
program.
Software Interrupt:
Software interrupt is an executable instruction regardless of the state of the interrupt mask
bit (I) in the condition code register. SWI is similar to hardware interrupts. It executes after
the other interrupts if the interrupt mask bit is zero. The contents of $1FFC and $1FFD
specify the address for this service routine .
Low Power Modes:
The low power modes consist of the stop instruction and the wait instruction.
following paragraphs explain these modes of operation.
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Stop Modes:
The stop instruction places the MPU in low power consumption mode. The stop instruction
disables clocking of most internal registers. Timer control register bits 6 and 7 (TCR6 and
TCR7) are altered to remove any pending timer interrupt requests and to disable any further
timer interrupts. The DS and AS output lines go “low” and the RW_n line goes “high”. The
multiplexed address/data bus goes to the data input state. The high order address lines
remain at the address of the next instruction. External interrupts are enabled by clearing the
I bit in the condition code register. All other registers, memory, and I/O remain unaltered.
Only an external interrupt or reset will bring the MPU out of the stop mode. Figure 11
shows a flowchart of the stop function.
STOP
TCR BIT 7 <= 0
TCR BIT 6 <= 1
CLEAR I BIT
N
RESET?
Y
N
EXTERNAL
INTERRUPT?
Y
FETCH EXTERNAL
INTERRUPT
OR RESET VECTOR
Figure 11. STOP Function Flowchart
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Wait Mode:
The wait instruction places the MPU in low power consumption mode. The wait instruction
disables clocking of most internal registers. The DS and AS output lines go “low” and the
RW_n line goes “high”. The multiplexed address/data bus goes to the data input state. The
high order address lines remain at the address of the next instruction. External interrupts are
enabled by clearing the I bit in the condition code register. All other registers, memory, and
I/O remain unaltered. Only an external interrupt, timer interrupt, or reset will bring the
MPU out of the wait mode. The timer may be enabled to allow a periodic exit from the wait
mode. If an external and a timer interrupt occur at the same time, the external interrupt is
serviced first. Then, if the timer interrupt request is not cleared in the external interrupt
routine, the normal timer interrupt (not the timer wait interrupt) is serviced since the MPU is
no longer in the wait mode. Figure 12 shows a flowchart of the wait function.
WAIT
OSCILLATOR
ACTIVE,
CLEAR I BIT,
TIMER CLOCK
ACTIVE,
N
RESET?
Y
EXTERNAL
INTERRUPT?
Y
N
TIMER
INTERRUPT?
(TCR BIT7
= 1)
N
Y
TCR
BIT 6 = 0?
N
Y
FETCH EXTERNAL
INTERRUPT, RESET,
OR TIMER
INTERRUPT (FROM
WAIT MODE ONLY)
Figure 12. WAIT Function Flowchart
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Timer:
The MPU contains a single 8-bit software programmable counter driven by a 7-bit software
programmable prescaler. The counter may be loaded under program control and decrements
to zero. When the counter decrements to zero, the timer interrupt request bit in the timer
control register (TCR7) is set. Figure 13 shows a block diagram of the timer. If the timer
mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are cleared, an
interrupt request is generated. After completion of the current instruction, the current state
of the machine is pushed onto the stack. The timer interrupt vector address is then fetched
from locations $1FF8 and $1FF9 and the interrupt routine is executed, unless the MPU was
in the WAIT mode in which case the interrupt vector address in locations $1FF6 and $1FF7
is fetched. Power-On-Reset causes the counter to set to $FF.
NOTE: 1. Prescaler and counter are clocked on the falling edge of the internal
clock (AS) or external input.
2. Counter is written to during Data Strobe (DS) and counts down continuously.
TIMER
(PIN 37)
TIMER_n
EXT
CLK
PRESCALER
(7 BITS)
COUNTER
(8 BITS)
INTERRUPT
CONTROL
2 - TO - 1
MUX
INTERRUPT
READ
WRITE
INT
CLK
ENABLE /
DISABLE_n
INTERNAL_n / EXTERNAL
INTERNAL
CLOCK
TCR4
TCR5
TCR3 TCR2
TCR1
TCR0
SETTING TCR3 CLEARS
PRESCALER TO ÷ 1
SOFTWARE FUNCTIONS
Figure 13. Timer Block Diagram
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The counter continues to count past zero, falling from $00 to $FF, and continues. The
processor may read the counter at any time without disturbing the count by reading the
timer data register (TDR). This allows a program to determine the length of time since a
timer interrupt has occurred. The timer interrupt request bit remains set until cleared by
software. The interrupt is lost if this happens before the timer interrupt is serviced.
The prescaler is a 7-bit divider used to extend the maximum length of the timer. TCR bits
0-2 are programmed to choose the appropriate prescaler output, which is used as the count
input. The prescaler is cleared by writing a “1” into TCR bit 3, which avoids truncation
errors. The processor cannot write to or read from the prescaler.
Timer Input Mode 1:
When TCR4 = 0 and TCR5 = 0, the input to the timer is from an internal clock and the
timer input is disabled. The internal clock mode can be used for periodic interrupt
generation as well as a reference for frequency and event measurement. The internal clock is
the instruction cycle clock and is coincident with Address Strobe (AS) except during the wait
instruction where it goes low. During the wait instruction the internal clock to the timer
continues to run at its normal rate.
Timer Input Mode 2:
When TCR4 = 1 and TCR5 = 0, the internal clock and timer input signal are ANDed to
form the timer input. This mode can be used to measure external pulse widths. The external
pulse turns on the internal clock for the duration of the pulse. The count accuracy in this
mode is ±1 clock. Accuracy improves with longer input pulse widths.
Timer Input Mode 3:
When TCR4 = 0 and TCR5 = 1, all inputs to the timer are disabled.
Timer Input Mode 4:
When TCR4 = 1 and TCR5 = 1, the internal clock input to the timer is disabled and the
timer input then comes from the external TIMER pin. The external clock can be used to
count external events as well as to provide an external frequency for generating periodic
interrupts.
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TCR (Timer Control Register ($0009)):
An 8-bit register that controls functions such as configuring operation mode, setting ratio of
the prescaler, and generating timer interrupt request signals. All bits except bit 3 are
read/write. Bits TCR5 - TCR0 are unaffected by reset_n.
7
6
5
4
3
2
1
0
TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
Reset:
0
1
0
0
0
0
0
0
TCR7 – Timer Interrupt Request
Used to indicate the timer interrupt when it is logic one.
1 – Set when the counter decrements to zero or under program control.
0 – Cleared on external reset, POR, STOP instruction, or program control.
TCR6 – Timer Interrupt Mask
Used to inhibit the timer interrupt.
1 – Interrupt inhibited. Set on external reset, POR, STOP instruction, or program
control.
0 – Interrupt enabled.
TCR5 – External or Internal
Selects input clock source. Unaffected by reset.
1 – External clock selected.
0 – Internal clock selected (AS) (fOSC /5).
TCR4 – Timer External Enable
Used to enable external timer pin or to enable the internal clock. Unaffected by reset.
1 – Enables external timer pin.
0 – Disables external timer pin.
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TCR3 – Prescaler Clear
Write only bit. Writing a “1” to this bit resets the prescaler to zero. A read of this location
always indicates a zero. Unaffected by reset.
TCR2, TCR1, TCR0 – Prescaler select bits
Decoded to select one of eight outputs of the prescaler. Unaffected by reset.
Prescaler
TRC2
0
0
0
0
1
1
1
1
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TRC1
0
0
1
1
0
0
1
1
TRC0
0
1
0
1
0
1
0
1
ENG21108140100
Page 18 of 31
RESET
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷128
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Instruction Set Description
The MPU has 61 basic instructions divided into 5 types. The 5 types are Register/memory, readmodify-write, branch, bit manipulation, and control.
Register/Memory Instructions:
Most of the following instructions use two operands. One is either the accumulator or the
index register and the other is obtained from memory. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register operand.
Function
Load A from memory
Load X from memory
Store A in memory
Store X in memory
Add memory to A
Add memory and carry to A
Subtract memory
Subtract memory from A with Borrow
AND memory to A
OR memory with A
Exclusive OR memory with A
Arithmetic compare A with memory
Arithmetic compare X with memory
Bit test memory with A (logical compare)
Jump Unconditional
Jump to subroutine
Mnemonic
LDA
LDX
STA
STX
ADD
ADC
SUB
SBC
AND
ORA
EOR
CMP
CPX
BIT
JMP
JSR
Read-Modify-Write Instructions:
These instructions read a memory or register location, modify or test its contents and then
write the modified value back to memory or the register.
Function
Increment
Decrement
Clear
Complement
Negate (2's complement)
Rotate Left Thru Carry
Rotate Right Thru Carry
Logical shift left
Logical shift right
Arithmetic shift right
Test for negative or zero
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Mnemonic
INC
DEC
CLR
COM
NEG
ROL
ROR
LSL
LSR
ASR
TST
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Bit Manipulation Instructions:
The MPU is capable of altering any bits residing in the first 256 bytes of memory. An
additional feature allows the software to test and branch on the state of any bit within these
locations. For test and branch instructions the value of the bit tested is placed in the carry bit
of the condition code register.
Function
Branch if bit n set
Branch if bit n clear
Set bit n
Clear bit n
Mnemonic
n = 0…7
BRSET n
BRCLR n
BSET n
BCLR n
Branch Instructions:
If a specific condition is met, the instruction branches. If not, no operation is performed.
Function
Branch always
Branch never
Branch if higher
Branch if lower or same
Branch if carry clear
Branch if higher or same
Branch if carry set
Branch if lower
Branch if not equal
Branch if equal
Branch if half carry clear
Branch if half carry set
Branch if plus
Branch if minus
Branch if interrupt mask bit clear
Branch if interrupt mask bit set
Branch if interrupt line low
Branch if interrupt line high
Branch to subroutine
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Mnemonic
BRA
BRN
BHI
BLS
BCC
BHS
BCS
BLO
BNE
BEQ
BHCC
BHCS
BPL
BMI
BMC
BMS
BIL
BIH
BSR
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Control Instructions:
Used to control processor operation during program execution. They are register reference
instructions.
Function
Transfer A to X
Transfer X to A
Set carry bit
Clear carry bit
Set interrupt mask bit
Clear interrupt mask bit
Software interrupt
Return from subroutine
Return from interrupt
Reset stack pointer
No-Operation
Stop
Wait
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Mnemonic
TAX
TXA
SEC
CLC
SEI
CLI
SWI
RTS
RTI
RSP
NOP
STOP
WAIT
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Opcode Map Summary:
The following table is an opcode map for the instructions used on the MPU. The legend
following the table shows how to use the table.
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
BTB
BSC
REL
DIR
INH
INH
IX1
IX
INH
INH
IMM
DIR
EXT
IX2
IX1
Hi
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Hi
Low
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Low
0
0000
BRSET0
5
3
BRCLR0
3
BRSET1
3
BRCLR1
3
BRSET2
3
BRCLR2
3
BSC 2
BRSET3
3
BSC 2
3
BSC 2
3
BSC 2
BRSET5
3
3
2
2
5
DIR 1
2
2
2
3
5
ROR
3
RORA
DIR 1
3
6
ROR
INH 2
3
ASRA
DIR 1
3
RORX
INH 1
5
ASR
3
5
IX1 1
3
ASRX
6
ASR
2
5
IX1 1
3
3
6
REL 2
5
BSET5
BSC 2
5
IX
1
5
BRCLR5
BTB 2
BCLR5
BSC 2
3
DECX
INH 1
INH 2
2
2
1
INH 2
5
1
BMI
REL
1
INH 2
2
ORA
IMM 2
2
2
RSP
1
INH
D
1101
5
BRCLR6
3
BTB 2
5
BCLR6
BSC 2
2
6
NOP
BSR
1
INH 2
IMM 2
3
BTB 2
BRCLR7
3
BTB 2
3
5
BCLR7
BSC 2
1
3
BIH
REL 2
5
CLR
DIR 1
Abbreviations for Address
Modes:
INH
A
X
IMM
DIR
EXT
Inherent
Accumulator
Index Register
Immediate
Direct
Extended
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CLRA
3
CLRX
INH 1
INH 2
REL
BSC
BTB
IX
IX1
IX2
Legend:
6
CLR
IX1 1
2
2
WAIT
IX 1
INH 1
Relative
Bit set/clear
Bit test and branch
Indexed, no offset
Indexed, 1 byte offset
Indexed, 2 byte offset
3
Page 22 of 31
A 1010
ORA
IX1 1
4
IX
3
5
JSR
DIR 3
LDX
IMM 2
2
5
LDX
EXT 3
4
STX
7
6
5
D 1101
JSR
JSR
JSR
IX2 2
IX1 1
IX
4
LDX
DIR 3
2
TXA
INH
6
JSR
EXT 3
IX2 2
5
STX
DIR 3
EXT 3
4
LDX
IX1 1
6
STX
4
F 1111
STX
IX1 1
IX
Opcode in Hexadecimal
F
1111
Mnemonic
Bytes
3
SUB
IX
1
E 1110
IX
5
STX
IX2 2
3
LDX
Opcode in Binary
0
0000
# of Cycles
ENG21108140100
9 1001
IX
4
ORA
IX2 2
5
3
ADC
IX1 1
5
ORA
EXT 3
4
3
LDX
INH
5
CLR
DIR 3
3
2
STOP
REL
IX2 2
4
ORA
4
ADC
2
3
4
3
2
C 1100
JMP
JMP
JMP
JMP
JMP
2
DIR 3
EXT 3
IX2 2
IX1 1
IX
2
BIL
BSC 2
5
F
1111
3
4
3
3
6
4
BMS
TST
TSTA
TSTX
TST
TST
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
BSET7
7 0111
IX
B 1011
SEI
ADD
ADD
ADD
ADD
ADD
ADD
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
5
3
3
6
5
BSET6
BMC
INC
INCA
INCX
INC
INC
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
4
STA
IX1 1
5
ADC
EXT 3
3
ORA
5
BRSET6
3
BTB 2
BRSET7
6 0110
IX
5
STA
IX2 2
4
ADC
DIR 3
2
CLI
IX
ADC
IMM 2
2
DEC
3
ADC
C
1100
E
1110
EXT 3
3
LDA
IX1 1
6
STA
5 0101
IX
4
LDA
IX2 2
5
STA
DIR 3
2
SEC
IX
IX1 1
STA
INH
5
6
DEC
EXT 3
IX1 1
5
LDA
3
BIT
2
2
3
4
5
4
3
8 1000
CLC
EOR
EOR
EOR
EOR
EOR
EOR
1
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
ROL
IX1 1
DIR 3
4
TAX
6
ROL
INH 2
3
DECA
DIR 1
3
ROLX
INH 1
5
DEC
REL 2
3
3
ROLA
DIR 1
3
BPL
BTB 2
5
5
ROL
IMM 2
4
LDA
4 0100
IX
4
BIT
IX2 2
3
AND
IX1 1
5
BIT
EXT 3
3
LDA
2
ASR
INH 2
DIR 3
2
LDA
IX
4
BIT
3 0011
IX
4
AND
IX2 2
3
CPX
IX1 1
5
AND
EXT 3
3
BIT
IMM 2
5
ROR
INH 1
5
3
BHCS
DIR 3
2
REL
5
BSC 2
IMM 2
4
AND
2 0010
IX
4
CPX
IX2 2
3
SBC
IX1 1
5
CPX
EXT 3
3
AND
BIT
REL 2
DIR 3
2
AND
IX
4
CPX
1 0001
IX
4
SBC
IX2 2
3
CMP
IX1 1
5
SBC
EXT 3
3
CPX
IMM 2
5
LSR
IX1 1
DIR 3
2
CPX
INH
4
SBC
0 0000
IX
4
CMP
IX2 2
3
SUB
IX1 1
5
CMP
EXT 3
3
IMM 2
3
REL 2
DIR 3
4
SUB
IX2 2
4
CMP
SBC
5
SUB
EXT 3
3
CMP
IMM 2
10
SWI
IX 1
6
LSR
INH 2
5
COM
IX1 1
3
LSRX
INH 1
6
COM
INH 2
3
LSRA
DIR 1
3
COMX
INH 1
5
LSR
REL 2
3
COMA
BSET4
BHCC
LSL
LSLA
LSLX
LSL
LSL
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
A
1010
2
CMP
INH
4
SUB
DIR 3
2
3
BEQ
BCLR4
BTB 2
REL 2
5
5
BRCLR4
1
COM
BNE
BSC 2
IMM 2
6
3
5
5
BRSET4
3
BTB 2
2
BCS
BCLR3
BTB 2
INH
REL
5
5
BRCLR3
IX 1
3
SUB
SBC
BCC
BSET3
BTB 2
IX1 1
2
SUB
3
5
5
6
0110
9
RTI
RTS
BLS
BCLR2
BTB 2
INH 2
5
NEG
REL
5
5
5
0101
B
1011
BSC 2
BSET2
BTB 2
INH 1
6
NEG
BHI
BCLR1
BTB 2
DIR 1
3
NEGX
3
5
5
4
0100
9
1001
BSC 2
5
3
0011
3
NEGA
BRN
BSET1
BTB 2
5
NEG
REL 2
5
BCLR0
BTB 2
3
BRA
BSC 2
5
2
0010
8
1000
BTB 2
5
1
0001
7
0111
5
BSET0
IX
Address Mode
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IA6805E2
Microprocessor Unit
AC/DC Parameters
Data Sheet
As of Production Version 00
Absolute maximum ratings:
Supply Voltage (VDD)........................….…...………….….………-0.3V to 6V
Input Pin Voltage (VIN)…………………………………...-0.3 to VDD+0.3V
Operating Temperature……………………………….……....-40°C to 85°C
Storage temperature Range (Tstg).................…........….…...…- 55°C to 150°C
ESD Protection (HBM)………………………………………………5000V
Note: The specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed
under these conditions. Operation at absolute maximum conditions for extended periods may adversely affect the long-term reliability
of the device.
DC Characteristics
(VDD=4.5 to 5.5 Vdc, VSS=0, TA=TL to TH), unless otherwise specified
DC CHARACTERISTICS
Symbol
V DD
V OL
V OH
IO L
I OH
Parameter
Supply Voltage
Output Voltage, I LOAD ≤ 2m A
Output Current
Min
Max
Unit
4.5
5.5
V
-
0.4
V
3.5
-
V
-
2
mA
-
-2
mA
V IH
High Level input Voltage
2
-
V
V IL
Low Level input Voltage
-
0.8
V
I IH
High Level input Current
-
1
µA
II L
Low Level input Current
-
-1
µA
Vt-
Schmitt Negative Threshold
1.1
-
V
Vt+
Schmitt Positive Threshold
-
1.87
V
-
5
MHz
DC
5
MHz
Frequency of Operation
f OSC
Crystal
f OSC
External Clock
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
Control Timing
VSS=0V, TA=TL to TH
Parameters
I/O Port Timing – Input Setup Time
(Figure 14)
Input Hold Time (Figure 14)
Output Delay Time (Figure 14)
Interrupt Setup Time (Figure 15)
Crystal Oscillator Startup Time
(Figure 16)
Wait Recovery Startup Time (Figure
17)
Stop Recovery Startup Time
(Figure 18)
Required Interrupt Release (Figure 15)
Timer Pulse Width (Figure 17)
Reset Pulse Width (Figure 16)
Timer Period (Figure 17)
Interrupt Pulse Width Low (Figure10)
Interrupt Pulse Period
(Figure 10)
Oscillator Cycle Period
(1/5 of tCYC) (Figure 3)
OSC1 Pulse Width High (Figure 3)
OSC1 Pulse Width Low (Figure 3)
Sym
VDD = 5.0V ±10%
f OSC = 5MHz
Min Typ Max
tPVASL
196
-
-
ns
tASLPX
tASLPV
TILASL
tOXOV
0
0.4
-
5
0
100
ns
ns
µs
ms
tIVASH
-
-
2
µs
tILASH
-
-
2
µs
tDSLIH
tTH, tTL
tRL
tTLTL
tILIH
tILIL
0.5
1.05
1.0
1.0
*
-
1.0
-
µs
tCYC
µs
tCYC
tCYC
tCYC
tOLOL
200
-
-
ns
tOH
tOL
75
75
-
-
ns
ns
Unit
*The minimum period of tILIL should not be less than the number of tCYC cycles it takes to execute the
interrupt service routine plus 20 tCYC cycles.
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
Bus Timing
VSS=0V, TA=TL to TH (Figure 19)
Num
1
2
3
4
8
9
11
16
17
18
19
21
23
24
25
26
27
28
VDD = 5.0V ±10%
f OSC = 5MHz
1 TTL, 100pF Load
Min
Max
1000
DC
587
403
4
9
97
40
11
18
0
0
204
26
185
103
190
203
185
-
Parameters
Cycle Time
Pulse Width, DS Low
Pulse Width, DS High
Clock Transition
RW_n
Non-Muxed Address Hold
RW_n Delay From DS Fall
Non-Muxed Address Delay From AS Rise
MPU Read Data Setup
Read Data Hold
MPU Data Delay, Write
Write Data Hold
Muxed Address Delay From AS Rise
Muxed Address Valid to AS Fall
Muxed Address Hold
Delay DS Fall to AS Rise
Pulse Width, AS High
Delay, AS Fall to DS Rise
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VLOW = 0.8V, VHIGH = VDD – 2.0V, VDD = 5.0V ±10%
TA = TL to TH, C L on Port = 50pF, fOSC = 5MHz
*NOTE
ADDRESS_STROBE
tPVASL
tASLPX
PORT_INPUT
tASLPV
PORT_OUTPUT
*Note: The address strobe of the first cycle of the next instruction.
Figure 14. I/O Port Timing
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
AS
n0
n1
n2
n3
n4
n5
n6
n7
n8
n9
DS
(NOTE)
TDSLIH
ADD_BUS_UNMUX[8:12]
1F (FF)
1F (FF)
NEXT OP CODE ADDRESS
INT ROUTINE
LAST ADDRESS
INT ROUTINE
STARTING ADDRESS
T ILASL
IRQ_N__TCR7_N
MUX_ADD_DATA[0:7]
SP PCL
SP-1
PCH
SP-2
X
SP-3
A
SP-4
CC
NEW PCH
80
NEW PCL
NEXT OP CODE
FA (IRQ) FB (IRQ)
1ST OP
F8 (TIMER) F9 (TIMER) INT ROUTINE
RTI
OP CODE
RW_N
Note: tDSLIH- the interrupting device must release the IRQ_N line within this time to prevent subsequent recognition
of the same interrupt.
Figure 15. IRQ_n and TCR 7_N Interrupt Timing
Figure 16. Power-On-Reset and RESET_n Timing
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
TIMER
COUNTER=$00
t TL
t TH
t TLTL
INT_EXT_CLK
TCR7
tIVASH
AS
n0
n1
n2
n3
n4
n5
n6
n7
DS
A[12:8]
ADDRESS + 1
OP CODE ADDR
OP CODE
ADDRESS
1F (FF) 1F (FF)
INT ROUTINE
STARTING
ADDRESS
ADDR + 1
B[7:0]
8F
PCL
SP
SP-1
PCH
SP-2
X
A
SP-3
SP-4
CC F6 NEW PCH F7 NEW PCL
WAIT OP CODE
1ST OP CODE
INT ROUTINE
RW_N
Figure 17. Timer Interrupt After WAIT Instruction Timing
TIMER
COUNTER=$00
t TL
t TH
t TLTL
INT_EXT_CLK
TCRB7
tIVASH
AS
n0
n1
n2
n3
n4
n5
n6
n7
DS
A[12:8]
ADDRESS + 1
OP CODE ADDR
OP CODE
ADDRESS
B[7:0]
1F (FF) 1F (FF)
INT ROUTINE
STARTING
ADDRESS
ADDR + 1
8E
SP
PCL
SP-1
PCH
STOP OP CODE
SP-2
X
SP-3
A
SP-4
CC F6 NEW PCH F7 NEW PCL
1ST OP CODE
INT ROUTINE
RW_N
Figure 18. Interrupt Recovery From STOP Instruction Timing
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Page 27 of 31
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
4
4
4
27
26
AS
1
2
DS
28
26
3
4
4
4
8
8
RW_n
11
11
16
9
9
A[12:8]
21
23
B[7:0]
WRITE
25
19
VALID
ADDR
18
24
21
VALID WRITE
DATA
25
17
23
B[7:0]
READ
VALID
ADDR
18
23
VALID READ
DATA
Figure 19. Bus Timing
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Page 28 of 31
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
Packaging Information
PDIP Packaging
TOP
E1
E
LEAD 1
IDENTIFIER
eA
1
C
eB
LEAD COUNT
DIRECTION
SIDE VIEW (WIDTH)
Lead Count
40 (in Inches)
A
D
Symbol
A1
L
B
B1
e
MIN
MAX
A
-
.200
A1
.015
-
B
.015
.020
B1
.040
.060
C
.008
.012
D
1.980
2.065
E
.580
.610
E1
.520
.560
e
SIDE VIEW (LENGTH)
eA
.580
-
eB
-
.686
L
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Page 29 of 31
.100 TYP
.100 MIN
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
PLCC Packaging
D1
E
E1
PIN 1
IDENTIFIER & ZONE
E3
2 PLCS
1.22/1.07
D
D3
TOP VIEW
BOTTOM VIEW
.81 / .66
LEAD COUNT
44 (in Millimeters)
Symbol
MIN
MAX
A
4.20
4.57
A1
2.29
3.04
D1
16.51
16.66
D2
14.99
16.00
A1
A
SEATING PLANE
.10
e
.53 / .33
.51 MIN.
D3
R 1.14 / .64
E1
16.51
16.66
E2
14.99
16.00
D2 / E2
SIDE VIEW
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Page 30 of 31
12.70 BSC
E3
12.70 BSC
e
1.27 BSC
D
17.40
17.67
E
17.40
17.65
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
Ordering Information
The IA6805E2 is available in two package styles listed in the table below. Other packages and temperature
grades may be available for additional cost and lead time.
Package Type
40 Lead Plastic DIP, 600 mil wide
44 Lead Plastic Leaded Chip Carrier
Temperature Grade
Industrial
Industrial
Order Number
IA6805E2-PDW40I
IA6805E2-PLC44I
Cross Reference to Original Manufacturers
innovASIC Part Number
Motorola Part Number
Harris Part Number
IA6805E2-PDW40I
q
q
MC146805E2CP
MC146805E2P
q
q
CDP6805E2CE
CDP6805E2E
IA6805E2-PLC44I
q
q
MC146805E2CFN
MC146805E2FN
q
q
CDP6805E2CQ
CDP6805E2Q
Errata
Production Version 00
1. Functional differences between IA6805E2 and Harris and Motorola Versions: Stop mode on
IA6805E2 will not halt oscillator. Recovery from stop will be quicker.
2. Observations:
A. Original data sheets for Motorola and Harris are inconsistent when describing timer input mode 2.
Original parts and InnovASIC will AND together the timer input with the inverse of the internal
clock (AS).
B. Original Harris part would unpredictably “pre-increment” timer counter when writing to timer
registers. IA6805E2 will not.
C. Original Harris part displays incorrect address on external pins during intermediate cycles (not a
functional problem) of multi-cycle instructions when accessing memory at page boundaries.
IA6805E2 will not.
D. Execution of illegal op-codes on the IA6805E2 will force a system reset. On the original Harris
and Motorola parts, execution of illegal op-codes would produce unpredictable results.
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