N01S818HA 1 Mb Ultra-Low Power Serial SRAM Standard SPI Interface and Multiplex DUAL and QUAD Interface http://onsemi.com Overview The ON Semiconductor serial SRAM family includes several integrated memory devices including this 1 Mb serially accessed Static Random Access Memory, internally organized as 128 K words by 8 bits. The devices are designed and fabricated using ON Semiconductor’s advanced CMOS technology to provide both high-speed performance and low power. The devices operate with a single chip select (CS) input and use a simple Serial Peripheral Interface (SPI) protocol. In SPI mode, a single data-in (SI) and data-out (SO) line is used along with the clock (SCK) to access data within the device. In DUAL mode, two multiplexed data-in/data-out (SIO0-SIO1) lines are used and in QUAD mode, four multiplexed data-in/data-out (SIO0-SIO3) lines are used with the clock to access the memory. The devices can operate over a wide temperature range of −40°C to +85°C and are available in a 8-lead TSSOP package. Features • • • • • • • • • Power Supply Range: 1.7 to 2.2 V Very Low Typical Standby Current < 1 mA Very Low Operating Current < 10 mA Simple Serial Interface ♦ Single-bit SPI Access ♦ DUAL-bit and QUAD-bit SPI-like Access Flexible Operating Modes ♦ Word Mode ♦ Page Mode ♦ Burst Mode (Full Array) High Frequency Read and Write Operation ♦ Clock Frequency 20 MHz Built-in Write Protection (CS High) High Reliability ♦ Unlimited Write Cycles These Devices are Pb−Free and are RoHS Compliant ♦ Green TSSOP TSSOP8 3x4.4 CASE 948BH PACKAGE CONFIGURATION CS 1 8 VCC SO / SIO1 2 7 HOLD / SIO3 NC / SIO2 3 6 SCK VSS 4 5 SI / SIO0 ORDERING INFORMATION Device Package Shipping† N01S818HAT22I TSSOP−8 (Pb−Free) 100 Units / Tube N01S818HAT22IT TSSOP−8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Table 1. DEVICE OPTIONS Device / Part Number N01S818HAT22I © Semiconductor Components Industries, LLC, 2013 September, 2013 − Rev. 0 Power Supply Speed Package Function 1.7 V − 2.2 V 20 MHz TSSOP−8 HOLD 1 Publication Order Number: N01S818HA/D N01S818HA Table 2. PIN NAMES Pin Name Pin Function CS Chip Select SCK Serial Clock SI / SIO0 Data Input − SPI mode Data Input/Output 0 − DUAL and QUAD mode SO / SIO1 Data Output − SPI mode Data Input/Output 1 − DUAL and QUAD mode SC / SIO2 No Connect − SPI and DUAL mode Data Input/Output 2 − QUAD mode HOLD / SIO3 HOLD Input − SPI and DUAL mode Data Input/Output 3 − QUAD mode VCC Power VSS Ground Decode Logic SCK CS SI / SIO0 Interface Circuitry Control Logic SRAM Array SO / SIO1 Data Flow Circuitry SIO2 HOLD / SIO3 Figure 1. Functional Block Diagram Table 3. CONTROL SIGNAL DESCRIPTIONS Signal Mode Used Name Description CS All Chip Select A low level selects the device and a high level puts the device in standby mode. If CS is brought high during a program cycle, the cycle will complete and then the device will enter standby mode. When CS is high, SO is in high-Z. CS must be driven low after power-up prior to any sequence being started. SCK All Serial Clock Synchronizes all activities between the memory and controller. All incoming addresses, data and instructions are latched on the rising edge of SCK. Data out is updated after the falling edge of SCK. SI SPI Serial Data In SO SPI Serial Data Out HOLD SPI and DUAL Hold SIO0 - 1 DUAL Serial Data Input / Output Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out after the falling edge of SCK. The instruction must be set after power-up to enable the DUAL access mode. SIO0 - 3 QUAD Serial Data Input / Output Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out after the falling edge of SCK. The instruction must be set after power-up to enable the QUAD access mode. Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out after the falling edge of SCK. A high level is required for normal operation. Once the device is selected and a serial sequence is started, this input may be taken low to pause serial communication without resetting the serial sequence. The pin must be brought low while SCK is low for immediate use. If SCK is not low, the HOLD function will not be invoked until the next SCK high to low transition. The device must remain selected during this sequence. SO is high-Z during the Hold time and SI and SCK are inputs are ignored. To resume operations, HOLD must be pulled high while the SCK pin is low. Lowering the HOLD input at any time will take to SO output to High-Z. http://onsemi.com 2 N01S818HA Basic Operation By programming the device through a command instruction, the dual and quad access modes may be initiated. In these modes, multiplexed I/O lines take the place of the SPI SI and SO pins and along with the CS and SCK control the device in a SPI-like, two bit (DUAL) and four bit (QUAD) wide serial manner. Once the device is put into either the DUAL or QUAD mode, the device will remain operating in that mode until powered down or the Reset Mode operation is programmed. The following table contains the possible instructions and formats. All instructions, addresses and data are transferred MSB first and LSB last. The 1 Mb serial SRAM is designed to interface directly with a standard Serial Peripheral Interface (SPI) common on many standard micro-controllers in the default state. It may also interface with other non-SPI ports by programming discrete I/O lines to operate the device. The serial SRAM contains an 8-bit instruction register and is accessed via the SI pin. The CS pin must be low and the HOLD pin must be high for the entire operation. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared, the user can assert the HOLD input and place the device into a Hold mode. After releasing the HOLD pin, the operation will resume from the point where it was held. The Hold operation is only supported in SPI and DUAL modes. Table 4. INSTRUCTION SET Instruction Command READ 03h Read data from memory starting at selected address Description WRITE 02h Write (program) data to memory starting at selected address EQIO 38h Enable QUAD I/O access EDIO 3Bh Enable DUAL I/O access RSTQIO FFh Reset from QUAD and DUAL to SPI I/O access RDMR 05h Read mode register WRMR 01h Write mode register DEVICE OPERATIONS Read Operation By continuing to provide clock cycles to the device, data can continue to be read out of the memory array in sequentially. The internal address pointer is automatically incremented to the next higher address after each byte of data is read out until the highest memory address is reached. When the highest memory address is reached, 1FFFFh, the address pointer wraps to the address 00000h. This allows the read cycles to be continued indefinitely. All Read operations are terminated by pulling CS high. The serial SRAM Read operation is started by by enabling CS low. First, the 8-bit Read instruction is transmitted to the device through the SI (or SIO0-3) pin(s) followed by the 24-bit address with the 7 MSBs of the address being “don’t care” bits and ignored. In SPI mode, after the READ instruction and address bits are sent, the data stored at that address in memory is shifted out on the SO pin after the output valid time. Additional “dummy” clock cycles (four in DUAL and two in QUAD) are required to follow the instruction and address inputs prior to the data being driven out on the SIO0-3 pins while operating in these two modes. CS SCK 0 1 2 3 4 5 6 7 8 9 Instruction SI 0 0 0 0 0 10 11 29 30 31 1 0 32 33 34 7 6 5 35 36 37 38 39 2 1 0 24−bit address 0 1 1 23 22 21 20 2 Data Out SO High−Z Figure 2. SPI Read Sequence (Single Byte) http://onsemi.com 3 4 3 N01S818HA CS SCK 0 1 2 3 4 5 6 7 8 9 23 22 10 Instruction SI 0 0 0 0 29 11 30 31 1 0 32 33 0 1 1 21 20 2 ADDR 1 42 43 44 36 37 38 39 1 0 Don’t Care Data Out from ADDR 1 7 High−Z 41 35 24−bit address 0 SO 40 34 45 46 47 48 49 50 51 52 53 54 55 1 0 ... 6 5 4 3 2 Don’t Care Data Out from ADDR 3 Data Out from ADDR 2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 Data Out from ADDR n 7 6 5 4 3 2 1 0 Figure 3. SPI Read Sequence (Sequential Bytes) CS SCK 0 1 2 3 4 5 Instruction 12 14 15 16 17 18 19 21 22 A3 23 24 25 A2 A1 A0 X X X X H0 H0 L0 L0 H1 H1 MSB C[3:0] = 03h H0 = 2 high order bits of data byte 0 L0 = 2 low order bits of data byte 0 H1 = 2 high order bits of data byte 1 L1 = 2 low order bits of data byte 1 Figure 4. DUAL Read Sequence CS SCK 0 1 2 3 Instruction SIO[3:0] C1 C0 4 5 6 7 8 9 11 12 A4 A3 A2 A1 13 14 15 16 Data out A0 X X H0 MSB Notes: 10 24−bit address A5 26 Data out MSB Notes: 20 24−bit address C3 C2 C1 C0 A11 A10 SIO[1:0] 13 L0 H1 MSB C[1:0] = 03h H0 = 4 high order bits of data byte 0 L0 = 4 low order bits of data byte 0 H1 = 4 high order bits of data byte 1 L1 = 4 low order bits of data byte 1 Figure 5. QUAD Read Sequence http://onsemi.com 4 L1 H2 L2 H3 L3 L1 L1 N01S818HA Write Operation page and the operation can be continuously looped over the 32 words of the same page. The new data will replace data already stored in the memory locations. If operating in burst mode, after the initial word of data is shifted in, additional data words can be written to the next sequential memory locations by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached, 1FFFFh, the address counter wraps to the address 00000h. This allows the burst write cycle to be continued indefinitely. Again, the new data will replace data already stored in the memory locations. All WRITE operations are terminated by pulling CS high. The serial SRAM WRITE is selected by enabling CS low. First, the 8-bit WRITE instruction is transmitted to the device followed by the 24-bit address with the 7 MSBs being don’t care. After the WRITE instruction and addresses are sent, the data to be stored in memory is shifted in on the SI pin. If operating in page mode, after the initial word of data is shifted in, additional data words can be written as long as the address requested is sequential on the same page. Simply write the data on SI pin and continue to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is written in. This can be continued for the entire page length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word address within the CS SCK 0 1 2 3 4 5 6 7 8 9 23 22 10 Instruction SI 0 0 0 0 0 11 29 30 31 32 33 2 1 0 7 6 53 54 55 24−bit address 0 1 0 21 20 34 35 36 37 38 39 1 0 Data In to ADDR 1 5 4 3 2 ADDR 1 High−Z SO 40 41 42 43 44 45 46 47 48 Data In to ADDR 2 7 6 5 4 3 49 50 51 52 Data In to ADDR 3 2 1 0 7 6 5 4 3 Data In to ADDR n 2 1 0 ... High−Z Figure 6. SPI Write Sequence http://onsemi.com 5 7 6 5 4 3 2 1 0 N01S818HA CS SCK 0 1 2 3 4 5 Instruction 12 14 15 17 18 19 A3 21 20 Data in A2 A1 A0 H0 H0 L0 L0 H1 H1 Ln Ln Hn Ln MSB MSB Notes: 16 24−bit address C3 C2 C1 C0 A11 A10 SIO1:0] 13 C[3:0] = 02h H0 = 2 high order bits of data byte 0 L0 = 2 low order bits of data byte 0 H1 = 2 high order bits of data byte 1 L1 = 2 low order bits of data byte 1 Figure 7. DUAL Write Sequence CS SCK 0 1 2 3 Instruction SIO[3:0] C1 C0 4 5 6 7 9 10 11 24−bit address A5 A4 A3 A2 A1 12 13 Data in A0 H0 MSB Notes: 8 L0 H1 L1 H2 L2 MSB C[1:0] = 02h H0 = 4 high order bits of data byte 0 L0 = 4 low order bits of data byte 0 H1 = 4 high order bits of data byte 1 L1 = 4 low order bits of data byte 1 Figure 8. QUAD Write Sequence READ Mode Register (RDMR) RDMR instruction to the device. Immediately after the instruction, the device outputs data on the SO (SIO0-3) pin(s). To complete the operation, drive CS high to terminate the register read. This instruction provides the ability to read the mode register. The register may be read at any time including during a Write operation. The Read Mode Register operation is executed by driving CS low, then sending the CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction SI 0 0 0 0 0 1 0 1 Mode Register Data Out SO High−Z 7 6 5 4 3 2 Figure 9. SPI Read Mode Register Sequence (RDMR) http://onsemi.com 6 1 0 N01S818HA CS SCK 0 1 2 3 4 Instruction SIO[1:0] 5 6 7 L L Notes: C[3:0] = 05h Mode Bits C3 C2 C1 C0 H H MSB Figure 10. DUAL Read Mode Register Sequence (RDMR) CS SCK 0 1 2 3 C1 C0 H C[1:0] = 05h Notes: Instruction Mode Bits SIO[3:0] L MSB Figure 11. QUAD Read Mode Register Sequence (RDMR) Write Mode Register (WRMR) This instruction provides the ability to write the mode register. The Write Mode Register operation is executed by driving CS low, then sending the WRMR instruction to the device. Immediately after the instruction, the data is driven to the device on the SO (SIO0-3) pin(s). To complete the operation, drive CS high to terminate the register write. CS SCK 0 1 2 3 4 5 6 7 8 9 Instruction SI 0 0 0 0 10 11 12 13 14 15 1 0 Mode Register Data In 0 0 0 1 7 6 5 4 3 2 High−Z SO Figure 12. SPI Write Mode Register Sequence CS SCK 0 1 2 3 Instruction SIO[1:0] C3 C2 C1 C0 4 5 6 7 Notes: C[3:0] = 01h Mode Bits H H L L MSB Figure 13. DUAL Write Mode Register Sequence http://onsemi.com 7 N01S818HA CS SCK 0 1 2 3 Instruction Mode Bits SIO[3:0] C1 C0 H Notes: L C[1:0] = 01h MSB Figure 14. QUAD Write Mode Register Sequence Table 5. MODE REGISTER Bit Operating Mode Bit 7 Bit 6 0 0 = Word Mode 1 0 = Page Mode 0 1 = Burst Mode (Default) 1 1 = Reserved 6 Function 0 Hold Function 1 = Hold function disabled 0 = Hold function enabled (Default) 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 Reserved 7 Power-Up State The serial SRAM enters a know state at power-up time. The device is in low-power standby state with CS = 1. A low level on CS is required to enter a active state. Table 6. ABSOLUTE MAXIMUM RATINGS Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol Rating Units VIN,OUT –0.3 to VCC +0.3 V VCC –0.3 to 5.5 V PD 500 mW TSTG –40 to 125 °C TA -40 to +85 °C TSOLDER 260°C, 10 sec °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 7. OPERATING CHARACTERISTICS (OVER SPECIFIED TEMPERATURE RANGE) Item Symbol Test Conditions Min Typ (Note 1) Units 2.2 V Supply Voltage VCC Data Retention Voltage (Note 2) VDR Input High Voltage VIH 0.7 VCC VCC + 0.3 Input Low Voltage VIL −0.3 0.2 VCC Output High Voltage VOH IOH = −0.4 mA Output Low Voltage VOL IOL = 1 mA 0.2 V ILI CS = VCC, VIN = 0 to VCC 1.0 mA Input Leakage Current 1.7 Max 1.0 V VCC − 0.2 V V Output Leakage Current ILO CS = VCC, VOUT = 0 to VCC 1.0 mA Operating Current ICC f = 20 MHz, IOUT = 0, SPI / DUAL 10 mA Standby Current ISB CS = VCC, VIN = VSS or VCC f = 20 MHz, IOUT = 0, QUAD 1. Typical values are measured at VCC = VCC Typ., TA = 25°C and are not 100% tested. 2. Typical lower limit of VCC when data will be retained in the memory array, not 100% tested. http://onsemi.com 8 10 1 5 mA N01S818HA Table 8. CAPACITANCE (Note 3) Symbol Test Conditions Max Units Input Capacitance Item CIN VIN = 0 V, f = 1 MHz, TA = 25°C Min 7 pF I/O Capacitance CI/O VIN = 0 V, f = 1 MHz, TA = 25°C 7 pF 3. These parameters are verified in device characterization and are not 100% tested. Table 9. TIMING TEST CONDITIONS Item Value Input Pulse Level 0.1 VCC to 0.9 VCC Input Rise and Fall Time 5 ns Input and Output Timing Reference Levels 0.5 VCC Output Load CL = 30 pF Operating Temperature −40 to +85°C Table 10. TIMING Item Symbol Clock Frequency fCLK Clock Period tCLK Min Max Units 20 MHz 50 ns Clock Rise Time tR 20 ns Clock Fall Time tF 20 ns Clock High Time tHI 25 ns Clock Low Time tLO 25 ns Clock Delay Time tCLD 25 ns CS Setup Time tCSS 25 ns CS Hold Time tCSH 50 ns CS Disable Time tCSD 25 ns SCK to CS tSCS 5 ns Data Setup Time tSU 10 ns Data Hold Time tHD 10 ns Output Valid From Clock Low tV 25 Output Hold Time tHO Output Disable Time tDIS HOLD Setup Time tHS 10 ns HOLD Hold Time tHH 10 ns HOLD Low to Output High-Z tHZ 10 ns HOLD High to Output Valid tHV http://onsemi.com 9 0 ns ns 20 50 ns ns N01S818HA tCSD tCLD CS tR tF tCSH tSCS tCSS SCK tSU tHD MSB in SI LSB in High−Z SO Figure 15. SPI Input Timing CS tLO tHI tCSH SCK tV SO MSB out LSB out tDIS Don’t Care SI Figure 16. SPI Output Timing CS tHS tHS tHH SCK tHH SO n+2 n+1 n High−Z tHV n tHZ SI n+2 n+1 n−1 tSU n Don’t Care HOLD Figure 17. SPI Hold Timing http://onsemi.com 10 n n−1 N01S818HA tCSD tCLD CS tR tF tCSH tSCS tCSS SCK tSU tHD MSB in SI0 LSB in Figure 18. QUAD Input Timing CS tLO tHI tCSH SCK tV SIO MSB out LSB out Figure 19. QUAD Output Timing http://onsemi.com 11 tDIS N01S818HA PACKAGE DIMENSIONS TSSOP8 3x4.4 / TSSOP8 (225 mil) CASE 948BH ISSUE O ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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