AD AD8226ARZ-RL Wide supply range, rail-to-rail output instrumentation amplifier Datasheet

Wide Supply Range, Rail-to-Rail
Output Instrumentation Amplifier
AD8226
Data Sheet
PIN CONFIGURATION
Gain set with 1 external resistor
Gain range: 1 to 1000
Input voltage goes below ground
Inputs protected beyond supplies
Very wide power supply range
Single supply: 2.2 V to 36 V
Dual supplies: ±1.35 V to ±18 V
Bandwidth (G = 1): 1.5 MHz
CMRR (G = 1): 90 dB minimum for BR models
Input noise: 22 nV/√Hz
Typical supply current: 350 μA
Specified temperature: −40°C to +125°C
8-lead SOIC and MSOP packages
AD8226
–IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
07036-001
FEATURES
TOP VIEW
(Not to Scale)
Figure 1.
Table 1. Instrumentation Amplifiers by Category1
General
Purpose
AD8220
AD8221
AD8222
AD8224
AD8228
AD8295
APPLICATIONS
Industrial process controls
Bridge amplifiers
Medical instrumentation
Portable data acquisition
Multichannel systems
1
Zero
Drift
AD8231
AD8290
AD8293
AD8553
AD8556
AD8557
Military
Grade
AD620
AD621
AD524
AD526
AD624
Low
Power
AD627
AD623
AD8223
AD8226
AD8227
AD8235/
AD8236
High Speed
PGA
AD8250
AD8251
AD8253
Visit www.analog.com for the latest instrumentation amplifiers.
GENERAL DESCRIPTION
The AD8226 is a low cost, wide supply range instrumentation
amplifier that requires only one external resistor to set any gain
between 1 and 1000.
The AD8226 is designed to work with a variety of signal
voltages. A wide input range and rail-to-rail output allow the
signal to make full use of the supply rails. Because the input
range also includes the ability to go below the negative supply,
small signals near ground can be amplified without requiring dual
supplies. The AD8226 operates on supplies ranging from ±1.35 V
to ±18 V for dual supplies and 2.2 V to 36 V for single supply.
The robust AD8226 inputs are designed to connect to realworld sensors. In addition to its wide operating range, the
AD8226 can handle voltages beyond the rails. For example,
with a ±5 V supply, the part is guaranteed to withstand ±35 V
at the input with no damage. Minimum as well as maximum
input bias currents are specified to facilitate open wire detection.
The AD8226 is perfect for multichannel, space-constrained
industrial applications. Unlike other low cost, low power
instrumentation amplifiers, the AD8226 is designed with
a minimum gain of 1 and can easily handle ±10 V signals.
With its MSOP package and 125°C temperature rating, the
AD8226 thrives in tightly packed, zero airflow designs.
The AD8226 is available in 8-lead MSOP and SOIC packages,
and is fully specified for −40°C to +125°C operation.
For a device with a similar package and performance as the
AD8226 but with gain settable from 5 to 1000, consider using
the AD8227.
Rev. C
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Technical Support
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AD8226* Product Page Quick Links
Last Content Update: 11/01/2016
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Evaluation Kits
• AD62x, AD822x, AD842x Series InAmp Evaluation Board
Documentation
Application Notes
• AN-1401: Instrumentation Amplifier Common-Mode
Range: The Diamond Plot
Data Sheet
• AD8226: Wide Supply Range, Rail-to-Rail Output
Instrumentation Amplifier Data Sheet
Technical Books
• A Designer's Guide to Instrumentation Amplifiers, 3rd
Edition, 2006
User Guides
• UG-261: Evaluation Boards for the AD62x, AD822x and
AD842x Series
Tools and Simulations
• AD8226 SPICE Macro Model
Reference Designs
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AD8226 Material Declaration
PCN-PDN Information
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CN0251
CN0253
CN0289
CN0295
CN0325
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
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AD8226
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Selection ............................................................................. 19
Applications ....................................................................................... 1
Reference Terminal .................................................................... 20
Pin Configuration ............................................................................. 1
Input Voltage Range ................................................................... 20
General Description ......................................................................... 1
Layout .......................................................................................... 20
Revision History ............................................................................... 2
Input Bias Current Return Path ............................................... 21
Specifications..................................................................................... 3
Input Protection ......................................................................... 22
Absolute Maximum Ratings ............................................................ 7
Radio Frequency Interference (RFI) ........................................ 22
Thermal Resistance ...................................................................... 7
Applications Information .............................................................. 23
ESD Caution .................................................................................. 7
Differential Drive ....................................................................... 23
Pin Configuration and Function Descriptions ............................. 8
Precision Strain Gage ................................................................. 24
Typical Performance Characteristics ............................................. 9
Driving an ADC ......................................................................... 24
Theory of Operation ...................................................................... 19
Outline Dimensions ....................................................................... 25
Architecture ................................................................................. 19
Ordering Guide .......................................................................... 25
REVISION HISTORY
9/12—Rev. B to Rev. C
7/09—Rev. 0 to Rev. A
Changes to CMRR, Voltage Offset, Input Offset Current, and
Gain Error Parameters, Table 2....................................................... 3
Changes to CMRR, Voltage Offset, and Input Offset Current
Parameters, Table 2 ........................................................................... 5
Added BRZ and BRM Models .......................................... Universal
Changes to Features Section ............................................................1
Changes to Table 1.............................................................................1
Changes to General Description Section .......................................1
Changes to Gain vs. Temperature Parameter, Output Parameter,
and Operating Range Parameter, Table 2 ...........................................4
Changes to Common-Mode Rejection Ratio (CMRR) Parameter
and to Input Offset, VOSO, Average Temperature Coefficient
Parameter, Table 3 .........................................................................5
Changes to Gain vs. Temperature Parameter, Table 3 ..................6
Changes to Gain Selection Section .............................................. 19
Changes to Reference Terminal Section and Input Voltage
Range Section.............................................................................. 20
Changes to Ordering Guide .......................................................... 25
3/11—Rev. A to Rev. B
Added AD8235/AD8236 to Table 1 ............................................... 1
Changes to Endnote 1, Table 2 ........................................................ 4
Change Endnote 2 Placement in Total Noise Equation, Table 3 ...... 5
Added G > 1 BRZ, BRMZ Max Parameter .................................... 6
Changes to Endnote 1, Table 3 ........................................................ 6
Changes to Figure 18 ...................................................................... 11
Changes to Figure 37 ...................................................................... 14
Changes to Figure 42 ...................................................................... 15
Updated Outline Dimensions ....................................................... 25
1/09—Revision 0: Initial Version
Rev. C | Page 2 of 28
Data Sheet
AD8226
SPECIFICATIONS
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 2.
Parameter
COMMON-MODE REJECTION RATIO (CMRR)
CMRR, DC to 60 Hz
G=1
G = 10
G = 100
G = 1000
CMRR at 5 kHz
G=1
G = 10
G = 100
G = 1000
NOISE
Voltage Noise
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI
G=1
G = 10
G = 100 to 1000
Current Noise
VOLTAGE OFFSET
Input Offset, VOSI
Average Temperature Coefficient
Output Offset, VOSO
Average Temperature Coefficient
Offset RTI vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current 1
Average Temperature Coefficient
Input Offset Current
Average Temperature Coefficient
REFERENCE INPUT
RIN
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G=1
G = 10
G = 100
G = 1000
Conditions
VCM = −10 V to +10 V
Min
ARZ, ARMZ
Typ
Max
Min
BRZ, BRMZ
Typ
Max
Unit
86
106
120
120
90
106
120
120
dB
dB
dB
dB
80
90
90
100
80
90
90
100
dB
dB
dB
dB
Total noise: eN = √(eNI2 + (eNO/G)2)
1 kHz
22
120
24
125
22
120
24
125
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
2
0.5
0.4
100
3
f = 1 kHz
f = 0.1 Hz to 10 Hz
Total offset voltage:
VOS = VOSI + (VOSO/G)
VS = ±5 V to ±15 V
TA = −40°C to +125°C
VS = ±5 V to ±15 V
TA = −40°C to +125°C
VS = ±5 V to ±15 V
0.5
2
2
0.5
0.4
100
3
100
2
600
10
100
115
120
120
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
5
5
5
0.5
1
50
1
400
5
100
115
120
120
20
15
30
70
27
25
35
5
5
5
µV
µV/°C
µV
µV/°C
dB
dB
dB
dB
20
15
30
70
1
1.5
2
27
25
35
0.5
0.5
0.5
5
5
100
7
100
7
nA
nA
nA
pA/°C
nA
nA
nA
pA/°C
1
0.01
1
0.01
kΩ
µA
V
V/V
%
1500
160
20
2
1500
160
20
2
kHz
kHz
kHz
kHz
−VS
Rev. C | Page 3 of 28
µV p-p
µV p-p
µV p-p
fA/√Hz
pA p-p
+VS
−VS
+VS
AD8226
Parameter
Settling Time 0.01%
G=1
G = 10
G = 100
G = 1000
Slew Rate
GAIN
Gain Range
Gain Error
G=1
G = 5 to 1000
Gain Nonlinearity
G = 1 to 10
G = 100
G = 1000
Gain vs. Temperature 2
G=1
G>1
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage Range 3
Input Overvoltage Range
OUTPUT
Output Swing
RL = 2 kΩ to Ground
Data Sheet
Conditions
10 V step
Min
ARZ, ARMZ
Typ
Max
Min
BRZ, BRMZ
Typ
Max
25
15
40
350
0.4
0.6
G=1
G = 5 to 100
G = 1 + (49.4 kΩ/RG)
1
25
15
40
350
0.4
0.6
1000
1
Unit
µs
µs
µs
µs
V/µs
V/µs
1000
V/V
0.015
0.15
0.01
0.1
%
%
10
75
750
10
75
750
ppm
ppm
ppm
5
5
−100
1
2
−100
ppm/°C
ppm/°C
ppm/°C
VOUT ±10 V
VOUT = −10 V to +10 V
RL ≥ 2 kΩ
RL ≥ 2 kΩ
RL ≥ 2 kΩ
TA = −40°C to +85°C
TA = 85°C to 125°C
TA = −40°C to +125°C
VS = ±1.35 V to +36 V
0.8||2
0.4||2
0.8||2
0.4||2
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
−VS − 0.1
−VS − 0.05
−VS − 0.15
+VS − 40
+VS − 0.8
+VS − 0.6
+VS − 0.9
−VS + 40
−VS − 0.1
−VS − 0.05
−VS − 0.15
+VS − 40
+VS − 0.8
+VS − 0.6
+VS − 0.9
−VS + 40
GΩ||pF
GΩ||pF
V
V
V
V
TA = +25°C
TA = +125°C
TA = −40°C
−VS + 0.4
−VS + 0.4
−VS + 1.2
+VS − 0.7
+VS – 1.0
+VS – 1.1
−VS + 0.4
−VS + 0.4
−VS + 1.2
+VS − 0.7
+VS – 1.0
+VS – 1.1
V
V
V
TA = +25°C
TA = +125°C
TA = −40°C
−VS + 0.2
−VS + 0.3
−VS + 0.2
+VS − 0.2
+VS − 0.3
+VS − 0.2
−VS + 0.2
−VS + 0.3
−VS + 0.2
+VS − 0.2
+VS − 0.3
+VS − 0.2
V
V
V
TA = −40°C to +125°C
−VS + 0.1
+VS − 0.1
−VS + 0.1
+VS − 0.1
V
mA
±18
425
325
525
600
+125
V
µA
µA
µA
µA
°C
RL = 10 kΩ to Ground
RL = 100 kΩ to Ground
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
TEMPERATURE RANGE
13
Dual-supply operation
TA = +25°C
TA = −40°C
TA = +85°C
TA = +125°C
±1.35
350
250
450
525
−40
1
13
±18
425
325
525
600
+125
±1.35
350
250
450
525
−40
The input stage uses pnp transistors; therefore, input bias current always flows out of the part.
The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3
Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
2
Rev. C | Page 4 of 28
Data Sheet
AD8226
+VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, specifications referred to input, unless otherwise noted.
Table 3.
Parameter
COMMON-MODE REJECTION RATIO (CMRR)
CMRR, DC to 60 Hz
G=1
G = 10
G = 100
G = 1000
CMRR at 5 kHz
G=1
G = 10
G = 100
G = 1000
NOISE
Voltage Noise
Input Voltage Noise, eNI
Output Voltage Noise, eNO
RTI
G=1
G = 10
G = 100 to 1000
Current Noise
VOLTAGE OFFSET
Input Offset, VOSI
Average Temperature Coefficient
Output Offset, VOSO
Average Temperature Coefficient
Offset RTI vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current 1
Average Temperature Coefficient
Input Offset Current
Average Temperature Coefficient
REFERENCE INPUT
RIN
IIN
Voltage Range
Reference Gain to Output
Reference Gain Error
DYNAMIC RESPONSE
Small-Signal −3 dB Bandwidth
G=1
G = 10
G = 100
G = 1000
Conditions
VCM = 0 V to 1.7 V
Min
ARZ, ARMZ
Typ
Max
Min
BRZ, BRMZ
Typ
Max
Unit
86
106
120
120
90
106
120
120
dB
dB
dB
dB
80
90
90
100
80
90
90
100
dB
dB
dB
dB
Total noise: eN = √(eNI2 + (eNO/G)2)
1 kHz
22
120
24
125
22
120
24
125
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
2.0
0.5
0.4
100
3
f = 1 kHz
f = 0.1 Hz to 10 Hz
Total offset voltage: VOS = VOSI + (VOSO/G)
TA = −40°C to +125°C
0.5
TA = −40°C to +125°C
VS = 0 V to 1.7 V
2
2.0
0.5
0.4
100
3
100
2
600
10
100
115
120
120
TA = +25°C
TA = +125°C
TA = −40°C
TA = −40°C to +125°C
TA = +25°C
TA = +125°C
TA = −40°C
TA =−40°C to +125°C
5
5
5
0.5
1
50
1
400
5
100
115
120
120
20
15
30
70
27
25
35
5
5
5
µV
µV/°C
µV
µV/°C
dB
dB
dB
dB
20
15
30
70
1
1.5
1
27
25
35
0.5
0.5
0.1
5
5
100
7
100
7
nA
nA
nA
pA/°C
nA
nA
nA
pA/°C
1
0.01
1
0.01
kΩ
µA
V
V/V
%
1500
160
20
2
1500
160
20
2
kHz
kHz
kHz
kHz
−VS
Rev. C | Page 5 of 28
µV p-p
µV p-p
µV p-p
fA/√Hz
pA p-p
+VS
−VS
+VS
AD8226
Parameter
Settling Time 0.01%
G=1
G = 10
G = 100
G = 1000
Slew Rate
GAIN
Gain Range
Gain Error
G=1
G = 5 to 1000
Gain vs. Temperature 2
G=1
G>1
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage Range 3
Input Overvoltage Range
OUTPUT
Output Swing
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
TEMPERATURE RANGE
Data Sheet
Conditions
2 V step
Min
ARZ, ARMZ
Typ
Max
Min
6
6
35
350
0.4
0.6
G=1
G = 5 to 100
G = 1 + (49.4 kΩ/RG)
1
BRZ, BRMZ
Typ
Max
6
6
35
350
0.4
0.6
1000
1
Unit
µs
µs
µs
µs
V/µs
V/µs
1000
V/V
VOUT = 0.8 V to 1.8 V
VOUT = 0.2 V to 2.5 V
0.04
0.3
0.01%
0.1%
%
%
TA = −40°C to +85°C
TA = +85°C to +125°C
TA = −40°C to +125°C
−VS = 0 V, +VS = 2.7 V to 36 V
5
5
−100
1
2
−100
ppm/°C
ppm/°C
ppm/°C
0.8||2
0.4||2
0.8||2
0.4||2
TA = +25°C
TA = −40°C
TA = +125°C
TA = −40°C to +125°C
−0.1
−0.15
−0.05
+VS − 40
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS + 40
−0.1
−0.15
−0.05
+VS − 40
+VS − 0.7
+VS − 0.9
+VS − 0.6
−VS + 40
RL = 10 kΩ to 1.35 V,
TA = −40°C to +125°C
0.1
+VS − 0.1
0.1
+VS − 0.1
13
Single-supply operation
TA = +25°C, −VS = 0 V, +VS = 2.7 V
TA = −40°C, −VS = 0 V, +VS = 2.7 V
TA = +85°C, −VS = 0 V, +VS = 2.7 V
TA = +125°C, −VS = 0 V, +VS = 2.7 V
2.2
325
250
425
475
−40
1
13
36
400
325
500
550
+125
2.2
325
250
425
475
−40
GΩ||pF
GΩ||pF
V
V
V
V
mA
36
400
325
500
550
+125
V
µA
µA
µA
µA
°C
Input stage uses pnp transistors; therefore, input bias current always flows out of the part.
The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
3
Input voltage range of the AD8226 input stage. The input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage.
See the Input Voltage Range section for more information.
2
Rev. C | Page 6 of 28
Data Sheet
AD8226
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
Supply Voltage
Output Short-Circuit Current
Maximum Voltage at −IN or +IN
Minimum Voltage at −IN or +IN
REF Voltage
Storage Temperature Range
Specified Temperature Range
Maximum Junction Temperature
ESD
Human Body Model
Charge Device Model
Machine Model
θJA is specified for a device in free air.
Rating
±18 V
Indefinite
−VS + 40 V
+VS − 40 V
±VS
−65°C to +150°C
−40°C to +125°C
140°C
Table 5. Thermal Resistance
Package
8-Lead MSOP, 4-Layer JEDEC Board
8-Lead SOIC, 4-Layer JEDEC Board
ESD CAUTION
1.5 kV
1.5 kV
100 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 7 of 28
θJA
135
121
Unit
°C/W
°C/W
AD8226
Data Sheet
–IN
1
RG
2
AD8226
8
+VS
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
TOP VIEW
(Not to Scale)
07036-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2, 3
4
5
6
7
8
Mnemonic
−IN
RG
+IN
−VS
REF
VOUT
+VS
Description
Negative Input.
Gain-Setting Pins. Place a gain resistor between these two pins.
Positive Input.
Negative Supply.
Reference. This pin must be driven by low impedance.
Output.
Positive Supply.
Rev. C | Page 8 of 28
Data Sheet
AD8226
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.
N: 2203
MEAN: 35.7649
SD: 229.378
160
MEAN: 0.041
SD: 0.224
250
140
200
100
HITS
HITS
120
80
150
100
60
40
50
–900
–600
–300
0
300
VOSO @ ±15V (µV)
600
900
0
–1.2
07036-031
0
Figure 3. Typical Distribution of Output Offset Voltage
–0.6
0
0.3
–0.3
VOSI DRIFT (µV)
0.6
0.9
1.2
Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100
MEAN: –0.57
SD: 1.5762
240
–0.9
07036-034
20
MEAN: 21.5589
SD: 0.624
180
210
150
180
120
HITS
HITS
150
120
90
90
60
60
30
–9
–6
–3
0
3
VOSO DRIFT (µV)
6
9
0
07036-032
0
18
Figure 4. Typical Distribution of Output Offset Voltage Drift
350
26
20
22
24
POSITIVE IBIAS CURRENT @ ±15V (nA)
07036-035
30
Figure 7. Typical Distribution of Input Bias Current
MEAN: –3.67283
SD: 51.1
MEAN: 0.003
SD: 0.075
300
300
250
250
HITS
150
150
100
100
0
–400
0
200
–200
VOSI @ RG PINS @ ±15V (µV)
400
0
–0.9
Figure 5. Typical Distribution of Input Offset Voltage
–0.6
–0.3
0
0.3
VOSI @ ±15V (nA)
0.6
0.9
Figure 8. Typical Distribution of Input Offset Current
Rev. C | Page 9 of 28
07036-036
50
50
07036-033
HITS
200
200
AD8226
Data Sheet
2.5
2.5
VREF = +1.35V
+1.35V, +1.9V
1.5
+0.02V, +1.3V
+2.68V, +1.2V
1.0
VREF = 0V
+2.4V, +0.8V
0.5
+2.68V, +0.3V
+0.02V, +0.3V
0
0
0.5
2.0
1.0
1.5
OUTPUT VOLTAGE (V)
2.5
1.5
+0.02V, +1.3V
+2.4V, +0.8V
0.5
+0.02V, +0.4V
+2.67V, +0.4V
+1.35, –0.3V
+0.02V, –0.3V
0
0.5
2.0
1.0
1.5
OUTPUT VOLTAGE (V)
2.5
3.0
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +2.7 V, G = 100
5
5
+0.02V, +4.3V
+2.5V, +4.3V
+0.02V, +4.3V
VREF = +1.35V
3
+0.02V, +3.0V
+4.98V, +3.0V
VREF = 0V
2
1
COMMON-MODE VOLTAGE (V)
4
+4.7V, +1.9V
+0.02V, +0.8V
+4.98V, +0.8V
+2.5V, +4.2V
VREF = +2.5V
4
3
+0.02V, +3.0V
+4.96V, +3.0V
VREF = 0V
2
1
+4.7V, +1.9V
+0.02V, +0.7V
+4.96V, +0.7V
0.5
1.0
1.5 2.0 2.5 3.0 3.5
OUTPUT VOLTAGE (V)
4.0
4.5
5.0
+2.5V, –0.3.V
+0.02V, –0.3V
–1
–0.5
5.5
0
0.5
1.0
1.5 2.0 2.5 3.0 3.5
OUTPUT VOLTAGE (V)
4.0
4.5
5.0
5.5
Figure 13. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +5 V, G = 100
Figure 10. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +5 V, G = 1
6
6
0V, +4.3V
0V, +4.2V
COMMON-MODE VOLTAGE (V)
4
2
–4.97V, +1.8V
+4.96V, +1.8V
0
–2
–4.97V, –3.0V
+4.96V, –0.3V
2
–4.96V, +1.7V
+4.96V, +1.7V
–4.96V, –3.1V
+4.96V, –3.1V
0
–2
–4
07036-039
–4
4
0V, –5.4V
–4
–2
0
2
OUTPUT VOLTAGE (V)
4
07036-042
0
07036-038
+2.5V, –0.4V
+0.02V, –0.4V
–1
–0.5
07036-041
0
0
COMMON-MODE VOLTAGE (V)
+2.67V, +1.3V
VREF = 0V
1.0
–0.5
–0.5
3.0
Figure 9. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, VS = +2.7 V, G = 1
–6
–6
VREF = +1.35V
+1.35V, +1.9V
07036-040
+1.35V, –0.4V
+0.02V, –0.4V
–1.0
–0.5
COMMON-MODE VOLTAGE (V)
2.0
0
–0.5
07036-037
COMMON-MODE VOLTAGE (V)
+0.02V, +2.0V
COMMON-MODE VOLTAGE (V)
+0.02V, +2.0V
2.0
0V, –5.3V
–6
–6
6
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±5 V, G = 1
–4
–2
0
2
OUTPUT VOLTAGE (V)
4
6
Figure 14. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±5 V, G = 100
Rev. C | Page 10 of 28
Data Sheet
AD8226
20
20
VS = ±12V
+11.95V, –6.4V
–11.95V, –6.4V
0V, –12.4V
–14.96V, –7.9V
+14.94V, –7.9V
0V, –15.4V
–20
–20
–15
–10
5
–5
0
OUTPUT VOLTAGE (V)
10
15
20
2.50
0.4
2.25
0.3
0.2
0.1
1.25
0
1.00
–0.1
IIN
–0.2
0.75
–0.3
0.50
0.25
0.2
1.75
0.1
1.50
0
1.25
–0.1
1.00
–0.2
IIN
0.75
–0.3
0
–0.6
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
Figure 19. Input Overvoltage Performance, G = 100, VS = 2.7 V
16
14
12
10
0
–0.1
–0.2
–0.3
–0.4
–0.5
–16
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0.3
INPUT CURRENT (mA)
0
–2
–4
–6
–8
–10
–12
–14
0.3
–0.5
0.1
IIN
0.4
VOUT
–0.4
0.2
2
0.5
0.25
07036-045
OUTPUT VOLTAGE (V)
8
6
4
20
–0.5
0.4
VOUT
15
0.50
0.5
VS = ±15V
G=1
–VIN = 0V
10
0.6
VS = 2.7V
G = 100
–VIN = 0V
2.00
Figure 16. Input Overvoltage Performance, G = 1, VS = 2.7 V
14
12
10
5
–5
0
OUTPUT VOLTAGE (V)
–0.4
0
–0.6
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
16
–10
2.75
0.5
OUTPUT VOLTAGE (V)
VOUT
1.50
–15
Figure 18. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±15 V, G = 100
INPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
1.75
+14.95V, –8.0V
0V, –15.4V
07036-044
2.00
0V, –12.3V
–14.95V, –8.0V
–20
–20
0.6
VS = 2.7V
G=1
–VIN = 0V
+11.95V, –6.5V
–11.95V, –6.5V
–15
Figure 15. Input Common-Mode Voltage vs. Output Voltage,
Dual Supplies, VS = ±15 V, G = 1
2.25
VS = ±12V
–5
–10
+11.95V, +5.2V
–11.95V, +5.2V
0
07036-043
–15
5
+14.95V, +6.7V
0V, +11.2V
07036-046
–5
–14.95V, +6.7V
INPUT CURRENT (mA)
0
–10
+11.95V, +5.3V
–11.95V, +5.3V
10
07036-047
5
+14.94V, +6.8V
0V, +11.3V
VS = ±15V
8
6
4
0.6
VS = ±15V
G = 100
–VIN = 0V
0.5
0.4
VOUT
0.2
0.1
2
0
–2
–4
–6
–8
–10
–12
–14
0.3
IIN
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–16
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
Figure 17. Input Overvoltage Performance, G = 1, VS = ±15 V
Figure 20. Input Overvoltage Performance, G = 100, VS = ±15 V
Rev. C | Page 11 of 28
INPUT CURRENT (mA)
+14.96V, +6.8V
0V, +14.2V
15
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
10
VS = ±15V
07036-048
0V, +14.3V
15
AD8226
Data Sheet
30
160
29
140
GAIN = 1000
–0.15V
27
26
NEGATIVE PSRR (dB)
INPUT BIAS CURRENT (nA)
28
25
24
23
22
21
+4.22V
20
120 GAIN = 100
GAIN = 10
100 GAIN = 1
80
60
40
19
18
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
COMMON-MODE VOLTAGE (V)
4.0
4.5
0
0.1
07036-049
16
–0.5
Figure 21. Input Bias Current vs. Common-Mode Voltage, VS = +5 V
60
40
1M
VS = ±15V
GAIN = 1000
50
40
GAIN (dB)
30
25
20
15
+14.18V
30
20
5
–10
0
–20
–5
–16
–12
–8
–4
0
4
8
COMMON-MODE VOLTAGE (V)
12
16
GAIN = 10
10
0
10
GAIN = 100
GAIN = 1
–30
100
Figure 22. Input Bias Current vs. Common-Mode Voltage, VS = ±15 V
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 25. Gain vs. Frequency, VS = ±15 V
160
70
140 GAIN = 1000
60
GAIN = 100
120 GAIN = 10
50
40
GAIN (dB)
GAIN = 1
80
1k
07036-015
35
07036-050
60
VS = 2.7V
GAIN = 1000
GAIN = 100
30
20
GAIN = 10
10
0
GAIN = 1
40
–10
20
1
10
100
1k
FREQUENCY (Hz)
10k
100k
1M
–30
100
07036-013
0
0.1
–20
Figure 23. Positive PSRR vs. Frequency, RTI
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 26. Gain vs. Frequency, 2.7 V Single Supply
Rev. C | Page 12 of 28
10M
07036-016
INPUT BIAS CURRENT (nA)
100k
10k
70
–15.13V
45
POSITIVE PSRR (dB)
1k
100
FREQUENCY (Hz)
Figure 24. Negative PSRR vs. Frequency
50
100
10
1
07036-014
17
Data Sheet
AD8226
150
35
140 GAIN = 100
30
INPUT BIAS CURRENT (nA)
BANDWIDTH
LIMITED
120 GAIN = 10
CMRR (dB)
100 GAIN = 1
80
60
40
VS = ±15V
VREF = 0V
–IN BIAS CURRENT
+IN BIAS CURRENT
OFFSET CURRENT
GAIN = 1000
125
25
100
20
75
15
50
10
25
INPUT OFFSET CURRENT (pA)
160
1
10
100
1k
FREQUENCY (Hz)
10k
100k
5
–45 –30 –15
07036-017
0
0.1
Figure 27. CMRR vs. Frequency, RTI
15 30 45 60 75
TEMPERATURE (°C)
90
0
105 120 135
Figure 30. Input Bias Current and Input Offset Current vs. Temperature
20
120
GAIN = 100
GAIN = 1000
10
BANDWIDTH
LIMITED
100
0
GAIN = 1
GAIN ERROR (µV/V)
GAIN = 10
80
CMRR (dB)
0
07036-012
20
60
40
–0.6
ppm/°C
–10
–20
–0.3ppm/°C
–30
–0.4ppm/°C
–40
–50
20
1
10
100
1k
FREQUENCY (Hz)
10k
100k
NORMALIZED AT 25°C
–70
–60 –40 –20
0
20
40
60
80
TEMPERATURE (°C)
07036-018
0
0.1
120
140
Figure 31. Gain Error vs. Temperature, G = 1
Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
20
3.0
2.5
10
2.0
–0.35ppm/°C
1.5
0
CMRR (µV/V)
1.0
0.5
0
–0.5
–10
0.2ppm/°C
–20
–1.0
–1.5
–30
–2.0
–3.0
0
10
20
30
40 50 60 70 80 90
WARM-UP TIME (Seconds)
100 110 120
–40
–50
–30
–10
10
30
50
70
TEMPERATURE (°C)
90
Figure 32. CMRR vs. Temperature, G = 1
Figure 29. Change in Input Offset Voltage vs. Warm-Up Time
Rev. C | Page 13 of 28
110
130
07036-052
REPRESENTATIVE DATA
NORMALIZED AT 25°C
–2.5
07036-011
CHANGE IN INPUT OFFSET VOLTAGE (µV)
100
07036-051
–60
AD8226
Data Sheet
+VS
15
–40°C
+25°C
+85°C
+105°C
+125°C
10
–0.4
OUTPUT VOLTAGE SWING (V)
INPUT VOLTAGE (V)
REFERRED TO SUPPLY VOLTAGES
–0.2
–0.6
–0.8
–VS
–0.2
–0.4
–40°C
+25°C
+85°C
+105°C
+125°C
5
0
–5
–10
2
4
6
8
10
12
SUPPLY VOLTAGE (±VS)
14
16
18
–15
100
07036-053
–0.8
Figure 36. Output Voltage Swing vs. Load Resistance
+VS
+VS
–0.1
–0.2
–0.2
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–40°C
+25°C
+85°C
+105°C
+125°C
–0.3
–0.4
+0.4
+0.3
+0.2
+0.1
–0.6
–0.8
+0.8
+0.6
+0.4
+0.2
2
4
6
8
10
12
SUPPLY VOLTAGE (±VS)
14
16
18
–VS
10µ
07036-054
–VS
Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
100µ
1m
OUTPUT CURRENT (A)
10m
Figure 37. Output Voltage Swing vs. Output Current, G = 1
8
+VS
G=1
–0.2
6
–0.4
–40°C
+25°C
+85°C
+105°C
+125°C
–0.6
–0.8
–1.0
–1.2
NONLINEARITY (2ppm/DIV)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–40°C
+25°C
+85°C
+105°C
+125°C
–0.4
+1.2
+1.0
+0.8
+0.6
+0.4
4
2
0
–2
–4
–6
2
4
6
8
10
12
SUPPLY VOLTAGE (±VS)
14
16
18
–8
–10
07036-055
–VS
Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ
–8
–6
–4
–2
0
2
4
OUTPUT VOLTAGE (V)
6
Figure 38. Gain Nonlinearity, G = 1, RL ≥ 2 kΩ
Rev. C | Page 14 of 28
8
10
07036-019
+0.2
07036-057
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
Figure 33. Input Voltage Limit vs. Supply Voltage
100k
10k
1k
LOAD RESISTANCE (Ω)
07036-056
–0.6
Data Sheet
AD8226
8
1k
G = 10
4
NOISE (nV/ Hz)
NONLINEARITY (2ppm/DIV)
6
2
0
–2
GAIN = 1
100
GAIN = 100
GAIN = 10
–4
GAIN = 1000
–6
–6
–4
–2
0
2
4
OUTPUT VOLTAGE (V)
6
8
10
1
Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ
10
100
1k
FREQUENCY (Hz)
10k
100k
07036-023
–8
BANDWIDTH
LIMITED
10
07036-020
–8
–10
Figure 42. Voltage Noise Spectral Density vs. Frequency
80
G = 100
GAIN = 1000, 200nV/DIV
40
20
GAIN = 1, 1µV/DIV
0
–20
–40
–60
–8
–6
–4
–2
0
2
4
OUTPUT VOLTAGE (V)
6
8
10
07036-021
1s/DIV
–80
–10
07036-024
NONLINEARITY (20ppm/DIV)
60
Figure 40. Gain Nonlinearity, G = 100, RL ≥ 2 kΩ
Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000
800
1k
G = 1000
NOISE (fA/ Hz)
400
200
0
–200
100
–400
–800
–10
–8
–6
–4
–2
0
2
4
OUTPUT VOLTAGE (V)
6
8
10
10
1
Figure 41. Gain Nonlinearity, G = 1000, RL ≥ 2 kΩ
10
100
FREQUENCY (Hz)
1k
Figure 44. Current Noise Spectral Density vs. Frequency
Rev. C | Page 15 of 28
10k
07036-058
–600
07036-022
NONLINEARITY (100ppm/DIV)
600
AD8226
Data Sheet
5V/DIV
15.46μs TO 0.01%
17.68µs TO 0.001%
1s/DIV
40µs/DIV
Figure 45. 0.1 Hz to 10 Hz Current Noise
07036-061
1.5pA/DIV
07036-025
0.002%/DIV
Figure 48. Large-Signal Pulse Response and Settling Time,
G = 10, 10 V Step, VS = ±15 V
30
27
VS = ±15V
21
5V/DIV
18
39.64μs TO 0.01%
58.04µs TO 0.001%
15
12
VS = +5V
07036-059
3
0
100
1k
10k
FREQUENCY (Hz)
100µs/DIV
1M
100k
Figure 49. Large-Signal Pulse Response and Settling Time,
G = 100, 10 V Step, VS = ±15 V
Figure 46. Large-Signal Frequency Response
5V/DIV
5V/DIV
349.6μs TO 0.01%
529.6µs TO 0.001%
25.38μs TO 0.01%
26.02µs TO 0.001%
0.002%/DIV
0.002%/DIV
40µs/DIV
400µs/DIV
Figure 47. Large-Signal Pulse Response and Settling Time,
G = 1, 10 V Step, VS = ±15 V
Figure 50. Large-Signal Pulse Response and Settling Time,
G = 1000, 10 V Step, VS = ±15 V
Rev. C | Page 16 of 28
07036-063
6
07036-062
0.002%/DIV
9
07036-060
OUTPUT VOLTAGE (V p-p)
24
20mV/DIV
4µs/DIV
Figure 52. Small-Signal Response, G = 10, RL = 10 kΩ, CL = 100 pF
20µs/DIV
Figure 53. Small-Signal Response, G = 100, RL = 10 kΩ, CL = 100 pF
07036-027
Figure 51. Small-Signal Response, G = 1, RL = 10 kΩ, CL = 100 pF
20mV/DIV
07036-028
4µs/DIV
20mV/DIV
100µs/DIV
07036-029
20mV/DIV
AD8226
07036-026
Data Sheet
Figure 54. Small-Signal Response, G = 1000, RL = 10 kΩ, CL = 100 pF
Rev. C | Page 17 of 28
AD8226
Data Sheet
340
SUPPLY CURRENT (µA)
330
NO LOAD
RL = 47pF
RL = 100pF
RL = 147pF
320
310
4µs/DIV
290
0
Figure 55. Small-Signal Response with Various Capacitive Loads,
G = 1, RL = ∞
40
30
SETTLED TO 0.001%
20
SETTLED TO 0.01%
10
07036-064
SETTLING TIME (µs)
50
2
4
6
8
12
10
STEP SIZE (V)
14
16
18
4
6
8
10
12
SUPPLY VOLTAGE (±VS)
14
Figure 57. Supply Current vs. Supply Voltage
60
0
2
20
Figure 56. Settling Time vs. Step Size, VS = ±15 V Dual Supplies
Rev. C | Page 18 of 28
16
18
07036-066
20mV/DIV
07036-030
300
Data Sheet
AD8226
THEORY OF OPERATION
+VS
+VS
RG
NODE 3
NODE 4
–VS
–VS
R1
24.7kΩ
R3
50kΩ
R2
24.7kΩ
NODE 2
+IN
Q1
R5
50kΩ
A1
A2
VOUT
A3
NODE 1
ESD AND
OVERVOLTAGE
PROTECTION
+VS
R4
50kΩ
ESD AND
OVERVOLTAGE
PROTECTION
Q2
+VS
–VS
R6
50kΩ
REF
–IN
–VS
VBIAS
RB
–VS
DIFFERENCE
AMPLIFIER STAGE
GAIN STAGE
07036-003
RB
Figure 58. Simplified Schematic
ARCHITECTURE
GAIN SELECTION
The AD8226 is based on the classic 3-op-amp topology. This
topology has two stages: a preamplifier to provide differential
amplification, followed by a difference amplifier to remove the
common-mode voltage. Figure 58 shows a simplified schematic
of the AD8226.
Placing a resistor across the RG terminals sets the gain of the
AD8226, which can be calculated by referring to Table 7 or by
using the following gain equation:
The first stage works as follows: in order to maintain a constant
voltage across the bias resistor RB, A1 must keep Node 3 a constant diode drop above the positive input voltage. Similarly, A2
keeps Node 4 at a constant diode drop above the negative input
voltage. Therefore, a replica of the differential input voltage is
placed across the gain-setting resistor, RG. The current that
flows across this resistance must also flow through the R1
and R2 resistors, creating a gained differential signal between
the A2 and A1 outputs. Note that, in addition to a gained
differential signal, the original common-mode signal, shifted
a diode drop up, is also still present.
The second stage is a difference amplifier, composed of A3 and
four 50 kΩ resistors. The purpose of this stage is to remove the
common-mode signal from the amplified differential signal.
The transfer function of the AD8226 is
VOUT = G(VIN+ − VIN−) + VREF
where:
G 1
49.4 kΩ
RG
RG 
49.4 kΩ
G 1
Table 7. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω)
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
249
100
49.9
Calculated Gain
1.990
4.984
9.998
19.93
50.40
100.0
199.4
495.0
991.0
The AD8226 defaults to G = 1 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the AD8226 specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain
error and gain drift are minimal.
If a gain of 5 is required and minimal gain drift is important,
consider using the AD8227. The AD8227 has a default gain of 5
that is set with internal resistors. Because all resistors are internal,
the gain drift is extremely low (<5 ppm/°C maximum).
Rev. C | Page 19 of 28
AD8226
Data Sheet
REFERENCE TERMINAL
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8226 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
For the best performance, source impedance to the REF
terminal should be kept below 2 Ω. As shown in Figure 58,
the reference terminal, REF, is at one end of a 50 kΩ resistor.
Additional impedance at the REF terminal adds to this 50 kΩ
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional RREF
can be computed by 2(50 kΩ + RREF)/(100 kΩ + RREF).
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.
REF
REF
V
+
(VDIFF )(G)
< +VS − V+ LIMIT
2
(2)
(VDIFF )(G)
+ VCM + VREF
2
< +VS − VREF _ LIMIT
2
(3)
Table 8. Input Voltage Range Constants for Various
Temperatures
Temperature
−40°C
+25°C
+85°C
+125°C
V−LIMIT
−0.55 V
−0.35 V
−0.15 V
−0.05 V
V+LIMIT
0.8 V
0.7 V
0.65 V
0.6 V
VREF_LIMIT
1.3 V
1.15 V
1.05 V
0.9 V
Recommendation for Best Performance
07036-004
OP1177
–
VCM +
The common-mode input range shifts upward with temperature. At cold temperatures, the part requires extra headroom
from the positive supply, and operation near the negative supply
has more margin. Conversely, hot temperatures require less
headroom from the positive supply, but are the worst-case
conditions for input voltages near the negative supply.
AD8226
V
(1)
Performance Across Temperature
CORRECT
AD8226
(VDIFF )(G)
> −V S + V−LIMIT
2
Figure 59. Driving the Reference Pin
INPUT VOLTAGE RANGE
Figure 9 through Figure 15 and Figure 18 show the allowable
common-mode input voltage ranges for various output voltages
and supply voltages. The 3-op-amp architecture of the AD8226
applies gain in the first stage before removing common-mode
voltage with the difference amplifier stage. Internal nodes between
the first and second stages (Node 1 and Node 2 in Figure 58)
experience a combination of a gained signal, a common-mode
signal, and a diode drop. This combined signal can be limited
by the voltage supplies even when the individual input and
output signals are not limited.
A typical part functions up to the boundaries described in this
section. However, for best performance, designing with a few
hundred millivolts extra margin is recommended. As signals
approach the boundary, internal transistors begin to saturate,
which can affect frequency and linearity performance.
If the application requirements exceed the boundaries, one
solution is to apply less gain with the AD8226, and then apply
additional gain later in the signal chain. Another option is to
use the pin-compatible AD8227.
LAYOUT
To ensure optimum performance of the AD8226 at the PCB
level, care must be taken in the design of the board layout.
The AD8226 pins are arranged in a logical manner to aid in
this task.
For most applications, Figure 9 through Figure 15 and Figure 18
provide sufficient information to achieve a good design. For
applications where a more detailed understanding is needed,
Equation 1 to Equation 3 can be used to understand how the
gain (G), common-mode input voltage (VCM), differential input
voltage (VDIFF), and reference voltage (VREF) interact. The values for
the constants, V−LIMIT, V+LIMIT, and VREF_LIMIT, are shown in Table 8.
These three formulas, along with the input and output range
specifications in Table 2 and Table 3, set the operating boundaries
of the part.
Rev. C | Page 20 of 28
–IN 1
8
+VS
RG 2
7
VOUT
RG 3
6
REF
+IN 4
5
–VS
AD8226
TOP VIEW
(Not to Scale)
Figure 60. Pinout Diagram
07036-005
INCORRECT
VCM −
Data Sheet
AD8226
Common-Mode Rejection Ratio Over Frequency
INPUT BIAS CURRENT RETURN PATH
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To keep CMRR across
frequency high, the input source impedance and capacitance of
each path should be closely matched. Additional source resistance
in the input path (for example, for input protection) should be
placed close to the in-amp inputs, which minimizes their
interaction with parasitic capacitance from the PCB traces.
The input bias current of the AD8226 must have a return path
to ground. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 62.
INCORRECT
CORRECT
+VS
+VS
AD8226
Parasitic capacitance at the gain-setting pins can also affect
CMRR over frequency. If the board design has a component
at the gain-setting pins (for example, a switch or jumper), the
part should be chosen so that the parasitic capacitance is as
small as possible.
AD8226
REF
REF
–VS
–VS
TRANSFORMER
Power Supplies
TRANSFORMER
+VS
A stable dc voltage should be used to power the instrumentation
amplifier. Note that noise on the supply pins can adversely affect
performance. For more information, see the PSRR performance
curves in Figure 23 and Figure 24.
+VS
AD8226
AD8226
REF
A 0.1 μF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 61, a 10 μF tantalum capacitor
can be used farther away from the part. In most cases, it can be
shared by other precision integrated circuits.
REF
10MΩ
–VS
–VS
THERMOCOUPLE
+VS
THERMOCOUPLE
+VS
+VS
C
0.1µF
C
10µF
C
REF
VOUT
AD8226
R
1
fHIGH-PASS = 2πRC
AD8226
+IN
AD8226
C
REF
R
REF
–IN
–VS
–VS
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
–VS
10µF
07036-006
Figure 62. Creating an IBIAS Path
0.1µF
Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground
References
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
Rev. C | Page 21 of 28
07036-007
LOAD
AD8226
Data Sheet
+VS
INPUT PROTECTION
The AD8226 has very robust inputs and typically does not
need additional input protection. Input voltages can be up to
40 V from the opposite supply rail. For example, with a +5 V
positive supply and a −8 V negative supply, the part can safely
withstand voltages from −35 V to 32 V. Unlike some other
instrumentation amplifiers, the part can handle large differential input voltages even when the part is in high gain. Figure 16,
Figure 17, Figure 19, and Figure 20 show the behavior of the
part under overvoltage conditions.
0.1µF
R
RADIO FREQUENCY INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in
applications having strong RF signals. The disturbance can appear
as a small dc offset voltage. High frequency signals can be filtered
with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 63. The filter limits the
input signal bandwidth according to the following relationship:
FilterFrequency DIFF 
FilterFrequency CM 
+IN
4.02kΩ
CD
10nF
VOUT
AD8226
RG
R
REF
–IN
4.02kΩ
CC
1nF
0.1µF
10µF
–VS
07036-008
The rest of the AD8226 terminals should be kept within the
supplies. All terminals of the AD8226 are protected against ESD.
For applications where the AD8226 encounters voltages beyond
the allowed limits, external current-limiting resistors and lowleakage diode clamps such as the BAV199L, the FJH1100s, or
the SP720 should be used.
10µF
CC
1nF
Figure 63. RFI Suppression
CD affects the difference signal and CC affects the common-mode
signal. Values of R and CC should be chosen to minimize RFI.
Mismatch between the R × CC at the positive input and the R × CC
at the negative input degrades the CMRR of the AD8226. By using
a value of CD that is one magnitude larger than CC, the effect of
the mismatch is reduced and performance is improved.
1
2πR(2C D  C C )
1
2πRC C
where CD  10 CC.
Rev. C | Page 22 of 28
Data Sheet
AD8226
APPLICATIONS INFORMATION
Tips for Best Differential Output Performance
DIFFERENTIAL DRIVE
For best ac performance, an op amp with at least a 2 MHz gain
bandwidth and a 1 V/µs slew rate is recommended. Good choices
for op amps are the AD8641, AD8515, and AD820.
+IN
AD8226
+OUT
–IN
R
R
Keep trace lengths from the resistors to the inverting terminal
of the op amp as short as possible. Excessive capacitance at this
node can cause the circuit to be unstable. If capacitance cannot
be avoided, use lower value resistors.
VBIAS
+
–
OP AMP
–OUT
RECOMMENDED OP AMPS: AD8515, AD8641, AD820.
RECOMMENDED R VALUES: 5kΩ to 20kΩ.
For best linearity and ac performance, a minimum positive
supply voltage (+VS) is required. Table 9 shows the minimum
supply voltage required for optimum performance. In this mode,
VCM_MAX indicates the maximum common-mode voltage expected
at the input of the AD8226.
07036-009
REF
Figure 64. Differential Output Using an Op Amp
Figure 64 shows how to configure the AD8226 for differential output.
Table 9. Minimum Positive Supply Voltage
Temperature
Less than −10°C
−10°C to 25°C
More than 25°C
The differential output is set by the following equation:
VDIFF_OUT = VOUT+ − VOUT− = Gain × (VIN+ − VIN−)
The common-mode output is set by the following equation:
VCM_OUT = (VOUT+ − VOUT−)/2= VBIAS
The advantage of this circuit is that the dc differential accuracy
depends on the AD8226, not on the op amp or the resistors. In
addition, this circuit takes advantage of the precise control that the
AD8226 has of its output voltage relative to the reference voltage.
Although the dc performance and resistor matching of the op amp
affect the dc common-mode output accuracy, such errors are
likely to be rejected by the next device in the signal chain and
therefore typically have little effect on overall system accuracy.
Rev. C | Page 23 of 28
Equation
+VS > (VCM_MAX + VBIAS)/2 + 1.4 V
+VS > (VCM_MAX + VBIAS)/2 + 1.25 V
+VS > (VCM_MAX + VBIAS)/2 + 1.1 V
AD8226
Data Sheet
Option 1 shows the minimum configuration required to drive
a charge-sampling ADC. The capacitor provides charge to the
ADC sampling capacitor while the resistor shields the AD8226
from the capacitance. To keep the AD8226 stable, the RC time
constant of the resistor and capacitor needs to stay above 5 µs.
This circuit is mainly useful for lower frequency signals.
PRECISION STRAIN GAGE
The low offset and high CMRR over frequency of the AD8226
make it an excellent candidate for performing bridge measurements. The bridge can be connected directly to the inputs of the
amplifier (see Figure 65).
5V
350Ω
+IN
350Ω
350Ω
+
AD8226
RG
–
–IN
2.5V
Option 3 is useful for applications where the AD8226 needs to
run off a large voltage supply but drive a single-supply ADC.
In normal operation, the AD8226 output stays within the ADC
range, and the AD8616 simply buffers it. However, in a fault
condition, the output of the AD8226 may go outside the supply
range of both the AD8616 and the ADC. This is not an issue in
the circuit, however, because the 10 kΩ resistor between the two
amplifiers limits the current into the AD8616 to a safe level.
07036-010
350Ω
Option 2 shows a circuit for driving higher speed signals. It uses a
precision op amp (AD8616) with relatively high bandwidth and
output drive. This amplifier can drive a resistor and capacitor with
a much higher time constant and is therefore suited for higher
frequency applications.
0.1µF
Figure 65. Precision Strain Gage
DRIVING AN ADC
Figure 66 shows several methods for driving an ADC. The
ADuC7026 microcontroller was chosen for this example because it
contains ADCs with an unbuffered, charge-sampling architecture
that is typical of most modern ADCs. This type of architecture
typically requires an RC buffer stage between the ADC and
amplifier to work correctly.
OPTION 1: DRIVING LOW FREQUENCY SIGNALS
3.3V
AVDD
ADC0
100Ω
AD8226
REF
3.3V
100nF
ADuC7026
OPTION 2: DRIVING HIGH FREQUENCY SIGNALS
3.3V
3.3V
AD8226
REF
AD8616
10Ω
ADC1
10nF
OPTION 3: PROTECTING ADC FROM LARGE VOLTAGES
+15V
3.3V
10kΩ
AD8226
REF
AD8616
10Ω
ADC2
10nF
–15V
Figure 66. Driving an ADC
Rev. C | Page 24 of 28
AGND
07036-065
10µF
Data Sheet
AD8226
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.23
0.09
6°
0°
0.40
0.25
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 67. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 68. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
AD8226ARMZ
AD8226ARMZ-RL
AD8226ARMZ-R7
AD8226ARZ
AD8226ARZ-RL
AD8226ARZ-R7
AD8226BRMZ
AD8226BRMZ-RL
AD8226BRMZ-R7
AD8226BRZ
AD8226BRZ-RL
AD8226BRZ-R7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
Z = RoHS Compliant Part.
Rev. C | Page 25 of 28
Package Option
RM-8
RM-8
RM-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
Branding
Y18
Y18
Y18
Y19
Y19
Y19
AD8226
Data Sheet
NOTES
Rev. C | Page 26 of 28
Data Sheet
AD8226
NOTES
Rev. C | Page 27 of 28
AD8226
Data Sheet
NOTES
©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07036-0-9/12(C)
Rev. C | Page 28 of 28