ATMEL AT25DF081A-MH-Y 8-mbit 2.7v minimum serial peripheral interface serial flash memory Datasheet

Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
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•
•
•
•
•
•
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•
•
•
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– Supports SPI Modes 0 and 3
– Supports RapidS Operation
– Supports Dual-Input Program and Dual-Output Read
Very High Operating Frequencies
– 100MHz for RapidS
– 85MHz for SPI
– Clock-to-Output (tV) of 5ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– 16 Sectors of 64-Kbytes Each
Hardware Controlled Locking of Protected Sectors via WP Pin
Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
128-Byte Programmable OTP Security Register
Flexible Programming
– Byte/Page Program (1- to 256-Bytes)
Fast Program and Erase Times
– 1.0ms Typical Page Program (256 Bytes) Time
– 50ms Typical 4-Kbyte Block Erase Time
– 250ms Typical 32-Kbyte Block Erase Time
– 400ms Typical 64-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 5mA Active Read Current (Typical at 20MHz)
– 5µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 208-mil wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6mm)
8-Mbit
2.7V Minimum
Serial Peripheral
Interface Serial
Flash Memory
Atmel AT25DF081A
Preliminary
8715B–SFLSH–8/10
1.
Description
The Atmel® AT25DF081A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or
external RAM for execution. The flexible erase architecture of the AT25DF081A, with its erase granularity as small
as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM
devices.
The physical sectoring and the erase block sizes of the AT25DF081A have been optimized to meet the needs of
today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the
memory space can be used much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with
large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space
efficiency allows additional code routines and data storage segments to be added while still maintaining the same
overall device density.
The AT25DF081A also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system
can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array
securely protected. This is useful in applications where program code is patched or updated on a subroutine or
module basis, or in applications where data storage segments need to be modified without running the risk of
errant modifications to the program code segments. In addition to individual sector protection capabilities, the
AT25DF081A incorporates Global Protect and Global Unprotect features that allow the entire memory array to be
either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors
do not have to be unprotected one-by-one prior to initial programming.
To take code and data protection to the next level, the AT25DF081A incorporates a sector lockdown mechanism
that allows any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only.
This addresses the need of certain secure applications that require portions of the Flash memory array to be permanently protected against malicious attempts at altering program code, data modules, security information, or
encryption/decryption algorithms, keys, and routines. The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as unique device serialization, system-level
Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 3-volt systems, the AT25DF081A supports read, program, and erase operations
with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.
2
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
2.
Pin Descriptions and Pinouts
Table 2-1.
Pin Descriptions
Asserted
State
Type
Low
Input
SCK
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI pin
is always latched in on the rising edge of SCK, while output data on the SO pin is always
clocked out on the falling edge of SCK.
-
Input
SI (SIO)
SERIAL INPUT (SERIAL INPUT/OUTPUT): The SI pin is used to shift data into the device.
The SI pin is used for all data input including command and address sequences. Data on the
SI pin is always latched in on the rising edge of SCK.
With the Dual-Output Read Array command, the SI pin becomes an output pin (SIO) to allow
two bits of data (on the SO and SIO pins) to be clocked out on every falling edge of SCK. To
maintain consistency with SPI nomenclature, the SIO pin will be referenced as SI throughout
the document with exception to sections dealing with the Dual-Output Read Array command
in which it will be referenced as SIO.
Data present on the SI pin will be ignored whenever the device is deselected (CS is
deasserted).
-
Input/Output
SO (SOI)
SERIAL OUTPUT (SERIAL OUTPUT/INPUT): The SO pin is used to shift data out from the
device. Data on the SO pin is always clocked out on the falling edge of SCK.
With the Dual-Input Byte/Page Program command, the SO pin becomes an input pin (SOI) to
allow two bits of data (on the SOI and SI pins) to be clocked in on every rising edge of SCK.
To maintain consistency with SPI nomenclature, the SOI pin will be referenced as SO
throughout the document with exception to sections dealing with the Dual-Input Byte/Page
Program command in which it will be referenced as SOI.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
-
Output/Input
WP
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please
refer to “Protection Commands and Features” on page 17 for more details on protection
features and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to VCC whenever possible.
Low
Input
HOLD
HOLD: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold” on page 41 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the HOLD pin also be externally connected to VCC
whenever possible.
Low
Input
Symbol
Name and Function
CS
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted,
the device will be deselected and normally be placed in standby mode (not Deep PowerDown mode), and the SO pin will be in a high-impedance state. When the device is
deselected, data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
3
8715B–SFLSH–8/10
Table 2-1.
Pin Descriptions (Continued)
Asserted
State
Type
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
-
Power
GROUND: The ground reference for the power supply. GND should be connected to the
system ground.
-
Power
Symbol
Name and Function
VCC
GND
Figure 2-1.
8-SOIC (Top View)
CS
SO (SOI)
WP
GND
1
8
2
7
3
6
4
5
VCC
HOLD
SCK
SI (SIO)
1
8
2
7
3
6
4
5
VCC
HOLD
SCK
SI (SIO)
Block Diagram
Figure 3-1.
Block Diagram
CONTROL AND
PROTECTION LOGIC
CS
SCK
SI (SIO)
SO (SOI)
WP
HOLD
4
8-UDFN (Top View)
CS
SO (SOI)
WP
GND
I/O BUFFERS
AND LATCHES
SRAM
DATA BUFFER
INTERFACE
CONTROL
AND
LOGIC
Y-DECODER
ADDRESS LATCH
3.
Figure 2-2.
X-DECODER
Y-GATING
FLASH
MEMORY
ARRAY
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
4.
Memory Array
To provide the greatest flexibility, the memory array of the Atmel® AT25DF081A can be erased in four levels of
granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size,
of which each sector can be individually protected from program and erase operations. The size of the physical
sectors is optimized for both code and data storage applications, allowing both code and data segments to reside
in their own isolated regions. The Memory Architecture Diagram illustrates the breakdown of each erase level as
well as the breakdown of each physical sector.
Memory Architecture Diagram
Block Erase Detail
64KB
32KB
Block Erase
Block Erase
(D8h Command) (52h Command)
32KB
64KB
(Sector 15)
64KB
32KB
32KB
64KB
(Sector 14)
64KB
•••
•••
•••
32KB
32KB
64KB
(Sector 0)
64KB
32KB
4KB
Block Erase
(20h Command)
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
Block Address
Range
0FFFFFh
0FEFFFh
0FDFFFh
0FCFFFh
0FBFFFh
0FAFFFh
0F9FFFh
0F8FFFh
0F7FFFh
0F6FFFh
0F5FFFh
0F4FFFh
0F3FFFh
0F2FFFh
0F1FFFh
0F0FFFh
0EFFFFh
0EEFFFh
0EDFFFh
0ECFFFh
0EBFFFh
0EAFFFh
0E9FFFh
0E8FFFh
0E7FFFh
0E6FFFh
0E5FFFh
0E4FFFh
0E3FFFh
0E2FFFh
0E1FFFh
0E0FFFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0FF000h
0FE000h
0FD000h
0FC000h
0FB000h
0FA000h
0F9000h
0F8000h
0F7000h
0F6000h
0F5000h
0F4000h
0F3000h
0F2000h
0F1000h
0F0000h
0EF000h
0EE000h
0ED000h
0EC000h
0EB000h
0EA000h
0E9000h
0E8000h
0E7000h
0E6000h
0E5000h
0E4000h
0E3000h
0E2000h
0E1000h
0E0000h
00FFFFh
00EFFFh
00DFFFh
00CFFFh
00BFFFh
00AFFFh
009FFFh
008FFFh
007FFFh
006FFFh
005FFFh
004FFFh
003FFFh
002FFFh
001FFFh
000FFFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00F000h
00E000h
00D000h
00C000h
00B000h
00A000h
009000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
•••
Internal Sectoring for
Sector Protection
Function
Page Program Detail
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
1-256 Byte
Page Program
(02h Command)
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
Page Address
Range
0FFFFFh
0FFEFFh
0FFDFFh
0FFCFFh
0FFBFFh
0FFAFFh
0FF9FFh
0FF8FFh
0FF7FFh
0FF6FFh
0FF5FFh
0FF4FFh
0FF3FFh
0FF2FFh
0FF1FFh
0FF0FFh
0FEFFFh
0FEEFFh
0FEDFFh
0FECFFh
0FEBFFh
0FEAFFh
0FE9FFh
0FE8FFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0FFF00h
0FFE00h
0FFD00h
0FFC00h
0FFB00h
0FFA00h
0FF900h
0FF800h
0FF700h
0FF600h
0FF500h
0FF400h
0FF300h
0FF200h
0FF100h
0FF000h
0FEF00h
0FEE00h
0FED00h
0FEC00h
0FEB00h
0FEA00h
0FE900h
0FE800h
0017FFh
0016FFh
0015FFh
0014FFh
0013FFh
0012FFh
0011FFh
0010FFh
000FFFh
000EFFh
000DFFh
000CFFh
000BFFh
000AFFh
0009FFh
0008FFh
0007FFh
0006FFh
0005FFh
0004FFh
0003FFh
0002FFh
0001FFh
0000FFh
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
001700h
001600h
001500h
001400h
001300h
001200h
001100h
001000h
000F00h
000E00h
000D00h
000C00h
000B00h
000A00h
000900h
000800h
000700h
000600h
000500h
000400h
000300h
000200h
000100h
000000h
•••
Figure 4-1.
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
5
8715B–SFLSH–8/10
5.
Device Operation
The Atmel® AT25DF081A is controlled by a set of instructions that are sent from a host controller, commonly
referred to as the SPI Master. The SPI Master communicates with the AT25DF081A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The AT25DF081A features a dual-input program mode in which the SO pin becomes an input. Similarly, the device
also features a dual-output read mode in which the SI pin becomes an output. In the Dual-Input Byte/Page Program command description, the SO pin will be referred to as the SOI (Serial Output/Input) pin, and in the DualOutput Read Array command, the SI pin will be referenced as the SIO (Serial Input/Output) pin.
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect
to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The
AT25DF081A supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes
0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and
not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and
always output on the falling edge of SCK.
Figure 5-1.
SPI Mode 0 and 3
CS
SCK
SI
MSB
SO
6.
LSB
MSB
LSB
Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been
asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the host controller. All
opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by
deasserting the CS pin.
Opcodes not supported by the AT25DF081A will be ignored by the device and no operation will be started. The
device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being
deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address
information is sent to the device, then no operation will be performed and the device will simply return to the idle
state and wait for the next operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25DF081A memory array is 0FFFFFh, address bits A23-A20 are always
ignored by the device.
6
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
Table 6-1.
Command Listing
Command
Opcode
Clock
Frequency
Address
Bytes
Dummy
Bytes
Data
Bytes
Read Commands
1Bh
0001 1011
Up to 100MHz
3
2
1+
0Bh
0000 1011
Up to 85MHz
3
1
1+
03h
0000 0011
Up to 50MHz
3
0
1+
3Bh
0011 1011
Up to 85MHz
3
1
1+
Block Erase (4 KBytes)
20h
0010 0000
Up to 100MHz
3
0
0
Block Erase (32 KBytes)
52h
0101 0010
Up to 100MHz
3
0
0
Block Erase (64 KBytes)
D8h
1101 1000
Up to 100MHz
3
0
0
60h
0110 0000
Up to 100MHz
0
0
0
C7h
1100 0111
Up to 100MHz
0
0
0
Byte/Page Program (1 to 256 Bytes)
02h
0000 0010
Up to 100MHz
3
0
1+
Dual-Input Byte/Page Program (1 to 256 Bytes)
A2h
1010 0010
Up to 100MHz
3
0
1+
Write Enable
06h
0000 0110
Up to 100MHz
0
0
0
Write Disable
04h
0000 0100
Up to 100MHz
0
0
0
Protect Sector
36h
0011 0110
Up to 100MHz
3
0
0
Unprotect Sector
39h
0011 1001
Up to 100MHz
3
0
0
Read Array
Dual-Output Read Array
Program and Erase Commands
Chip Erase
Protection Commands
Global Protect/Unprotect
Read Sector Protection Registers
Use Write Status Register Byte 1 Command
3Ch
0011 1100
Up to 100MHz
3
0
1+
Sector Lockdown
33h
0011 0011
Up to 100MHz
3
0
1
Freeze Sector Lockdown State
34h
0011 0100
Up to 100MHz
3
0
1
Read Sector Lockdown Registers
35h
0011 0101
Up to 100MHz
3
0
1+
Program OTP Security Register
9Bh
1001 1011
Up to 100MHz
3
0
1+
Read OTP Security Register
77h
0111 0111
Up to 100MHz
3
2
1+
Read Status Register
05h
0000 0101
Up to 100MHz
0
0
1+
Write Status Register Byte 1
01h
0000 0001
Up to 100MHz
0
0
1
Write Status Register Byte 2
31h
0011 0001
Up to 100MHz
0
0
1
Reset
F0h
1111 0000
Up to 100MHz
0
0
1
Read Manufacturer and Device ID
9Fh
1001 1111
Up to 85MHz
0
0
1 to 4
Deep Power-Down
B9h
1011 1001
Up to 100MHz
0
0
0
Resume from Deep Power-Down
ABh
1010 1011
Up to 100MHz
0
0
0
Security Commands
Status Register Commands
Miscellaneous Commands
7
8715B–SFLSH–8/10
7.
Read Commands
7.1
Read Array
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock signal once the initial starting address has been specified. The device incorporates an internal
address counter that automatically increments on every clock cycle.
Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command. The use of each opcode depends
on the maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at
any clock frequency up to the maximum specified by fCLK, and the 03h opcode can be used for lower frequency
read operations up to the maximum specified by fRDLF. The 1Bh opcode allows the highest read performance possible and can be used at any clock frequency up to the maximum specified by fMAX; however, use of the 1Bh
opcode at clock frequencies above fCLK should be reserved to systems employing the Atmel RapidSTM protocol.
To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (1Bh, 0Bh, or
03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be
clocked in to specify the starting address location of the first byte to read within the memory array. Following the
three address bytes, additional dummy bytes may need to be clocked into the device depending on which opcode
is used for the Read Array operation. If the 1Bh opcode is used, then two dummy bytes must be clocked into the
device after the three address bytes. If the 0Bh opcode is used, then a single dummy byte must be clocked in after
the address bytes.
After the three address bytes (and the dummy bytes or byte if using opcodes 1Bh or 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a
byte first. When the last byte (0FFFFFh) of the memory array has been read, the device will continue reading back
at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array
to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 7-1.
Read Array – 1Bh Opcode
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
SCK
OPCODE
SI
0
0
0
1
1
ADDRESS BITS A23-A0
0
MSB
1
1
A
MSB
A
A
A
A
A
A
DON'T CARE
A
A
X
X
X
X
X
X
DON'T CARE
X
X
MSB
X
X
X
X
X
X
X
X
MSB
DATA BYTE 1
SO
HIGH-IMPEDANCE
D
MSB
8
D
D
D
D
D
D
D
D
D
MSB
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
Figure 7-2.
Read Array – 0Bh Opcode
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
OPCODE
SI
0
0
0
0
1
ADDRESS BITS A23-A0
0
1
1
MSB
A
A
A
A
A
A
A
DON'T CARE
A
A
MSB
X
X
X
X
X
X
X
X
MSB
DATA BYTE 1
SO
HIGH-IMPEDANCE
D
D
MSB
Figure 7-3.
D
D
D
D
D
D
D
D
MSB
Read Array – 03h Opcode
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE
SI
0
0
0
0
0
ADDRESS BITS A23-A0
0
MSB
1
1
A
A
A
A
A
A
A
A
A
MSB
DATA BYTE 1
SO
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
D
MSB
9
8715B–SFLSH–8/10
7.2
Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial
starting address has been specified. Unlike the standard Read Array command, however, the Dual-Output Read
Array command allows two bits of data to be clocked out of the device on every clock cycle rather than just one.
The Dual-Output Read Array command can be used at any clock frequency up to the maximum specified by fRDDO.
To perform the Dual-Output Read Array operation, the CS pin must first be asserted and the opcode of 3Bh must
be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to
specify the starting address location of the first byte to read within the memory array. Following the three address
bytes, a single dummy byte must also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data
being output on both the SO and SIO pins. The data is always output with the MSB of a byte first, and the MSB is
always output on the SO pin. During the first clock cycle, bit seven of the first data byte will be output on the SO pin
while bit six of the same data byte will be output on the SIO pin. During the next clock cycle, bits five and four of the
first data byte will be output on the SO and SIO pins, respectively. The sequence continues with each byte of data
being output after every four clock cycles. When the last byte (0FFFFFh) of the memory array has been read, the
device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a high-impedance state.
The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 7-4.
Dual-Output Read Array
CS
SCK
0
1
2
3
4
5
6
7
8
9
OPCODE
SIO
0
0
1
1
1
MSB
SO
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
ADDRESS BITS A23-A0
0
1
1
A
MSB
A
A
A
A
A
A
OUTPUT
DATA BYTE 1
DON'T CARE
A
A
X
X
X
X
X
X
X
X
D6
D4
D2
D0
D7
D5
D3
D1
D6
D4
D2
D0
D7
D5
D3
D1
D6
D4
D7
D5
MSB
HIGH-IMPEDANCE
MSB
10
OUTPUT
DATA BYTE 2
MSB
MSB
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
8.
Program and Erase Commands
8.1
Byte/Page Program
The Byte/Page Program command allows anywhere from a single byte of data to 256-bytes of data to be programmed into previously erased memory locations. An erased memory location is one that has all eight bits set to
the logical “1” state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write Enable
command must have been previously issued to the device (see “Write Enable” on page 17) to set the Write Enable
Latch (WEL) bit of the Status Register to a logical “1” state.
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the
three address bytes denoting the first byte location of the memory array to begin programming at. After the address
bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are
not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the
beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes
of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addition, if more than 256-bytes of data are sent to the device, then only the last 256-bytes sent will be latched into the
internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data
bytes sent to the device. If less than 256-bytes of data were sent to the device, then the remaining bytes within the
page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in a time of tPP or tBP if only programming a single byte.
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin
is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device will abort the operation and no data will be programmed into the memory array. In addition, if the address
specified by A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector”
on page 19) or locked down (see “Sector Lockdown” on page 25), then the Byte/Page Program command will not
be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the
Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address
being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or
because the memory location to be programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For
faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to
determine if the data bytes have finished programming. At some point before the program cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
11
8715B–SFLSH–8/10
Figure 8-1.
Byte Program
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE
SI
0
0
0
0
0
ADDRESS BITS A23-A0
0
1
A
0
MSB
SO
Figure 8-2.
A
A
A
A
A
A
DATA IN
A
A
MSB
D
D
D
D
D
D
D
D
MSB
HIGH-IMPEDANCE
Page Program
CS
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE
SI
0
0
0
0
0
ADDRESS BITS A23-A0
0
MSB
SO
12
1
0
A
MSB
A
A
A
A
A
DATA IN BYTE 1
D
D
D
D
MSB
D
D
D
DATA IN BYTE n
D
D
D
D
D
D
D
D
D
MSB
HIGH-IMPEDANCE
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
8.2
Dual-Input Byte/Page Program
The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program command and can be
used to program anywhere from a single byte of data up to 256-bytes of data into previously erased memory locations. Unlike the standard Byte/Page Program command, however, the Dual-Input Byte/Page Program command
allows two bits of data to be clocked into the device on every clock cycle rather than just one.
Before the Dual-Input Byte/Page Program command can be started, the Write Enable command must have been
previously issued to the device (see “Write Enable” on page 17) to set the Write Enable Latch (WEL) bit of the Status Register to a logical “1” state. To perform a Dual-Input Byte/Page Program command, an opcode of A2h must
be clocked into the device followed by the three address bytes denoting the first byte location of the memory array
to begin programming at. After the address bytes have been clocked in, data can then be clocked into the device
two bits at a time on both the SOI and SI pins.
The data is always input with the MSB of a byte first, and the MSB is always input on the SOI pin. During the first
clock cycle, bit seven of the first data byte would be input on the SOI pin while bit six of the same data byte would
be input on the SI pin. During the next clock cycle, bits five and four of the first data byte would be input on the SOI
and SI pins, respectively. The sequence would continue with each byte of data being input after every four clock
cycles. Like the standard Byte/Page Program command, all data clocked into the device is stored in an internal
buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are
not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the
beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes
of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addition, if more than 256-bytes of data are sent to the device, then only the last 256-bytes sent will be latched into the
internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data
bytes sent to the device. If less than 256-bytes of data were sent to the device, then the remaining bytes within the
page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in a time of tPP or tBP if only programming a single byte.
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin
is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device will abort the operation and no data will be programmed into the memory array. In addition, if the address
specified by A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector”
on page 19) or locked down (see “Sector Lockdown” on page 25), then the Byte/Page Program command will not
be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the
Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address
being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or
because the memory location to be programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For
faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to
determine if the data bytes have finished programming. At some point before the program cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
13
8715B–SFLSH–8/10
Figure 8-3.
Dual-Input Byte Program
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35
SCK
OPCODE
SI
1
0
1
0
0
0
1
0
MSB
SOI
INPUT
DATA BYTE
ADDRESS BITS A23-A0
A
A
A
A
A
A
A
A
A
D6 D4 D2 D0
MSB
HIGH-IMPEDANCE
D7 D5 D3 D1
MSB
Figure 8-4.
Dual-Input Page Program
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE
SI
1
0
1
0
0
0
MSB
SOI
INPUT
DATA BYTE 1
ADDRESS BITS A23-A0
HIGH-IMPEDANCE
1
0
A
A
A
A
A
A
A
A
A
INPUT
DATA BYTE 2
INPUT
DATA BYTE n
D6 D4 D2 D0 D6 D4 D2 D0
D6 D4 D2 D0
MSB
D7 D5 D3 D1 D7 D5 D3 D1
MSB
14
MSB
D7 D5 D3 D1
MSB
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
8.3
Block Erase
A block of 4-, 32-, or 64-Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one
of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode
of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase. Before a Block Erase
command can be started, the Write Enable command must have been previously issued to the device to set the
WEL bit of the Status Register to a logical “1” state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must
be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address
within the 4-, 32-, or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device
will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the
block is internally self-timed and should take place in a time of tBLKE.
Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded
by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values
can be either a logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored, and for a 64-Kbyte
erase, address bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded
by the device, the complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the
device will abort the operation and no erase operation will be performed.
If the address specified by A23-A0 points to a memory location within a sector that is in the protected or locked
down state, then the Block Erase command will not be executed, and the device will return to the idle state once
the CS pin has been deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an
incomplete address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory
location within the region to be erased is protected or locked down.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the
tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL
bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.
Figure 8-5.
Block Erase
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
SCK
OPCODE
SI
C
C
C
C
C
C
MSB
SO
ADDRESS BITS A23-A0
C
C
A
A
A
A
A
A
A
A
A
A
A
A
MSB
HIGH-IMPEDANCE
15
8715B–SFLSH–8/10
8.4
Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip
Erase command can be started, the Write Enable command must have been previously issued to the device to set
the WEL bit of the Status Register to a logical “1” state.
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two
opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased, no address
bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS
pin is deasserted, the device will erase the entire memory array. The erasing of the device is internally self-timed
and should take place in a time of tCHPE.
The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if
any sector of the memory array is in the protected or locked down state, then the Chip Erase command will not be
executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if the CS pin is deasserted on uneven byte boundaries or if a
sector is in the protected or locked down state.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the
tCHPE time to determine if the device has finished erasing. At some point before the erase cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.
Figure 8-6.
Chip Erase
CS
0
1
2
3
4
5
6
7
SCK
OPCODE
SI
C
C
C
C
C
C
C
C
MSB
SO
16
HIGH-IMPEDANCE
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
9.
Protection Commands and Features
9.1
Write Enable
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1”
state. The WEL bit must be set before a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, or Write Status Register command can be
executed. This makes the issuance of these commands a two step process, thereby reducing the chances of a
command being accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the
issuance of one of these commands, then the command will not be executed.
To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into
the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be
ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted
on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the
WEL bit will not change.
Figure 9-1.
Write Enable
CS
0
1
2
3
4
5
6
7
SCK
OPCODE
SI
0
0
0
0
0
1
1
0
MSB
SO
HIGH-IMPEDANCE
17
8715B–SFLSH–8/10
9.2
Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical
"0" state. With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, and Write Status Register commands will
not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to the WEL bit
section of the Status Register description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will
be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The
complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the
state of the WEL bit will not change.
Figure 9-2.
Write Disable
CS
0
1
2
3
4
5
6
7
SCK
OPCODE
SI
0
0
0
0
0
1
0
0
MSB
SO
18
HIGH-IMPEDANCE
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
9.3
Protect Sector
Every physical 64-Kbyte sector of the device has a corresponding single-bit Sector Protection Register that is used
to control the software protection of a sector. Upon device power-up, each Sector Protection Register will default to
the logical “1” state indicating that all sectors are protected and cannot be programmed or erased.
Issuing the Protect Sector command to a particular sector address will set the corresponding Sector Protection
Register to the logical “1” state. The following table outlines the two states of the Sector Protection Registers.
Table 9-1.
Value
Sector Protection Register Values
Sector Protection Status
0
Sector is unprotected and can be programmed and erased.
1
Sector is protected and cannot be programmed or erased. This is the default state.
Before the Protect Sector command can be issued, the Write Enable command must have been previously issued
to set the WEL bit in the Status Register to a logical “1”. To issue the Protect Sector command, the CS pin must
first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes designating any address within the sector to be protected. Any additional data clocked into the device will be ignored. When
the CS pin is deasserted, the Sector Protection Register corresponding to the physical sector addressed by A23A0 will be set to the logical “1” state, and the sector itself will then be protected from program and erase operations.
In addition, the WEL bit in the Status Register will be reset back to the logical “0” state.
The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin
must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation. When the device aborts the Protect Sector operation, the state of the Sector Protection Register will be
unchanged, and the WEL bit in the Status Register will be reset to a logical “0”.
As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector Protection Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the
Status Register (please refer to the Status Register description for more details). If the Sector Protection Registers
are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will reset the
WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been
deasserted.
Figure 9-3.
Protect Sector
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
SCK
OPCODE
SI
0
0
1
1
0
ADDRESS BITS A23-A0
1
MSB
SO
1
0
A
A
A
A
A
A
A
A
A
A
A
A
MSB
HIGH-IMPEDANCE
19
8715B–SFLSH–8/10
9.4
Unprotect Sector
Issuing the Unprotect Sector command to a particular sector address will reset the corresponding Sector Protection Register to the logical “0” state (see Table 9-1 for Sector Protection Register values). Every physical sector of
the device has a corresponding single-bit Sector Protection Register that is used to control the software protection
of a sector.
Before the Unprotect Sector command can be issued, the Write Enable command must have been previously
issued to set the WEL bit in the Status Register to a logical “1”. To issue the Unprotect Sector command, the CS
pin must first be asserted and the opcode of 39h must be clocked into the device. After the opcode has been
clocked in, the three address bytes designating any address within the sector to be unprotected must be clocked
in. Any additional data clocked into the device after the address bytes will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the sector addressed by A23-A0 will be reset to the logical
“0” state, and the sector itself will be unprotected. In addition, the WEL bit in the Status Register will be reset back
to the logical “0” state.
The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin
must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be
reset to a logical “0”.
As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Protection Registers
can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the Status
Register (please refer to the Status Register description for more details). If the Sector Protection Registers are
locked, then any attempts to issue the Unprotect Sector command will be ignored, and the device will reset the
WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been
deasserted.
Figure 9-4.
Unprotect Sector
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
SCK
OPCODE
SI
0
0
1
1
1
ADDRESS BITS A23-A0
0
MSB
SO
20
0
1
A
A
A
A
A
A
A
A
A
A
A
A
MSB
HIGH-IMPEDANCE
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
9.5
Global Protect/Unprotect
The Global Protect and Global Unprotect features can work in conjunction with the Protect Sector and Unprotect
Sector functions. For example, a system can globally protect the entire memory array and then use the Unprotect
Sector command to individually unprotect certain sectors and individually reprotect them later by using the Protect
Sector command. Likewise, a system can globally unprotect the entire memory array and then individually protect
certain sectors as needed.
Performing a Global Protect or Global Unprotect is accomplished by writing a certain combination of data to the
Status Register using the Write Status Register Byte 1 command (see “Write Status Register Byte 1” on page 35
for command execution details). The Write Status Register command is also used to modify the SPRL (Sector Protection Registers Locked) bit to control hardware and software locking.
To perform a Global Protect, the appropriate WP pin and SPRL conditions must be met, and the system must write
a logical “1” to bits five, four, three, and two of the first byte of the Status Register. Conversely, to perform a Global
Unprotect, the same WP and SPRL conditions must be met but the system must write a logical “0” to bits five, four,
three, and two of the first byte of the Status Register. Table 9-2 details the conditions necessary for a Global Protect or Global Unprotect to be performed.
Table 9-2.
WP
State
Valid SPRL and Global Protect/Unprotect Conditions
Current
SPRL
Value
New Write Status
Register Byte 1
Data
Bit
76543210
0x0000xx
0x0001xx
0x1110xx
0x1111xx
0
Protection Operation
New
SPRL
Value
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
0
0
0
0
0
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
1
1
1
1
1
0
1x0000xx
1x0001xx
1x1110xx
1x1111xx
No change to the current protection level. All sectors currently protected will remain protected
and all sectors currently unprotected will remain unprotected.
0
1
xxxxxxxx
The Sector Protection Registers are hard-locked and cannot be changed when the WP pin is
LOW and the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur.
In addition, the SPRL bit cannot be changed (the WP pin must be HIGH in order to change
SPRL back to a 0).
0x0000xx
0x0001xx
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
0
0
0
0
0
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
1
1
1
1
1
0x1110xx
0x1111xx
1
0
1x0000xx
1x0001xx
1x1110xx
1x1111xx
21
8715B–SFLSH–8/10
Table 9-2.
WP
State
Valid SPRL and Global Protect/Unprotect Conditions (Continued)
Current
SPRL
Value
New Write Status
Register Byte 1
Data
Bit
76543210
0x0000xx
0x0001xx
0x1110xx
0x1111xx
1
1
1x0000xx
1x0001xx
1x1110xx
1x1111xx
New
SPRL
Value
Protection Operation
No change to the current protection level. All sectors currently protected will remain
protected, and all sectors currently unprotected will remain unprotected.
The Sector Protection Registers are soft-locked and cannot be changed when the
current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur.
However, the SPRL bit can be changed back to a 0 from a 1 since the WP pin is
HIGH. To perform a Global Protect/Unprotect, the Write Status Register command
must be issued again after the SPRL bit has been changed from a 1 to a 0.
0
0
0
0
0
1
1
1
1
1
Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection Registers are not
locked), then writing a 00h to the first byte of the Status Register will perform a Global Unprotect without changing
the state of the SPRL bit. Similarly, writing a 7Fh to the first byte of the Status Register will perform a Global Protect
and keep the SPRL bit in the logical “0” state. The SPRL bit can, of course, be changed to a logical “1” by writing an
FFh if software-locking or hardware-locking is desired along with the Global Protect.
If the desire is to only change the SPRL bit without performing a Global Protect or Global Unprotect, then the system can simply write a 0Fh to the first byte of the Status Register to change the SPRL bit from a logical “1” to a
logical “0” provided the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from
a logical “0” to a logical “1” without affecting the current sector protection status (no changes will be made to the
Sector Protection Registers).
When writing to the first byte of the Status Register, bits five, four, three, and two will not actually be modified but
will be decoded by the device for the purposes of the Global Protect and Global Unprotect functions. Only bit
seven, the SPRL bit, will actually be modified. Therefore, when reading the first byte of the Status Register, bits
five, four, three, and two will not reflect the values written to them but will instead indicate the status of the WP pin
and the sector protection status. Please refer to “Read Status Register” on page 31 and Table 11-1 on page 31 for
details on the Status Register format and what values can be read for bits five, four, three, and two.
22
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
9.6
Read Sector Protection Registers
The Sector Protection Registers can be read to determine the current software protection status of each sector.
Reading the Sector Protection Registers, however, will not determine the status of the WP pin.
To read the Sector Protection Register for a particular sector, the CS pin must first be asserted and the opcode of
3Ch must be clocked in. Once the opcode has been clocked in, three address bytes designating any address
within the sector must be clocked in. After the last address byte has been clocked in, the device will begin outputting data on the SO pin during every subsequent clock cycle. The data being output will be a repeating byte of
either FFh or 00h to denote the value of the appropriate Sector Protection Register.
At clock frequencies above fCLK, the first byte of data output will not be valid. Therefore, if operating at clock frequencies above fCLK, at least two bytes of data must be clocked out from the device in order to determine the
correct status of the appropriate Sector Protection Register.
Table 9-3.
Read Sector Protection Register – Output Data
Output Data
Sector Protection Register Value
00h
Sector Protection Register value is 0 (sector is unprotected)
FFh
Sector Protection Register value is 1 (sector is protected)
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.
In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bits in the
Status Register can be read to determine if all, some, or none of the sectors are software protected (refer to “Read
Status Register” on page 31 for more details).
Figure 9-5.
Read Sector Protection Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE
SI
0
0
1
1
1
ADDRESS BITS A23-A0
1
MSB
0
0
A
A
A
A
A
A
A
A
A
MSB
DATA BYTE
SO
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
D
MSB
23
8715B–SFLSH–8/10
9.7
Protected States and the Write Protect (WP) Pin
The WP pin is not linked to the memory array itself and has no direct effect on the protection status or lockdown
status of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection Registers
Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device. For hardware
locking to be active, two conditions must be met-the WP pin must be asserted and the SPRL bit must be in the logical “1” state.
When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit itself is also locked.
Therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be
locked in the unprotected state. These states cannot be changed as long as hardware locking is active, so the Protect Sector, Unprotect Sector, and Write Status Register commands will be ignored. In order to modify the
protection status of a sector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must be
reset back to the logical “0” state using the Write Status Register command. When resetting the SPRL bit back to a
logical “0”, it is not possible to perform a Global Protect or Global Unprotect at the same time since the Sector Protection Registers remain soft-locked until after the Write Status Register command has been executed.
If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”, the only way to reset
the bit back to the logical “0” state is to power-cycle the device. This allows a system to power-up with all sectors
software protected but not hardware locked. Therefore, sectors can be unprotected and protected as needed and
then hardware locked at a later time by simply setting the SPRL bit in the Status Register.
When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the SPRL bit in the Status Register can still be set to a logical “1” to lock the Sector Protection Registers. This provides a software locking ability
to prevent erroneous Protect Sector or Unprotect Sector commands from being processed. When changing the
SPRL bit to a logical “1” from a logical “0”, it is also possible to perform a Global Protect or Global Unprotect at the
same time by writing the appropriate values into bits five, four, three, and two of the first byte of the Status
Register.
Tables 9-4 and 9-5 detail the various protection and locking states of the device.
Table 9-4.
Sector Protection Register States
WP
Sector Protection Register
n(1)
Sector
n(1)
0
Unprotected
1
Protected
X
(Don't Care)
Note:
1. “n” represents a sector number
Table 9-5.
24
Hardware and Software Locking
WP
SPRL
0
0
0
1
1
0
1
1
Locking
Hardware
Locked
Software
Locked
SPRL Change Allowed
Sector Protection Registers
Can be modified from 0 to 1
Unlocked and modifiable using the Protect and Unprotect
Sector commands. Global Protect and Unprotect can also be
performed.
Locked
Locked in current state. Protect and Unprotect Sector
commands will be ignored. Global Protect and Unprotect
cannot be performed.
Can be modified from 0 to 1
Unlocked and modifiable using the Protect and Unprotect
Sector commands. Global Protect and Unprotect can also be
performed.
Can be modified from 1 to 0
Locked in current state. Protect and Unprotect Sector
commands will be ignored. Global Protect and Unprotect
cannot be performed.
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
10.
Security Commands
10.1
Sector Lockdown
Certain applications require that portions of the Flash memory array be permanently protected against malicious
attempts at altering program code, data modules, security information, or encryption/decryption algorithms, keys,
and routines. To address these applications, the device incorporates a sector lockdown mechanism that allows any
combination of individual 64-Kbyte sectors to be permanently locked so that they become read only. Once a sector
is locked down, it can never be erased or programmed again, and it can never be unlocked from the locked down
state.
Each 64-Kbyte physical sector has a corresponding single-bit Sector Lockdown Register that is used to control the
lockdown status of that sector. These registers are nonvolatile and will retain their state even after a device powercycle or reset operation. The following table outlines the two states of the Sector Lockdown Registers.
Table 10-1.
Value
Sector Lockdown Register Values
Sector Lockdown Status
0
Sector is not locked down and can be programmed and erased. This is the default state.
1
Sector is permanently locked down and can never be programmed or erased again.
Issuing the Sector Lockdown command to a particular sector address will set the corresponding Sector Lockdown
Register to the logical “1” state. Each Sector Lockdown Register can only be set once; therefore, once set to the
logical “1” state, a Sector Lockdown Register cannot be reset back to the logical “0” state.
Before the Sector Lockdown command can be issued, the Write Enable command must have been previously
issued to set the WEL bit in the Status Register to a logical “1”. In addition, the Sector Lockdown Enabled (SLE) bit
in the Status Register must have also been previously set to the logical “1” state by using the Write Status Register
Byte 2 command (see “Write Status Register Byte 2” on page 36). To issue the Sector Lockdown command, the
CS pin must first be asserted and the opcode of 33h must be clocked into the device followed by three address
bytes designating any address within the 64-Kbyte sector to be locked down. After the three address bytes have
been clocked in, a confirmation byte of D0h must also be clocked in immediately following the three address bytes.
Any additional data clocked into the device after the first byte of data will be ignored. When the CS pin is deasserted, the Sector Lockdown Register corresponding to the sector addressed by A23-A0 will be set to the logical
“1” state, and the sector itself will then be permanently locked down from program and erase operations within a
time of tLOCK. In addition, the WEL bit in the Status Register will be reset back to the logical “0” state.
The complete three address bytes and the correct confirmation byte value of D0h must be clocked into the device
before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight
bits); otherwise, the device will abort the operation. When the device aborts the Sector Lockdown operation, the
state of the corresponding Sector Lockdown Register as well as the SLE bit in the Status Register will be
unchanged; however, the WEL bit in the Status Register will be reset to a logical “0”.
As a safeguard against accidental or erroneous locking down of sectors, the Sector Lockdown command can be
enabled and disabled as needed by using the SLE bit in the Status Register. In addition, the current sector lockdown state can be frozen so that no further modifications to the Sector Lockdown Registers can be made (see
“Freeze Sector Lockdown State” below). If the Sector Lockdown command is disabled or if the sector lockdown
state is frozen, then any attempts to issue the Sector Lockdown command will be ignored, and the device will reset
the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been
deasserted.
25
8715B–SFLSH–8/10
Figure 10-1. Sector Lockdown
CS
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE
SI
0
0
1
1
0
ADDRESS BITS A23-A0
0
1
1
MSB
SO
10.2
A
A
A
A
A
A
MSB
CONFIRMATION BYTE IN
1
1
0
1
0
0
0
0
MSB
HIGH-IMPEDANCE
Freeze Sector Lockdown State
The current sector lockdown state can be permanently frozen so that no further modifications to the Sector Lockdown Registers can be made; therefore, the Sector Lockdown command will be permanently disabled, and no
additional sectors can be locked down aside from those already locked down. Any attempts to issue the Sector
Lockdown command after the sector lockdown state has been frozen will be ignored.
Before the Freeze Sector Lockdown State command can be issued, the Write Enable command must have been
previously issued to set the WEL bit in the Status Register to a logical “1”. In addition, the Sector Lockdown
Enabled (SLE) bit in the Status Register must have also been previously set to the logical “1” state. To issue the
Freeze Sector Lockdown State command, the CS pin must first be asserted and the opcode of 34h must be
clocked into the device followed by three command specific address bytes of 55AA40h. After the three address
bytes have been clocked in, a confirmation byte of D0h must be clocked in immediately following the three address
bytes. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the current sector lockdown state will be permanently frozen within a time of tLOCK. In addition, the WEL bit in the Status Register
will be reset back to the logical “0” state, and the SLE bit will be permanently reset to a logical “0” to indicate that
the Sector Lockdown command is permanently disabled.
The complete and correct three address bytes and the confirmation byte must be clocked into the device before the
CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation. When the device aborts the Freeze Sector Lockdown State operation, the
WEL bit in the Status Register will be reset to a logical “0”; however, the state of the SLE bit will be unchanged.
Figure 10-2. Freeze Sector Lockdown State
CS
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE
SI
0
0
1
1
0
ADDRESS BITS A23-A0
1
MSB
SO
26
0
0
0
MSB
1
0
0
0
0
CONFIRMATION BYTE IN
1
1
0
1
0
0
0
0
MSB
HIGH-IMPEDANCE
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
10.3
Read Sector Lockdown Registers
The Sector Lockdown Registers can be read to determine the current lockdown status of each physical 64-Kbyte
sector. To read the Sector Lockdown Register for a particular 64-Kbyte sector, the CS pin must first be asserted
and the opcode of 35h must be clocked in. Once the opcode has been clocked in, three address bytes designating
any address within the 64-Kbyte sector must be clocked in. After the address bytes have been clocked in, data will
be output on the SO pin during every subsequent clock cycle. The data being output will be a repeating byte of
either FFh or 00h to denote the value of the appropriate Sector Lockdown Register.
At clock frequencies above fCLK, the first byte of data output will not be valid. Therefore, if operating at clock frequencies above fCLK, at least two bytes of data must be clocked out from the device in order to determine the
correct status of the appropriate Sector Lockdown Register.
Table 10-2.
Read Sector Lockdown Register – Output Data
Output Data
Sector Lockdown Register Value
00h
Sector Lockdown Register value is 0 (sector is not locked down)
FFh
Sector Lockdown Register value is 1 (sector is permanently locked down)
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 10-3. Read Sector Lockdown Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
OPCODE
SI
0
0
1
1
0
ADDRESS BITS A23-A0
1
MSB
0
1
A
MSB
A
A
A
A
A
A
DON'T CARE
A
A
X
X
X
X
X
X
X
X
MSB
DATA BYTE
SO
HIGH-IMPEDANCE
D
MSB
D
D
D
D
D
D
D
D
D
MSB
27
8715B–SFLSH–8/10
10.4
Program OTP Security Register
The device contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key
storage, etc. The OTP Security Register is independent of the main Flash memory array and is comprised of a total
of 128-bytes of memory divided into two portions. The first 64-bytes (byte locations 0 through 63) of the OTP Security Register are allocated as a one-time user-programmable space. Once these 64-bytes have been programmed,
they cannot be erased or reprogrammed. The remaining 64-bytes of the OTP Security Register (byte locations 64
through 127) are factory programmed by Atmel® and will contain a unique value for each device. The factory programmed data is fixed and cannot be changed.
Table 10-3.
OTP Security Register
Security Register
Byte Number
0
1
...
62
One-Time User Programmable
63
64
65
...
126
127
Factory Programmed by Atmel
The user-programmable portion of the OTP Security Register does not need to be erased before it is programmed.
In addition, the Program OTP Security Register command operates on the entire 64-byte user-programmable portion of the OTP Security Register at one time. Once the user-programmable space has been programmed with any
number of bytes, the user-programmable space cannot be programmed again; therefore, it is not possible to only
program the first two bytes of the register and then program the remaining 62-bytes at a later time.
Before the Program OTP Security Register command can be issued, the Write Enable command must have been
previously issued to set the WEL bit in the Status Register to a logical “1”. To program the OTP Security Register,
the CS pin must first be asserted and an opcode of 9Bh must be clocked into the device followed by the three
address bytes denoting the first byte location of the OTP Security Register to begin programming at. Since the size
of the user-programmable portion of the OTP Security Register is 64-bytes, the upper order address bits do not
need to be decoded by the device. Therefore, address bits A23-A6 will be ignored by the device and their values
can be either a logical “1” or “0”. After the address bytes have been clocked in, data can then be clocked into the
device and will be stored in the internal buffer.
If the starting memory address denoted by A23-A0 does not start at the beginning of the OTP Security Register
memory space (A5-A0 are not all 0), then special circumstances regarding which OTP Security Register locations
to be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the
64-byte user-programmable space will wrap around back to the beginning of the OTP Security Register. For example, if the starting address denoted by A23-A0 is 00003Eh, and three bytes of data are sent to the device, then the
first two bytes of data will be programmed at OTP Security Register addresses 00003Eh and 00003Fh while the
last byte of data will be programmed at address 000000h. The remaining bytes in the OTP Security Register
(addresses 000001h through 00003Dh) will not be programmed and will remain in the erased state (FFh). In addition, if more than 64-bytes of data are sent to the device, then only the last 64-bytes sent will be latched into the
internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate OTP Security Register locations based on the starting address specified by A23-A0 and the number of
data bytes sent to the device. If less than 64-bytes of data were sent to the device, then the remaining bytes within
the OTP Security Register will not be programmed and will remain in the erased state (FFh). The programming of
the data bytes is internally self-timed and should take place in a time of tOTPP. It is not possible to suspend the programming of the OTP Security Register.
28
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin
is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device will abort the operation and the user-programmable portion of the OTP Security Register will not be programmed. The WEL bit in the Status Register will be reset back to the logical “0” state if the OTP Security Register
program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin
being deasserted on uneven byte boundaries, or because the user-programmable portion of the OTP Security
Register was previously programmed.
While the device is programming the OTP Security Register, the Status Register can be read and will indicate that
the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting
the tOTPP time to determine if the data bytes have finished programming. At some point before the OTP Security
Register programming completes, the WEL bit in the Status Register will be reset back to the logical “0” state.
If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte
user programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed again.
The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the contents of the buffer will be altered from its previous state when this command is issued.
Figure 10-4. Program OTP Security Register
CS
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
OPCODE
SI
1
0
0
1
1
ADDRESS BITS A23-A0
0
MSB
SO
1
1
A
MSB
A
A
A
A
A
DATA IN BYTE 1
D
MSB
D
D
D
D
D
D
DATA IN BYTE n
D
D
D
D
D
D
D
D
D
MSB
HIGH-IMPEDANCE
29
8715B–SFLSH–8/10
10.5
Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum clock frequency specified by fMAX. To read the OTP Security Register, the CS pin must first be asserted and
the opcode of 77h must be clocked into the device. After the opcode has been clocked in, the three address bytes
must be clocked in to specify the starting address location of the first byte to read within the OTP Security Register.
Following the three address bytes, two dummy bytes must be clocked into the device before data can be output.
After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP
Security Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security Register has
been read, the device will continue reading back at the beginning of the register (000000h). No delays will be
incurred when wrapping around from the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 10-5. Read OTP Security Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36
SCK
OPCODE
SI
0
1
1
1
0
ADDRESS BITS A23-A0
1
MSB
1
1
A
MSB
A
A
A
A
A
A
DON'T CARE
A
A
X
X
X
X
X
X
X
X
X
MSB
DATA BYTE 1
SO
HIGH-IMPEDANCE
D
MSB
30
D
D
D
D
D
D
D
D
D
MSB
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
11.
Status Register Commands
11.1
Read Status Register
The two-byte Status Register can be read to determine the device’s ready/busy status, as well as the status of
many other functions such as Hardware Locking and Software Protection. The Status Register can be read at any
time, including during an internally self-timed program or erase operation.
To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the
device. After the opcode has been clocked in, the device will begin outputting Status Register data on the SO pin
during every subsequent clock cycle. After the second byte of the Status Register has been clocked out, the
sequence will repeat itself starting again with the first byte of the Status Register as long as the CS pin remains
asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated, so each
repeating sequence will output new data. The RDY/BSY status is available for both bytes of the Status Register
and is updated for each byte.
At clock frequencies above fCLK, the first two bytes of data output from the Status Register will not be valid. Therefore, if operating at clock frequencies above fCLK, at least four bytes of data must be clocked out from the device in
order to read the correct values of both bytes of the Status Register.
Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Table 11-1.
Status Register Format – Byte 1
Bit(1)
7
Name
SPRL
Sector Protection Registers Locked
Type(2)
RES
Reserved for future use
R
5
EPE
Erase/Program Error
R
3:2
1
0
Notes:
WPP
SWP
WEL
RDY/BSY
Write Protect (WP) Pin Status
Software Protection Status
Write Enable Latch Status
Ready/Busy Status
0
Sector Protection Registers are unlocked (default)
1
Sector Protection Registers are locked
0
Reserved for future use
0
Erase or program operation was successful
1
Erase or program error detected
0
WP is asserted
1
WP is deasserted
00
All sectors are software unprotected (all Sector
Protection Registers are 0)
01
Some sectors are software protected. Read
individual Sector Protection Registers to determine
which sectors are protected
10
Reserved for future use
11
All sectors are software protected (all Sector
Protection Registers are 1 – default)
0
Device is not write enabled (default)
1
Device is write enabled
0
Device is ready
1
Device is busy with an internal operation
R/W
6
4
Description
R
R
R
R
1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register Byte 1 command.
2. R/W = Readable and writeable
R = Readable only
31
8715B–SFLSH–8/10
Table 11-2.
Bit
Status Register Format – Byte 2
(1)
Name
Type(2)
Description
7
RES
Reserved for future use
R
0
Reserved for future use
6
RES
Reserved for future use
R
0
Reserved for future use
5
RES
Reserved for future use
R
0
Reserved for future use
0
Reset command is disabled (default)
4
RSTE
1
Reset command is enabled
0
Sector Lockdown and Freeze Sector Lockdown State
commands are disabled (default)
1
Sector Lockdown and Freeze Sector Lockdown State
commands are enabled
3
SLE
Reset Enabled
Sector Lockdown Enabled
R/W
R/W
2
RES
Reserved for future use
R
0
Reserved for future use
1
RES
Reserved for future use
R
0
Reserved for future use
0
Device is ready
0
RDY/BSY
Ready/Busy Status
R
1
Device is busy with an internal operation
Notes:
1. Only bits 4 and 3 of Status Register Byte 2 will be modified when using the Write Status Register Byte 2 command.
2. R/W = Readable and writeable
R = Readable only
11.1.1 SPRL Bit
The SPRL bit is used to control whether the Sector Protection Registers can be modified or not. When the SPRL
bit is in the logical “1” state, all Sector Protection Registers are locked and cannot be modified with the Protect Sector and Unprotect Sector commands (the device will ignore these commands). In addition, the Global Protect and
Global Unprotect features cannot be performed. Any sectors that are presently protected will remain protected, and
any sectors that are presently unprotected will remain unprotected.
When the SPRL bit is in the logical “0” state, all Sector Protection Registers are unlocked and can be modified (the
Protect Sector and Unprotect Sector commands, as well as the Global Protect and Global Unprotect features, will
be processed as normal). The SPRL bit defaults to the logical “0” state after device power-up. The Reset command
has no effect on the SPRL bit.
The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then
the SPRL bit may only be changed from a logical “0” (Sector Protection Registers are unlocked) to a logical “1”
(Sector Protection Registers are locked). In order to reset the SPRL bit back to a logical “0” using the Write Status
Register Byte 1 command, the WP pin will have to first be deasserted.
The SPRL bit is the only bit of Status Register Byte 1 that can be user modified via the Write Status Register Byte
1 command.
11.1.2 EPE Bit
The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one
byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the
logical “1” state. The EPE bit will not be set if an erase or program operation aborts for any reason such as an
attempt to erase or program a protected region or a locked down sector or if the WEL bit is not set prior to an erase
or program operation. The EPE bit will be updated after every erase and program operation.
32
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
11.1.3 WPP Bit
The WPP bit can be read to determine if the WP pin has been asserted or not.
11.1.4 SWP Bits
The SWP bits provide feedback on the software protection status for the device. There are three possible combinations of the SWP bits that indicate whether none, some, or all of the sectors have been protected using the Protect
Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have been protected, then the individual Sector Protection Registers can be read with the Read Sector Protection Registers
command to determine which sectors are in fact protected.
11.1.5 WEL Bit
The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0”
state, the device will not accept any Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, or Write Status Register commands. The
WEL bit defaults to the logical “0” state after a device power-up or reset operation. In addition, the WEL bit will be
reset to the logical “0” state automatically under the following conditions:
• Write Disable operation completes successfully
• Write Status Register operation completes successfully or aborts
• Protect Sector operation completes successfully or aborts
• Unprotect Sector operation completes successfully or aborts
• Sector Lockdown operation completes successfully or aborts
• Freeze Sector Lockdown State operation completes successfully or aborts
• Program OTP Security Register operation completes successfully or aborts
• Byte/Page Program operation completes successfully or aborts
• Block Erase operation completes successfully or aborts
• Chip Erase operation completes successfully or aborts
• Hold condition aborts
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an incomplete
or unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to
be reset when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Protect Sector,
Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, or Write Status Register command must have been clocked into the device.
11.1.6 RSTE Bit
The RSTE bit is used to enable or disable the Reset command. When the RSTE bit is in the logical “0” state (the
default state after power-up), the Reset command is disabled and any attempts to reset the device using the Reset
command will be ignored. When the RSTE bit is in the logical “1” state, the Reset command is enabled.
The RSTE bit will retain its state as long as power is applied to the device. Once set to the logical “1” state, the
RSTE bit will remain in that state until it is modified using the Write Status Register Byte 2 command or until the
device has been power cycled. The Reset command itself will not change the state of the RSTE bit.
33
8715B–SFLSH–8/10
11.1.7 SLE Bit
The SLE bit is used to enable and disable the Sector Lockdown and Freeze Sector Lockdown State commands.
When the SLE bit is in the logical “0” state (the default state after power-up), the Sector Lockdown and Freeze Sector Lockdown commands are disabled. If the Sector Lockdown and Freeze Sector Lockdown commands are
disabled, then any attempts to issue the commands will be ignored. This provides a safeguard for these commands
against accidental or erroneous execution. When the SLE bit is in the logical “1” state, the Sector Lockdown and
Freeze Sector Lockdown State commands are enabled.
Unlike the WEL bit, the SLE bit does not automatically reset after certain device operations. Therefore, once set,
the SLE bit will remain in the logical “1” state until it is modified using the Write Status Register Byte 2 command or
until the device has been power cycled. The Reset command has no effect on the SLE bit.
If the Freeze Sector Lockdown State command has been issued, then the SLE bit will be permanently reset in the
logical “0” state to indicate that the Sector Lockdown command has been disabled.
11.1.8 RDY/BSY Bit
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must
be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a logical “0”.
Figure 11-1. Read Status Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SCK
OPCODE
SI
0
0
0
0
0
1
0
1
MSB
SO
HIGH-IMPEDANCE
STATUS REGISTER
BYTE 1
D
MSB
34
D
D
D
D
D
D
STATUS REGISTER
BYTE 2
D
D
D
D
MSB
D
D
D
D
STATUS REGISTER
BYTE 1
D
D
D
D
D
D
D
D
D
MSB
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
11.2
Write Status Register Byte 1
The Write Status Register Byte 1 command is used to modify the SPRL bit of the Status Register and/or to perform
a Global Protect or Global Unprotect operation. Before the Write Status Register Byte 1 command can be issued,
the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical
“1”.
To issue the Write Status Register Byte 1 command, the CS pin must first be asserted and the opcode of 01h must
be clocked into the device followed by one byte of data. The one byte of data consists of the SPRL bit value, a
don’t care bit, four data bits to denote whether a Global Protect or Unprotect should be performed, and two additional don’t care bits (see Table 11-3). Any additional data bytes that are sent to the device will be ignored. When
the CS pin is deasserted, the SPRL bit in the Status Register will be modified, and the WEL bit in the Status Register will be reset back to a logical “0”. The values of bits five, four, three, and two and the state of the SPRL bit
before the Write Status Register Byte 1 command was executed (the prior state of the SPRL bit) will determine
whether or not a Global Protect or Global Unprotect will be performed. Please refer to “Global Protect/Unprotect”
on page 21 for more details.
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin
must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation,
the state of the SPRL bit will not change, no potential Global Protect or Unprotect will be performed, and the WEL
bit in the Status Register will be reset back to the logical “0” state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made to reset the SPRL
bit to a logical “0” while the WP pin is asserted, then the Write Status Register Byte 1 command will be ignored, and
the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted.
Table 11-3.
Write Status Register Byte 1 Format
Bit 7
Bit 6
SPRL
X
Bit 5
Bit 4
Bit 3
Global Protect/Unprotect
Bit 2
Bit 1
Bit 0
X
X
Figure 11-2. Write Status Register Byte 1
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
STATUS REGISTER IN
BYTE 1
OPCODE
SI
0
0
0
0
0
0
MSB
SO
0
1
D
X
D
D
D
D
X
X
MSB
HIGH-IMPEDANCE
35
8715B–SFLSH–8/10
11.3
Write Status Register Byte 2
The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Status Register. Using
the Write Status Register Byte 2 command is the only way to modify the RSTE and SLE bits in the Status Register
during normal device operation, and the SLE bit can only be modified if the sector lockdown state has not been frozen. Before the Write Status Register Byte 2 command can be issued, the Write Enable command must have been
previously issued to set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and the opcode of 31h must
be clocked into the device followed by one byte of data. The one byte of data consists of three don’t care bits, the
RSTE bit value, the SLE bit value, and three additional don’t care bits (see Table 11-4). Any additional data bytes
that are sent to the device will be ignored. When the CS pin is deasserted, the RSTE and SLE bits in the Status
Register will be modified, and the WEL bit in the Status Register will be reset back to a logical “0”. The SLE bit will
only be modified if the Freeze Sector Lockdown State command has not been previously issued.
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin
must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation,
the state of the RSTE and SLE bits will not change, and the WEL bit in the Status Register will be reset back to the
logical “0” state.
Table 11-4.
Write Status Register Byte 2 Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
RSTE
SLE
X
X
X
Figure 11-3. Write Status Register Byte 2
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
STATUS REGISTER IN
BYTE 2
OPCODE
SI
0
0
1
1
0
0
MSB
SO
36
0
1
X
X
X
D
D
X
X
X
MSB
HIGH-IMPEDANCE
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
12.
Other Commands and Functions
12.1
Reset
In some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than wait
the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally.
The Reset command allows a program or erase operation in progress to be ended abruptly and returns the device
to an idle state. Since the need to reset the device is immediate, the Write Enable command does not need to be
issued prior to the Reset command being issued. Therefore, the Reset command operates independently of the
state of the WEL bit in the Status Register.
The Reset command can only be executed if the command has been enabled by setting the Reset Enabled
(RSTE) bit in the Status Register to a logical “1”. If the Reset command has not been enabled (the RSTE bit is in
the logical “0” state), then any attempts at executing the Reset command will be ignored.
To perform a Reset, the CS pin must first be asserted and the opcode of F0h must be clocked into the device. No
address bytes need to be clocked in, but a confirmation byte of D0h must be clocked into the device immediately
after the opcode. Any additional data clocked into the device after the confirmation byte will be ignored. When the
CS pin is deasserted, the program or erase operation currently in progress will be terminated within a time of tRST.
Since the program or erase operation may not complete before the device is reset, the contents of the page being
programmed or the block being erased cannot be guaranteed to be valid.
The Reset command has no effect on the states of the Sector Protection Registers, the Sector Lockdown Registers, or the SPRL, RSTE, and SLE bits in the Status Register. The WEL, PS, and ES bits, however, will be reset
back to their default states.
The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and
the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation
will be performed.
Figure 12-1. Reset
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
OPCODE
SI
1
1
1
1
0
CONFIRMATION BYTE IN
0
MSB
SO
0
0
1
1
0
1
0
0
0
0
MSB
HIGH-IMPEDANCE
37
8715B–SFLSH–8/10
12.2
Read Manufacturer and Device ID
Identification information can be read from the device to enable systems to electronically query and identify the
device while it is in system. The identification method and the command opcode comply with the JEDEC standard
for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The
type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the vendor specific Extended Device Information.
The Read Manufacturer and Device ID command is limited to a maximum clock frequency of fCLK. Since not all
Flash devices are capable of operating at very high clock frequencies, applications should be designed to read the
identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used
in the application can be identified properly. Once the identification process is complete, the application can then
increase the clock frequency to accommodate specific Flash devices that are capable of operating at the higher
clock frequencies.
To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into
the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO
pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two
bytes of Device ID information. The fourth byte output will be the Extended Device Information String Length, which
will be 00h indicating that no Extended Device Information follows. After the Extended Device Information String
Length byte is output, the SO pin will go into a high-impedance state; therefore, additional clock cycles will have no
affect on the SO pin and no data will be output. As indicated in the JEDEC standard, reading the Extended Device
Information String Length and any subsequent data is optional.
Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a
high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be
read.
Table 12-1.
Manufacturer and Device ID Information
Byte No.
Data Type
Value
1
Manufacturer ID
1Fh
2
Device ID (Part 1)
45h
3
Device ID (Part 2)
01h
4
[Optional to read] Extended Device Information (EDI) String Length
01h
5
[Optional to read] EDI Byte 1
00h
Table 12-2.
Manufacturer and Device ID Details
Data Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
Hex
Value
Details
JEDEC Assigned Code
Manufacturer ID
0
0
0
1
1
Family Code
1
1
0
0
Sub Code
0
1
0
38
0
0001 1111 (1Fh for Atmel)
45h
Family Code:
Density Code:
010 (AT25DF/26DFxxx series)
00101 (8-Mbit)
01h
Sub Code:
000 (Standard series)
Product Version: 00001 (Second major version)
1
Product Version Code
Device ID (Part 2)
0
JEDEC Code:
Density Code
Device ID (Part 1)
0
1Fh
0
0
0
0
0
1
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
Figure 12-2. Read Manufacturer and Device ID
&6
6&.
OPCODE
6,
62
)K
+,*+,03('$1&(
Note: Each transition
12.3
)K
K
K
K
K
MANUFACTURED ID
DEVICE ID
BYTE 1
DEVICE ID
BYTE 2
EDI
STRING LENGTH
EDI
DATA BYTE 1
shown for SI and SO represents one byte (8 bits)
Deep Power-Down
During normal operation, the device will be placed in the standby mode to consume less power as long as the CS
pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability
to place the device into an even lower power consumption state called the Deep Power-Down mode.
When the device is in the Deep Power-Down mode, all commands including the Read Status Register command
will be ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be
ignored, the mode can be used as an extra protection mechanism against program and erase operations.
Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode of
B9h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored.
When the CS pin is deasserted, the device will enter the Deep Power-Down mode within the maximum time of
tEDPD.
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on
an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the
standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode after a powercycle.
The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase
cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation
has been completed in order for the device to enter the Deep Power-Down mode.
39
8715B–SFLSH–8/10
Figure 12-3. Deep Power-Down
CS
tEDPD
0
1
2
3
4
5
6
7
SCK
OPCODE
SI
1
0
1
1
1
0
0
1
MSB
SO
HIGH-IMPEDANCE
Active Current
ICC
Standby Mode Current
12.4
Deep Power-Down Mode Current
Resume from Deep Power-Down
In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep PowerDown command must be issued. The Resume from Deep Power-Down command is the only command that the
device will recognized while in the Deep Power-Down mode.
To resume from the Deep Power-Down mode, the CS pin must first be asserted and opcode of ABh must be
clocked into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS
pin is deasserted, the device will exit the Deep Power-Down mode within the maximum time of tRDPD and return to
the standby mode. After the device has returned to the standby mode, normal command operations such as Read
Array can be resumed.
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an
even byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep PowerDown mode.
Figure 12-4. Resume from Deep Power-Down
CS
tRDPD
0
1
2
3
4
5
6
7
SCK
OPCODE
SI
1
0
1
0
1
0
1
1
MSB
SO
HIGH-IMPEDANCE
Active Current
ICC
Deep Power-Down Mode Current
40
Standby Mode Current
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
12.5
Hold
The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock
sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the
operation, and the erase cycle will continue until it is finished.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting
the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold
mode won’t be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as
long as the HOLD pin and CS pin are asserted.
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin
will be ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low
pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won’t end until the beginning
of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will
be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.
Figure 12-5. Hold Mode
CS
SCK
HOLD
Hold
Hold
Hold
41
8715B–SFLSH–8/10
13.
Atmel RapidS Implementation
To implement Atmel RapidSTM and operate at clock frequencies higher than what can be achieved in a viable SPI
implementation, a full clock cycle can be used to transmit data back and forth across the serial bus. The Atmel
AT25DF081A is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the
rising edge of SCK.
For full clock cycle operation to be achieved, when the AT25DF081A is clocking data out on the falling edge of
SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the AT25DF081A a full clock cycle to latch
the incoming data in on the next rising edge of SCK.
Implementing RapidS allows a system to run at higher clock frequencies since a full clock cycle is used to accommodate a device’s clock-to-output time, input setup time, and associated rise/fall times. For example, if the system
clock frequency is 100 MHz (10ns cycle time) with a 50% duty cycle, and the host controller has an input setup
time of 2ns, then a standard SPI implementation would require that the slave device be capable of outputting its
data in less than 3ns to meet the 2ns host controller setup time [(10ns x 50%) – 2ns] not accounting for rise/fall
times. In an SPI mode 0 or 3 implementation, the SPI master is designed to clock in data on the next immediate rising edge of SCK after the SPI slave has clocked its data out on the preceding falling edge. This essentially makes
SPI a half-clock cycle protocol and requires extremely fast clock-to-output times and input setup times in order to
run at high clock frequencies. With a RapidS implementation of this example, however, the full 10ns cycle time is
available which gives the slave device up to 8ns, not accounting for rise/fall times, to clock its data out. Likewise,
with RapidS, the host controller has more time available to output its data to the slave since the slave device would
be clocking that data in a full clock cycle later.
Figure 13-1. Atmel RapidS Operation
Slave CS
1
8
2
3
4
5
6
1
1
8
7
2
3
4
5
6
7
SCK
B
A
MOSI
C
tV
E
D
MSB
LSB
BYTE A
H
G
I
F
MISO
MSB
LSB
BYTE B
MOSI = Master Out, Slave In
MISO = Master In, Slave Out
The Master is the ASIC/MCU and the Slave is the memory device
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK
A.
B.
C.
D.
E.
F.
G.
H.
I.
42
Master clocks out first bit of BYTE A on the rising edge of SCK
Slave clocks in first bit of BYTE A on the next rising edge of SCK
Master clocks out second bit of BYTE A on the same rising edge of SCK
Last bit of BYTE A is clocked out from the Master
Last bit of BYTE A is clocked into the slave
Slave clocks out first bit of BYTE B
Master clocks in first bit of BYTE B
Slave clocks out second bit of BYTE B
Master clocks in last bit of BYTE B
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
14.
Electrical Specifications
14.1
Absolute Maximum Ratings*
Temperature under Bias........................-55°C to +125°C
*NOTICE:
Storage Temperature ............................-65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground............................-0.6V to +4.1V
All Output Voltages
with Respect to Ground....................-0.6V to VCC + 0.5V
14.2
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions
beyond those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC and AC Operating Range
Atmel AT25DF081A
Operating Temperature (Case)
Ind.
-40°C to 85°C
VCC Power Supply
14.3
2.7V to 3.6V
DC Characteristics
Symbol
Parameter
Condition
ISB
Standby Current
IDPD
Deep Power-down Current
ICC1
Active Current, Read Operation
Min
Typ
Max
Units
CS, WP, HOLD = VCC,
all inputs at CMOS levels
25
50
µA
CS, WP, HOLD = VCC,
all inputs at CMOS levels
5
10
µA
f = 100MHz; IOUT = 0mA;
CS = VIL, VCC = Max
17
20
f = 85MHz; IOUT = 0mA;
CS = VIL, VCC = Max
16
19
f = 66MHz; IOUT = 0mA;
CS = VIL, VCC = Max
15
18
f = 50MHz; IOUT = 0mA;
CS = VIL, VCC = Max
14
17
f = 33MHz; IOUT = 0mA;
CS = VIL, VCC = Max
13
16
f = 20MHz; IOUT = 0mA;
CS = VIL, VCC = Max
12
15
CS = VCC, VCC = Max
10
15
mA
12
mA
ICC2
Active Current, Program Operation
ICC3
Active Current, Erase Operation
CS = VCC, VCC = Max
18
mA
ILI
Input Leakage Current
VIN = CMOS levels
1
µA
ILO
Output Leakage Current
VOUT = CMOS levels
1
µA
VIL
Input Low Voltage
0.3 x VCC
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 1.6mA; VCC = Min
VOH
Output High Voltage
IOH = -100µA; VCC = Min
0.7 x VCC
V
0.4
VCC - 0.2V
V
V
43
8715B–SFLSH–8/10
14.4
AC Characteristics – Maximum Clock Frequencies
Symbol
Parameter
Min
Max
Units
Atmel RapidS and SPI Operation
14.5
fMAX
Maximum Clock Frequency for All Operations – RapidS Operation Only
(excluding 0Bh, 03h, 3Bh, and 9F opcodes)
100
MHz
fCLK
Maximum Clock Frequency for All Operations
(excluding 03h and 3Bh opcodes)
85
MHz
fRDLF
Maximum Clock Frequency for 03h Opcode (Read Array – Low Frequency)
50
MHz
fRDDO
Maximum Clock Frequency for 3Bh Opcode (Dual-Output Read)
85
MHz
Max
Units
AC Characteristics – All Other Parameters
Symbol
Parameter
Min
tCLKH
Clock High Time
4.3
ns
Clock Low Time
4.3
ns
(1)
Clock Rise Time, Peak-to-Peak (Slew Rate)
0.1
V/ns
(1)
tCLKL
tCLKR
Clock Fall Time, Peak-to-Peak (Slew Rate)
0.1
V/ns
tCSH
Chip Select High Time
50
ns
tCSLS
Chip Select Low Setup Time (relative to Clock)
5
ns
tCSLH
Chip Select Low Hold Time (relative to Clock)
5
ns
tCSHS
Chip Select High Setup Time (relative to Clock)
5
ns
tCSHH
Chip Select High Hold Time (relative to Clock)
5
ns
tDS
Data In Setup Time
2
ns
Data In Hold Time
1
ns
tCLKF
tDH
(1)
Output Disable Time
5
ns
tV(2)
Output Valid Time
5
ns
tOH
Output Hold Time
2
ns
tHLS
HOLD Low Setup Time (relative to Clock)
5
ns
tHLH
HOLD Low Hold Time (relative to Clock)
5
ns
tHHS
HOLD High Setup Time (relative to Clock)
5
ns
HOLD High Hold Time (relative to Clock)
5
ns
tDIS
tHHH
tHLQZ
(1)
HOLD Low to Output High-Z
tHHQX(1)
tWPS(1)(3)
tWPH(1)(3)
tSECP(1)
tSECUP(1)
tLOCK(1)
tEDPD(1)
tRDPD(1)
HOLD High to Output Low-Z
tRST
Notes:
5
ns
5
ns
Write Protect Setup Time
20
ns
Write Protect Hold Time
100
ns
Sector Protect Time (from Chip Select High)
20
ns
Sector Unprotect Time (from Chip Select High)
20
ns
Sector Lockdown and Freeze Sector Lockdown State Time (from Chip Select High)
200
µs
Chip Select High to Deep Power-Down
1
µs
Chip Select High to Standby Mode
30
µs
Reset Time
30
µs
1. Not 100% tested (value guaranteed by design and characterization)
2. 15pF load at frequencies above 70MHz, 30pF otherwise
3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1
44
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
14.6
Program and Erase Characteristics
Symbol
Parameter
tPP(1)
Page Program Time (256-Bytes)
tBP
Byte Program Time
tBLKE(1)
Min
Typ
Max
Units
1.0
3.0
ms
7
Block Erase Time
µs
4-Kbytes
50
200
32-Kbytes
250
600
64-Kbytes
400
950
ms
tCHPE(1)(2)
Chip Erase Time
16
28
sec
tOTPP(1)
OTP Security Register Program Time
200
500
µs
200
ns
Max
Units
tWRSR
Notes:
(2)
Write Status Register Time
1. Maximum values indicate worst-case performance after 100,000 erase/program cycles
2. Not 100% tested (value guaranteed by design and characterization)
14.7
14.8
Power-up Conditions
Symbol
Parameter
Min
tVCSL
Minimum VCC to Chip Select Low Time
100
tPUW
Power-up Device Delay Before Program or Erase Allowed
VPOR
Power-on Reset Voltage
1.5
µs
10
ms
2.5
V
Input Test Waveforms and Measurement Levels
AC
DRIVING
LEVELS
0.9VCC
VCC/2
0.1VCC
AC
MEASUREMENT
LEVEL
tR, tF < 2 ns (10% to 90%)
14.9
Output Test Load
DEVICE
UNDER
TEST
15pF (frequencies above 70MHz)
or
30pF
45
8715B–SFLSH–8/10
15.
AC Waveforms
Figure 15-1. Serial Input Timing
tCSH
CS
tCSLH
tCLKL
tCSLS
tCLKH
tCSHH
tCSHS
SCK
tDS
SI
SO
tDH
MSB
LSB
MSB
HIGH-IMPEDANCE
Figure 15-2. Serial Output Timing
CS
tCLKH
tCLKL
tDIS
SCK
SI
tOH
tV
tV
SO
Figure 15-3. WP Timing for Write Status Register Byte 1 Command When SPRL = 1
CS
tWPH
tWPS
WP
SCK
SI
0
MSB OF
WRITE STATUS REGISTER
BYTE 1 OPCODE
SO
46
0
0
X
MSB
LSB OF
WRITE STATUS REGISTER
DATA BYTE
MSB OF
NEXT OPCODE
HIGH-IMPEDANCE
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
Figure 15-4. HOLD Timing – Serial Input
CS
SCK
tHHH
tHLS
tHLH
tHHS
tHLH
tHHS
HOLD
SI
SO
HIGH-IMPEDANCE
Figure 15-5. HOLD Timing – Serial Output
CS
SCK
tHHH
tHLS
HOLD
SI
tHLQZ
tHHQX
SO
47
8715B–SFLSH–8/10
16.
Ordering Information
16.1
Code Detail Detail
AT 2 5 D F 0 8 1 A - S S H - B
Atmel Designator
Shipping Carrier Option
B = Bulk (tubes)
Y = Bulk (trays)
T = Tape and reel
Product Family
Device Grade
H = Green, NiPdAu lead finish, industrial
temperature range (-40°C to +85°C)
Device Density
8 = 8-megabit
Interface
Package Option
1 = Serial
16.2
SS = 8-lead, 0.150" wide SOIC
S = 8-lead, 0.208" wide SOIC
M = 8-pad, 5 x 6 x 0.6mm UDFN
Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code
Package
AT25DF081A-MH-Y
AT25DF081A-MH-T
8MA1
AT25DF081A-SSH-B
AT25DF081A-SSH-T
8S1
AT25DF081A-SH-B
AT25DF081A-SH-T
8S2
Note:
Lead (Pad) Finish
Operating Voltage
Max. Freq. (MHz)
Operation Range
NiPdAu
2.7V to 3.6V
100
Industrial
(-40°C to +85°C)
The shipping carrier option code is not marked on the devices.
Package Type
8MA1
8-pad (5 x 6 x 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN)
8S1
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2
8-lead, 0.208” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
48
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
17.
Packaging Information
17.1
8MA1 – UDFN
E
C
Pin 1 ID
Side View
D
y
Top View
A1
A
K
E2
Option A
8
Pin #1
Chamfer
(C 0.35)
1
Pin #1 Notch
(0.20 R)
(Option B)
7
2
e
D2
6
3
5
4
SYMBOL
MIN
NOM
MAX
A
0.45
0.55
0.60
A1
0.00
0.02
0.05
b
0.35
0.40
0.48
Bottom View
D
4.90
5.00
5.10
D2
3.80
4.00
4.20
E
5.90
6.00
6.10
E2
3.20
3.40
3.60
1.27
e
Notes: 1. This package conforms to JEDEC reference MO-229,
Saw Singulation.
2. The terminal #1 ID is a Laser-marked Feature.
NOTE
0.152 REF
C
b
L
COMMON DIMENSIONS
(Unit of Measure = mm)
L
0.50
0.60
0.75
y
0.00
–
0.08
K
0.20
–
–
4/15/08
TITLE
8MA1, 8-pad (5 x 6 x 0.6mm Body), Thermally
Package Drawing Contact:
[email protected] Enhanced Plastic Ultra Thin Dual Flat No Lead
Package (UDFN)
GPC
YFG
DRAWING NO.
REV.
8MA1
D
49
8715B–SFLSH–8/10
17.2
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
5/19/10
TITLE
Package Drawing Contact:
8S1, 8-lead (0.150” Wide Body), Plastic Gull
[email protected] Wing Small Outline (JEDEC SOIC)
50
GPC
SWB
DRAWING NO.
8S1
REV.
F
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
Atmel AT25DF081A [Preliminary]
17.3
8S2 – EIAJ SOIC
C
1
E
E1
L
End View
N
q
Top View
e
b
A
A1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
D
Side View
Notes: 1. This drawing is for general information only; refer to
EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs
are not included.
3. Determines the true geometric position.
4. Values b, C apply to plated terminal. The standard
thickness of the plating layer shall measure between
0.007 to .021mm.
MIN
NOM
MAX
NOTE
A
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
4
C
0.15
0.35
4
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
q
0˚
8˚
e
2
3
1.27 BSC
4/15/08
TITLE
8S2, 8-lead, 0.208” Body, Plastic Small
Package Drawing Contact:
[email protected] Outline Package (EIAJ)
GPC
STN
DRAWING NO.
REV.
8S2
F
51
8715B–SFLSH–8/10
18.
52
Revision History
Doc. Rev.
Date
Comments
8715B
08/2010
Change tRDPD Max from 10 to 30 in AC Parameters
8715A
06/2010
Initial document release
Atmel AT25DF081A [Preliminary]
8715B–SFLSH–8/10
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8715B–SFLSH–8/10