Mitel MT89L80AN Cmos st-busâ ¢ family digital switch Datasheet

MT89L80
CMOS ST-BUS FAMILY
Digital Switch
Advance Information
Features
•
•
•
•
•
•
•
•
•
•
DS5196
MT89L80AP
MT89L80AN
Description
This VLSI CMOS device is designed for switching
PCM-encoded voice or data, under microprocessor
control, in a modern digital exchange, PBX or
Central Office. It provides simultaneous connections
for up to 256 64 kbit/s channels. Each of the eight
serial inputs and outputs consist of 32 64 kbit/s
channels multiplexed to form a 2048 kbit/s ST-BUS
stream.
In addition, the MT89L80 provides
microprocessor read and write access to individual
ST-BUS channels.
**
F0i RESET VDD VSS
Frame
Counter
STi0
ODE
Output
MUX
STi1
STi2
STi3
STi4
STi5
Serial
to
Parallel
Converter
Data
Memory
Control Register
Connection
Memory
STi6
STi7
44 Pin PLCC
48 Pin SSOP
-40°C to +85°C
Key telephone systems
PBX systems
Small and medium voice switching systems
C4i
September 1999
Ordering Information
3.3 volt supply
5V tolerant inputs and TTL compatible outputs.
256 x 256 channel non-blocking switch
Accepts serial streams at 2.048Mb/s
Per-channel three-state control
Patented per channel message mode
Non-multiplexed microprocessor interface
Mitel ST-BUS compatible
Low power consumption: typical 15mW
Pin compatible with the MT8980DP
Applications
•
•
•
ISSUE 2
DTA D7/
D0
STo1
Parallel
to
Serial
Converter
STo2
STo3
STo4
STo5
STo6
STo7
Control Interface
DS CS R/W A5/
A0
STo0
CSTo
** for 48-pin SSOP only
Figure 1 - Functional Block Diagram
2-3
MT89L80
6
5
4
3
2
1
44
43
42
41
40
NC
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
NC
Advance Information
7
8
9
10
11
12
13
14
15
16
17
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
39
38
37
36
35
34
33
32
31
30
29
NC
A3
A4
A5
DS
R/W
CS
D7
D6
D5
NC
18
19
20
21
22
23
24
25
26
27
28
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
44 PIN PLCC
VSS
DTA
STi0
STi1
STi2
NC
STi3
STi4
STi5
STi6
STi7
VDD
RESET
F0i
C4i
A0
A1
A2
NC
A3
A4
A5
DS
R/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CSTo
ODE
STo0
STo1
STo2
NC
STo3
STo4
STo5
STo6
STo7
VSS
VDD
D0
D1
D2
D3
D4
NC
D5
D6
D7
CS
VSS
48 PIN SSOP
(JEDEC MO-118, 300mil Wide)
Figure 2 - Pin Connections
Pin Description
Pin #
44
48
PLCC SSOP
Name
2
2
3-5
3-5
STi0-2 ST-BUS Inputs 0 to 2 (5V-tolerant Inputs). Serial data input streams. These streams
have data rates of 2.048Mbit/s with 32 channels.
7-11
7-11
STi3-7 ST-BUS Inputs 3 to 7 (5V-tolerant Inputs). Serial data input streams. These streams
may have data rates of 2.048Mbit/s with 32channels.
12
12,36
13
DTA
Description
VDD
Data Acknowledgment (5V Tolerant Three-state Output). This active low output
indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
+3.3 Volt Power Supply.
RESET Device Reset ( 5v-tolerant input). This pin is only available for the 48-pin SSOP
package.This active low input puts the device in its reset state. It clears the internal
counters and registers. All ST-BUS outputs are set to the high impedance state. In
normal operation. The RESET pin must be held low for a minimum of 100nsec to reset
the device.
13
14
F0i
Frame Pulse (5V-tolerant Input). This is the input for the frame synchronization
pulse for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal
counter to reset on the next negative transition of C4i.
14
15
C4i
4.096 MHz Clock (5V-tolerant Input). ST-BUS bit cell boundaries lie on the alternate
falling edges of this clock.
15-17
16-18
A0-2
Address 0-2 / Input Streams 8-10 (5V-tolerant Input). These are the inputs for the
address lines on the microprocessor interface.
2-4
MT89L80
Advance Information
Pin Description (continued)
Pin #
44
48
PLCC SSOP
Name
Description
19-21
20-22
A3-5
22
23
DS
Data Strobe (5V-tolerant Input). This is the input for the active high data strobe on the
microprocessor interface.
23
24
R/W
Read/Write (5V-tolerant Input). This is the input for the read/write signal on the
microprocessor interface - high for read, low for write.
24
26
CS
Chip Select (5V-tolerant Input). This is the input for the active low chip select on the
microprocessor interface
25-27
27-29
D7-D5
Data Bus (5V-tolerant I/O): These are the bidirectional data pins on the microprocessor
interface.
29-33
31-35
D4-D0
Data Bus (5V-tolerant I/O): These are the bidirectional data pins on the microprocessor
interface.
34
1,
25,37
VSS
35-39
38-42
STo7-3 ST-BUS Outputs 7 to 3 (5V-Tolerant Three-state Outputs). These are the pins for the
eight 2048 kbit/s ST-BUS output streams.
41-43
44-46
STo2-0 ST-BUS Outputs 2to 0 (5V-Tolerant Three-state Outputs). These are the pins for the
eight 2048kbit/s ST-BUS output streams.
44
47
ODE
Output Drive Enable (5V-tolerant Input). If this input is held high, the STo0-STo7 output
drivers function normally. If this input is low, the STo0-STo7 output drivers go into their
high impedance state. NB: Even when ODE is high, channels on the STo0-STo7
outputs can go high impedance under software control.
1
48
CSTo
Control ST-BUS Output (5V-Tolerant Output). Each frame of 256 bits on this ST-BUS
output contains the values of bit 1 in the 256 locations of the Connection Memory High.
6, 18, 6, 19,
28, 40 30, 43
NC
Address 3-5 / Input Streams 11-13 (5V-tolerant Input). These are the inputs for the
address lines on the microprocessor interface.
Ground.
No Connection.
2-5
MT89L80
Advance Information
Functional Description
Hardware Description
In recent years, there has been a trend in telephony
towards digital switching, particularly in association
with software control. Simultaneously, there has
been a trend in system architectures towards
distributed processing or multi-processor systems.
Serial data at 2048 kbit/s is received at the eight STBUS inputs (STi0 to STi7), and serial data is
transmitted at the eight ST-BUS outputs (STo0 to
STo7). Each serial input accepts 32 channels of
digital data, each channel containing an 8-bit word
which may represent a PCM-encoded analog/voice
sample as provided by a codec (e.g., MITEL’s
MT8964).
In accordance with these trends, MITEL has devised
the ST-BUS (Serial Telecom Bus).
This bus
architecture can be used both in software-controlled
digital voice and data switching, and for
interprocessor communications.
The uses in
switching and in interprocessor communications are
completely integrated to allow for a simple general
purpose architecture appropriate for the systems of
the future.
The serial streams of the ST-BUS operate
continuously at 2048 kbit/s and are arranged in 125
µs wide frames which contain 32 8-bit channels.
MITEL manufactures a number of devices which
interface to the ST-BUS; a key device being the
MT89L80 chip.
The MT89L80 can switch data from channels on STBUS inputs to channels on ST-BUS outputs, and
simultaneously allows its controlling microprocessor
to read channels on ST-BUS inputs or write to
channels on ST-BUS outputs (Message Mode). To
the microprocessor, the MT89L80 looks like a
memory peripheral. The microprocessor can write to
the MT89L80 to establish switched connections
between input ST-BUS channels and output ST-BUS
channels, or to transmit messages on output ST-BUS
channels.
By reading from the MT89L80, the
microprocessor can receive messages from ST-BUS
input channels or check which switched connections
have already been established.
By integrating both switching and interprocessor
communications, the MT89L80 allows systems to
use distributed processing and to switch voice or
data in an ST-BUS architecture.
This serial input word is converted into parallel data
and stored in the 256 X 8 Data Memory. Locations in
the Data Memory are associated with particular
channels on particular ST-BUS input streams. These
locations can be read by the microprocessor which
controls the chip.
Locations in the Connection Memory, which is split
into high and low parts, are associated with
particular ST-BUS output streams. When a channel
is due to be transmitted on an ST-BUS output, the
data for the channel can either be switched from an
ST-BUS input or it can originate from the
microprocessor. If the data is switched from an
input, then the contents of the Connection Memory
Low location associated with the output channel is
used to address the Data Memory. This Data
Memory address corresponds to the channel on the
input ST-BUS stream on which the data for switching
arrived. If the data for the output channel originates
from the microprocessor (Message Mode), then the
contents of the Connection Memory Low location
associated with the output channel are output
directly, and this data is output repetitively on the
channel once every frame until the microprocessor
intervenes.
The Connection Memory data is received, via the
Control Interface, at D7 to D0. The Control Interface
also receives address information at A5 to A0 and
handles the microprocessor control signals CS,
DTA, R/W and DS. There are two parts to any
address in the Data Memory or Connection Memory.
A5
A4
A3
A2
A1
A0
Hex Address
Location
0
1
1
•
•
•
1
0
0
0
•
•
•
1
0
0
0
•
•
•
1
0
0
0
•
•
•
1
0
0
0
•
•
•
1
0
0
1
•
•
•
1
00 - 1F
20
21
•
•
•
3F
Control Register *
Channel 0†
Channel 1†
•
•
•
Channel 31†
* Writing to the Control Register is the only fast transaction.
† Memory and stream are specified by the contents of the Control Register.
Figure 3- Address Memory Map
2-6
MT89L80
Advance Information
The higher order bits come from the Control
Register, which may be written to or read from via
the Control Interface. The lower order bits come
from the address lines directly.
The Control Register also allows the chip to
broadcast messages on all ST-BUS outputs (i.e., to
put every channel into Message Mode), or to split the
memory so that reads are from the Data Memory
and writes are to the Connection Memory Low. The
Connection Memory High determines whether
individual output channels are in Message Mode,
and allows individual output channels to go into a
high-impedance state, which enables arrays of
MT89L80s to be constructed. It also controls the
CSTo pin.
All ST-BUS timing is
signals C4i and F0i.
If address line A5 is low, then the Control Register is
addressed regardless of the other address lines (see
Fig. 3). If A5 is high, then the address lines A4-A0
select the memory location corresponding to channel
0-31 for the memory and stream selected in the
Control Register.
The data in the Control Register consists of mode
control bits, memory select bits, and stream address
bits (see Fig. 4). The memory select bits allow the
Connection Memory High or Low or the Data
Memory to be chosen, and the stream address bits
define one of the ST-BUS input or output streams.
Bit 7 of the Control Register allows split memory
operation - reads are from the Data Memory and
writes are to the Connection Memory Low.
derived from the two
Software Control
The address lines on the Control Interface give
access to the Control Register directly or, depending
on the contents of the Control Register, to the High
or Low sections of the Connection Memory or to the
Data Memory.
The other mode control bit, bit 6, puts every output
channel on every output stream into active Message
Mode; i.e., the contents of the Connection Memory
Low are output on the ST-BUS output streams once
every frame unless the ODE pin is low. In this mode
the chip behaves as if bits 2 and 0 of every
Connection Memory High location were 1,
regardless of the actual values.
(unused)
7
Bit
7
Name
5
4
3
2
1
0
Description
Split Memory When 1, all subsequent reads are from the Data Memory and writes are to the Connection
Memory Low, except when the Control Register is accessed again. When 0, the Memory
Select bits specify the memory for subsequent operations. In either case, the Stream
Address Bits select the subsection of the memory which is made available.
6
Message
Mode
5
(unused)
4-3
Memory
Select Bits
2-0
6
Stream
Address
Bits
Memory
Select
Bits
Mode
Control
Bits
When 1, the contents of the Connection Memory Low are output on the Serial Output
streams except when the ODE pin is low. When 0, the Connection Memory bits for each
channel determine what is output.
0-0 - Not to be used
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High
Stream
The number expressed in binary notation on these bits refers to the input or output ST-BUS
Address Bits stream which corresponds to the subsection of memory made accessible for subsequent
operations.
Figure 4 - Control Register Bits
2-7
MT89L80
Advance Information
No Corresponding Memory
- These bits give 0s if read.
7
6
5
4
Per Channel
Control Bits
3
2
1
0
Bit
NameE
Description
2
Message
Channel
When 1, the contents of the corresponding location in Connection Memory Low are
output on the location’s channel and stream. When 0, the contents of the corresponding
location in Connection Memory Low act as an address for the Data Memory and so
determine the source of the connection to the location’s channel and stream.
1
CSTo Bit
This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output
first.
0
Output
Enable
If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the
output driver for the location’s channel and stream. This allows individual channels on
individual streams to be made high-impedance, allowing switching matrices to be
constructed. A 1 enables the driver and a 0 disables it.
Figure 5 - Connection Memory High Bits
Stream
Address
Bits
7
6
Channel
Address
Bits
5
4
3
2
1
0
Bit
Name
Description
7-5*
Stream
Address
Bits*
The number expressed in binary notation on these 3 bits is the number of the ST-BUS
stream for the source of the connection. Bit 7 is the most significant bit. e.g., if bit 7 is 1,
bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on STi4.
4-0*
Channel
Address
Bits*
The number expressed in binary notation on these 5 bits is the number of the channel
which is the source of the connection (The ST-BUS stream where the channel lies is
defined by bits 7, 6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2
is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire
8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated
to define the source of the connection which is output on the channel and stream associated with this location.
Figure 6 - Connection Memory Low Bits
2-8
MT89L80
Advance Information
If bit 6 of the Control Register is 0, then bits 2 and 0
of each Connection Memory High location function
normally (see Fig. 5). If bit 2 is 1, the associated STBUS output channel is in Message Mode; i.e., the
byte in the corresponding Connection Memory Low
location is transmitted on the stream at that channel.
Otherwise, one of the bytes received on the serial
inputs is transmitted and the contents of the
Connection Memory Low define the ST-BUS input
stream and channel where the byte is to be found
(see Fig. 6).
If the ODE pin is low, then all serial outputs are highimpedance. If it is high and bit 6 in the Control
Register is 1, then all outputs are active. If the ODE
pin is high and bit 6 in the Control Register is 0, then
the bit 0 in the Connection Memory High location
enables the output drivers for the corresponding
individual ST-BUS output stream and channel. Bit
0=1 enables the driver and bit 0=0 disables it (see
Fig. 5).
Bit 1 of each Connection Memory High location (see
Fig. 5) is output on the CSTo pin once every frame.
To allow for delay in any external control circuitry the
bit is output one channel before the corresponding
channel on the ST-BUS streams, and the bit for
stream 0 is output first in the channel; e.g., bit 1’s for
channel 9 of streams 0-7 are output synchronously
with ST-BUS channel 8 bits 7-0.
Fig. 7 shows the interface between the MT89L80s
and the filter/codecs. Fig. 8 shows the position of
these components in an example architecture.
The MT8964 filter/codec in Fig. 7 receives and
transmits digitized voice signals on the ST-BUS input
DR, and ST-BUS output DX, respectively. These
signals are routed to the ST-BUS inputs and outputs
on the top MT89L80, which is used as a digital
speech switch.
The MT8964 is controlled by the ST-BUS input DC
originating from the bottom MT89L80, which
generates the appropriate signals from an output
channel in Message Mode.
This architecture
optimizes the messaging capability of the line circuit
by building signalling logic, e.g., for on-off hook
detection, which communicates on an ST-BUS
output. This signalling ST-BUS output is monitored
by a microprocessor (not shown) through an ST-BUS
input on the bottom MT89L80.
Fig. 8 shows how a simple digital switching system
may be designed using the ST-BUS architecture.
This is a private telephone network with 256
extensions which uses a single MT89L80 as a
speech switch and a second MT89L80 for
communication with the line interface circuits.
Applications
Use in a Simple Digital Switching System
Figs. 7 and 8 show how MT89L80s can be used with
MT8964s to form a simple digital switching system.
STo0
STi0
89L80 used
as
speech
switch
MT89L80
DX
DR
DC
STo0
STi0
89L80 used
in message
mode for
control and
signalling
MT8964
Filter/Codec
Signalling
Logic
Line Driver
and
2- to 4Wire
Converter
Line Interface Circuit with 8964 Filter/Codec
MT89L80
Figure 7 - Example of Typical Interface between 89L80s and 8964s for Simple Digital Switching System
2-9
MT89L80
Advance Information
Line Interface Circuit
with Codec (e.g. 8964)
Line 1
8
Speech
Switch
89L80
STi0-7
8
STo0-7
STo0-7
Controlling
MicroProcessor
8
STi0-7
•
•
•
Repeated for Lines
2 to 255
•
•
•
Repeated for Lines
2 to 255
8
Control &
Signalling
89L80
Line Interface Circuit
with Codec (e.g.8964)
Line 256
Figure 8 - Example Architecture of a Simple Digital Switching System
2-10
MT89L80
Advance Information
Absolute Maximum Ratings*
Parameter
Symbol
1
Supply Voltage
2
Voltage on any I/O pin (except supply pins)
VO
3
Current at Digital Outputs
IO
4
Storage Temperature
TS
5
Package Power Dissipation
PD
Min
Max
Units
-0.3
5.0
V
VSS-0.3
VDD+0.3
V
20
mA
+125
°C
1
W
-55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
.
Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
1
Operating Temperature
TOP
-40
+85
°C
2
Positive Supply
VDD
3.0
3.6
V
3
Input High Voltage
VIH
0.7VDD
VDD
V
4
Input High Voltage on 5V Tolerant Inputs
VIH
5.5
V
5
Input Low Voltage
VIL
0.3VDD
V
VSS
Test Conditions
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1
2
3
4
5
I
N
P
U
T
S
6
7
8
9
10
11
O
U
T
P
U
T
S
Sym
Min
Typ‡
Max
Units
4
7
mA
Supply Current
IDD
Input High Voltage
VIH
Input Low Voltage
VIL
0.3VDD
V
Input Leakage
IIL
5
µA
Input Pin Capacitance
CI
10
pF
0.7VDD
Test Conditions
Outputs unloaded
V
Output High Voltage
VOH
0.8VDD
V
Output High Current
IOH
10
mA
Output Low Voltage
VOL
Output Low Current
IOL
High Impedance Leakage
IOZ
Output Pin Capacitance
CO
0.4
5
V
VI between VSS and VDD
IOH = 10 mA
Sourcing. VOH=2.4V
IOL = 5 mA
mA
Sinking. VOL = 0.4V
5
µA
VO between VSS and VDD
10
pF
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*
AC Electrical Characteristics _Timing Parameter Measurement Voltage Levels
Characteristics
Sym
Level
Units
1
CMOS Threshold Voltage
VTT
0.5VDD
V
2
CMOS Rise/Fall Threshold Voltage high
VHM
0.7VDD
V
3
CMOS Rise/Fall Threshold Voltage low
VLM
0.3VDD
V
Test Conditions
2-11
MT89L80
Advance Information
AC Electrical Characteristics† - Clock Timing (Figures 9 and 10)
Sym
Min
Typ‡
Max
Units
Clock Period*
tCLK
220
244
300
ns
Clock Width High
tCH
85
122
150
ns
Clock Width Low
tCL
85
122
150
ns
Clock Transition Time
tCTT
10
ns
Frame Pulse SetupTime
tFPS
10
190
ns
Frame Pulse Hold Time
tFPH
10
190
ns
Frame Pulse Width
tFPW
Characteristics
1
2
3
4
5
6
I
N
P
U
T
S
7
244
Test Conditions
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.
NB: Frame Pulse is repeated every 512 cycles of C4i.
C4i
F0i
BIT
CELLS
Channel 31
Bit o
Channel 0
Bit 7
Figure 9- Frame Alignment
tCLK
tCL
tCH
tCTT
VHM
C4i
VLM
tCHL
tFPH
F0i
tCTT
tFPH
tFPS
VHM
VLM
tFPW
Figure 10 - Clock Timing
2-12
tFPS
MT89L80
Advance Information
AC Electrical Characteristics† - Serial Streams (Figures 11, 12 and 13)
1
2
3
4
5
6
7
O
U
T
P
U
T
S
I
N
Characteristics
Sym
Min
STo0/7 Delay - Active to High Z
tSAZ
STo0/7 Delay - High Z to Active
Typ‡
Max
Units
Test Conditions
5
55
ns
RL=1 KΩ*, CL=150 pF
tSZA
5
55
ns
CL=150 pF
STo0/7 Delay - Active to Active
tSAA
5
55
ns
CL=150 pF
Output Driver Enable Delay
tOED
50
ns
RL=1 KΩ*, CL=150 pF
External Control Delay
tXCD
55
ns
CL=150 pF
Serial Input Setup Time
tSIS
20
ns
Serial Input Hold Time
tSIH
20
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
Bit Cell Boundary
VHM
C4i
ODE
VHM
VLM
VLM
V
STo0 HM
to
V
STo7 LM
*
STo0 VHM
to
STo7 VLM
*
tOED
*
tOED
tSAZ
STo0 VHM
to
STo7 VLM
Figure 12 - Output Driver Enable
*
tSZA
Bit Cell Boundaries
V
STo0 HM
to
V
STo7 LM
VHM
C4i
VLM
tSAA
tSIH
STi0 VHM
to
STi7 VLM
VHM
CSTo VLM
tSIS
tXCD
Figure 11 - Serial Outputs and External Control
Figure 13 - Serial Inputs
2-13
MT89L80
Advance Information
AC Electrical Characteristics† - Processor Bus (Figures 14)
Characteristics
Sym
Min
Typ‡
Max
Units
1
Chip Select Setup Time
tCSS
0
ns
2
Read/Write Setup Time
tRWS
5
ns
3
Address Setup Time
tADS
5
ns
4
Acknowledgment Delay
Test Conditions
Control Register Read
tAKD
52
120
ns
CL=150 pF
Control Register Write
tAKD
25
65
ns
CL=150 pF
Connection Memory Read
tAKD
62
120
ns
CL=150 pF
Connection Memory Write
tAKD
30
53
ns
CL=150 pF
Data Memory Read
tAKD
560
1220
ns
CL=150 pF
5
Fast Write Data Setup Time
tFWS
6
Slow Write Data Delay
tSWD
7
Read Data Setup Time
tRDS
0
8
Data Hold Time
Read
tDHT
10
Write
tDHT
5
10
50
0
ns
122
90
ns
ns
CL= 150 pF
ns
RL=1 KΩ∗, CL=150 pF
ns
9
Read Data To High Impedance
tRDZ
15
90
10
Chip Select Hold Time
tCSH
0
ns
11
Read/Write Hold Time
tRWH
0
ns
12
Address Hold Time
tADH
8
ns
13
Acknowledgment Hold Time
tAKH
50
80
ns
ns
RL=1 KΩ∗, CL=150 pF
RL=1 KΩ∗, CL=150 pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
DS
VHM
VLM
CS
VHM
VLM
R/W
VHM
VLM
A5
to
A0
tCSS
tCSH
tRWS
tRWH
VHM
VLM
tADS
DTA
VHM
VLM
tADH
tAKD
tAKH
*
*
tRDS
D7
to
D0
VHM
VLM
tDHT
*
*
tSWD
tFWS
Figure 14 - Processor Bus
2-14
tRDZ
Package Outlines
Pin 1
E
A
C
L
H
e
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin
5) A & B Maximum dimensions include allowable mold flash
D
A2
A1
B
20-Pin
24-Pin
28-Pin
48-Pin
Dim
Min
A
A1
0.002
(0.05)
B
0.0087
(0.22)
C
Max
Min
Max
0.079
(2)
-
0.079
(2)
0.002
(0.05)
0.013
(0.33)
0.0087
(0.22)
0.008
(0.21)
Min
Max
Min
Max
0.079
(2)
0.095
(2.41)
0.110
(2.79)
0.008
(0.2)
0.016
(0.406)
0.008
(0.2)
0.0135
(0.342)
0.002
(0.05)
0.013
(0.33)
0.0087
(0.22)
0.008
(0.21)
0.013
(0.33)
0.008
(0.21)
0.010
(0.25)
D
0.27
(6.9)
0.295
(7.5)
0.31
(7.9)
0.33
(8.5)
0.39
(9.9)
0.42
(10.5)
0.62
(15.75)
0.63
(16.00)
E
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.291
(7.39)
0.299
(7.59)
e
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
A2
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.089
(2.26)
0.099
(2.52)
H
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.395
(10.03)
0.42
(10.67)
L
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.02
(0.51)
0.04
(1.02)
Small Shrink Outline Package (SSOP) - N Suffix
General-11
Package Outlines
F
A
G
D1
D2
D
H
E
E1
e: (lead coplanarity)
A1
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) For D & E add for allowable Mold Protrusion 0.010"
I
E2
20-Pin
28-Pin
44-Pin
68-Pin
84-Pin
Dim
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
A
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.180
(4.57)
0.165
(4.20)
0.200
(5.08)
0.165
(4.20)
0.200
(5.08)
A1
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.120
(3.04)
0.090
(2.29)
0.130
(3.30)
0.090
(2.29)
0.130
(3.30)
D/E
0.385
(9.78)
0.395
(10.03)
0.485
(12.32)
0.495
(12.57)
0.685
(17.40)
0.695
(17.65)
0.985
(25.02)
0.995
(25.27)
1.185
(30.10)
1.195
(30.35)
D1/E1
0.350
(8.890)
0.356
0.450
0.456
0.650
0.656
0.950
0.958
1.150
1.158
(9.042) (11.430) (11.582) (16.510) (16.662) (24.130) (24.333) (29.210) (29.413)
D2/E2
0.290
(7.37)
0.330
(8.38)
0.390
(9.91)
0.430
(10.92)
0.590
(14.99)
0.630
(16.00)
0.890
(22.61)
0.930
(23.62)
1.090
(27.69)
1.130
(28.70)
e
0
0.004
0
0.004
0
0.004
0
0.004
0
0.004
F
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
0.026
(0.661)
0.032
(0.812)
G
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
0.013
(0.331)
0.021
(0.533)
H
I
0.050 BSC
(1.27 BSC)
0.020
(0.51)
0.050 BSC
(1.27 BSC)
0.020
(0.51)
0.050 BSC
(1.27 BSC)
0.020
(0.51)
Plastic J-Lead Chip Carrier - P-Suffix
General-10
0.050 BSC
(1.27 BSC)
0.020
(0.51)
0.050 BSC
(1.27 BSC)
0.020
(0.51)
http://www.mitelsemi.com
World Headquarters - Canada
Tel: +1 (613) 592 2122
Fax: +1 (613) 592 6909
North America
Tel: +1 (770) 486 0194
Fax: +1 (770) 631 8213
Asia/Pacific
Tel: +65 333 6193
Fax: +65 333 6192
Europe, Middle East,
and Africa (EMEA)
Tel: +44 (0) 1793 518528
Fax: +44 (0) 1793 518581
Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no
liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of
patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or
service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever.
Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or
other intellectual property rights owned by Mitel.
This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or
contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this
publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific
piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or
data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in
any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel’s
conditions of sale which are available on request.
M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation
Mitel Semiconductor is an ISO 9001 Registered Company
Copyright 1999 MITEL Corporation
All Rights Reserved
Printed in CANADA
TECHNICAL DOCUMENTATION - NOT FOR RESALE