® LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issue Delete Icc1 Spec. Added I Grade Spec. Revised Test Condition of ICC/ISB1/IDR Revised VTERM to VT1 and VT2 Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Added packing type in ORDERING INFORMATION Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 Issue Date Jul.25.2004 Sep.21.2004 Apr.20.2009 ® LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 FEATURES GENERAL DESCRIPTION Fast access time : 8/10/12/15ns Low power consumption: Operating current : 80/75/70/65mA (TYP.) Standby current : 0.6mA (TYP.) Single 3.3V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 2.0V (MIN.) Green package available Package : 32-pin 8mm x 13.4mm STSOP The LY61L1288 is a 1,048,576-bit high speed CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY61L1288 is well designed for high speed system application. Easy expansion is provided by using an active LOW Chip Enable(CE#). The active LOW Write Enable(WE#) controls both writing and reading of the memory. The LY61L1288 operates from a single power supply of 3.3V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family LY61L1288 LY61L1288 LY61L1288(E) LY61L1288(E) LY61L1288(I) LY61L1288(I) Operating Temperature 0 ~ 70℃ 0 ~ 70℃ -20 ~ 80℃ -20 ~ 80℃ -40 ~ 85℃ -40 ~ 85℃ Vcc Range Speed 3.15 ~ 3.6V 3.0 ~ 3.6V 3.15 ~ 3.6V 3.0 ~ 3.6V 3.15 ~ 3.6V 3.0 ~ 3.6V 8/10ns 12/15ns 8/10ns 12/15ns 8/10ns 12/15ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 0.6mA 80/75mA 0.6mA 70/65mA 0.6mA 80/75mA 0.6mA 70/65mA 0.6mA 80/75mA 0.6mA 70/65mA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A16 128Kx8 MEMORY ARRAY DECODER DQ0-DQ7 I/O DATA CIRCUIT CE# WE# OE# CONTROL CIRCUIT SYMBOL DESCRIPTION A0 - A16 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground COLUMN I/O PIN CONFIGURATION A0 A1 A2 A3 CE# DQ0 DQ1 Vcc Vss DQ2 DQ3 WE# A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LY61L1288 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE# DQ7 DQ6 Vss Vcc DQ5 DQ4 A12 A11 A10 A9 A8 STSOP Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 ® LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 Operating Temperature RATING -0.5 to 4.6 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 TA Storage Temperature Power Dissipation DC Output Current TSTG PD IOUT UNIT V V ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# H L L L OE# X H L X WE# X H H L SUPPLY CURRENT ISB,ISB1 ICC ICC ICC I/O OPERATION High-Z High-Z DOUT DIN H = VIH, L = VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Supply Voltage VCC Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage VIH *2 VIL ILI Average Operating Power supply Current Standby Power Supply Current *1 ILO VOH VOL ICC ISB ISB1 TEST CONDITION -8/-10 -12/-15 VCC ≧ VIN ≧ VSS VCC ≧ VOUT ≧ VSS, Output Disabled IOH = -4mA IOL = 8mA -8 -10 -12 -15 CE# = VIH, others at VIH or VIL CE# ≧VCC - 0.2V, Other pins at 0.2V or VCC-0.2V Cycle time = Min. CE# = VIL , II/O = 0mA Other pins at VIH or VIL MIN. 3.15 3.0 2.0 - 0.3 -1 *4 MAX. 3.6 3.6 VCC+0.5 0.8 1 UNIT V V V V µA -1 - 1 µA 2.4 - 80 75 70 65 3 0.4 150 120 100 90 10 V V mA mA mA mA mA - 0.6 3 *5 mA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ 5. 1mA for special request Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 TYP. 3.3 3.3 - ® LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER SYM. LY61L1288 LY61L1288 LY61L1288 LY61L1288 UNIT -8 -10 -12 -15 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Read Cycle Time tRC 8 10 12 15 ns Address Access Time tAA 8 10 12 15 ns Chip Enable Access Time tACE 8 10 12 15 ns Output Enable Access Time tOE 4 5 6 7 ns Chip Enable to Output in Low-Z tCLZ* 2 2 3 4 ns Output Enable to Output in Low-Z tOLZ* 0 0 0 0 ns Chip Disable to Output in High-Z tCHZ* 4 5 6 7 ns Output Disable to Output in High-Z tOHZ* 4 5 6 7 ns Output Hold from Address Change tOH 3 3 3 3 ns (2) WRITE CYCLE PARAMETER SYM. LY61L1288 LY61L1288 LY61L1288 LY61L1288 UNIT -8 -10 -12 -15 MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Write Cycle Time tWC 8 10 12 15 ns Address Valid to End of Write tAW 6.5 8 10 12 ns Chip Enable to End of Write tCW 6.5 8 10 12 ns Address Set-up Time tAS 0 0 0 0 ns Write Pulse Width tWP 6.5 8 9 10 ns Write Recovery Time tWR 0 0 0 0 ns Data to Write Time Overlap tDW 5 6 7 8 ns Data Hold from End of Write Time tDH 0 0 0 0 ns Output Active from End of Write tOW* 1.5 2 3 4 ns Write to Output in High-Z tWHZ* 5 6 7 8 ns *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ® LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 High-Z ® LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW (4) tDH Data Valid Din WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tWP WE# tWHZ Dout High-Z (4) tDW tDH Data Valid Din Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# ≧ VCC - 0.2V VCC = 2.0V IDR CE# ≧ VCC - 0.2V others at 0.2V or VCC - 0.2V See Data Retention tCDR Waveforms (below) tR MIN. 2.0 TYP. - MAX. 3.6 UNIT V - 0.4 2 mA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM VDR ≧ 2.0V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≧ Vcc-0.2V VIH Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 PACKAGE OUTLINE DIMENSION 32 pin 8mm x 13.4mm STSOP Package Outline Dimension HD cL 12° (2x) 16 17 12° (2x) b E e 1 32 "A" Seating Plane D y 12° (2X) 16 17 0.254 A2 c A GAUGE PLANE A1 0 SEATING PLANE "A" DATAIL VIEW 1 32 UNIT SYM. A A1 A2 b c D E e HD L L1 y Θ INCH(BASE) MM(REF) 0.049 (MAX) 0.005 ±0.002 0.039 ±0.002 0.008 ±0.01 0.005 (TYP) 0.465 ±0.004 0.315 ±0.004 0.020 (TYP) 0.528±0.008 0.0197 ±0.004 0.0315 ±0.004 0.003 (MAX) o o 0 ～5 1.25 (MAX) 0.130 ±0.05 1.00 ±0.05 0.20±0.025 0.127 (TYP) 11.80 ±0.10 8.00 ±0.10 0.50 (TYP) 13.40 ±0.20. 0.50 ±0.10 0.8 ±0.10 0.076 (MAX) o o 0 ～5 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 L 12° (2X) L1 ® LY61L1288 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.2 ORDERING INFORMATION LY61L1288 U V - WW Y Z Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0°C ~ 70°C E : (Extended) -20°C ~ +80°C I : (Industrial) -40°C ~ +85°C WW : Access Time(Speed) V : Lead Information L : Lead Free U : Package Type R : 32-pin 8 mm X 13.4 mm STSOP Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 ® LY61L1288 Rev. 1.2 128K X 8 BIT HIGH SPEED CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10