NCP6151/NCP6151A Dual Output 4 Phase +1/0 Phase Controller with single SVID Interface for Desktop and Notebook CPU Applications Features • Meets Intel VR12/IMVP7 Specifications • Current Mode Dual Edge Modulation for Fastest Initial Response to Transient Loading • Dual High Performance Operational Error Amplifier • One Digital Soft Start Ramp for Both Rails • Dynamic Reference Injection® (Patent #US07057381) • Accurate Total Summing Current Amplifier(Patent #US006683441) • DAC with Droop Feed-forward Injection(Patent Pending) • Dual High Impedance Differential Voltage and Total Current Sense Amplifiers • Phase-to-Phase Dynamic Current Balancing • “Lossless” DCR Current Sensing for Current Balancing • Summed Thermally Compensated Inductor Current Sensing for Droop • True Differential Current Balancing Sense Amplifiers for Each Phase • Adaptive Voltage Positioning (AVP) Rev1, 032012 51 47 45 CSREF IOU T CSN4 CSP4 44 42 40 43 41 1 2 TSENSE VR_HOT# 3 SD IO SC LK 5 ALERT# VR_RDY 7 VR_RDYA ENABLE 9 ROSC VCC 11 39 CSN2 37 CSP2 CSN3 35 CSP3 CSN1 33 CSP1 DRVON 31 PWM1/ADDR PWM3 /IMAX 29 PWM2/VBOOT PWM4 38 PIN 1 INDIC ATOR 4 6 36 34 NCP6151 8 32 Top View (not to scale) 10 30 12 PWMA/IMAXA 28 13 27 14 16 18 20 22 25 24 VBOOTA 26 CSPA 23 DROOPA CSCOM PA 21 COMPA ILI MA 19 F BA TRBSTA 17 VSPA 15 CSNA VR MP TSEN SEA 49 46 CSSUMA IOU TA VSP CSSUM 48 DROOP CSCOMP COMP 50 ILIM FB TRBST DIF FOUT VSN 52 VSNA DIFFOU TA The NCP6151/NCP6151A dual output four plus one phase buck solution is optimized for Intel VR12 compatible CPUs. The controller combines true differential voltage sensing, differential inductor DCR current sensing, input voltage feed-forward, and adaptive voltage positioning to provide accurately regulated power for both Desktop and Notebook applications. The control system is based on Dual-Edge pulse-width modulation (PWM) combined with DCR current sensing providing the fastest initial response to dynamic load events and reduced system cost. It also sheds to single phase during light load operation and can auto frequency scale in light load while maintaining excellent transient performance. Dual high performance operational error amplifiers are provided to simplify compensation of the system. Patented Dynamic Reference Injection further simplifies loop compensation by eliminating the need to compromise between closed-loop transient response and Dynamic VID performance. Patented Total Current Summing provides highly accurate current monitoring for droop and digital current monitoring. NCP6151A support coupled inductor operation. It operates with 2 phases versus NCP6151 operating with single phase during PS1 mode. http://onsemi.com QFN52 Dual Row Pin Package Device Package Shipping NCP6151D52MNR2G QFN52 Dual Row NCP6151AD52MNR2G QFN52 Dual Row NCP61510091MNR2G QFN52 Dual Row 2500/Tape & Reel 2500/Tape & Reel 2500/Tape & Reel * Pb-free and Halide-free packages are available • • • • • • • • • Switching Frequency Range of 200KHz – 1.0MHz Startup into Pre-Charged Loads While Avoiding False OVP Power Saving Phase Shedding Vin Feed Forward Ramp Slope Pin Programming for Internal SVID parameters Over Voltage Protection (OVP) & Under Voltage Protection (UVP) Over Current Protection (OCP) Dual Power Good Output with Internal Delays NCP6151A support coupled inductor operation Applications • Desktop & Notebook Processors Page 1 Block Diagram Rev1, 032012 Page 2 NCP6151 QFN52 Dual Row Pin Diagram FLAG / GND (53) NCP6151/NCP6151A QFN52 Dual Row Pin List and Descriptions Pin No. 1 2 3 4 5 6 7 8 9 VSP TSENSE VR_HOT# SDIO SCLK ALERT# VR_RDY VR_RDYA ENABLE 10 ROSC 11 VCC 12 VRMP 13 TSENSEA Symbol Rev1, 032012 Description Non-inverting input to the core differential remote sense amplifier. Temp Sense input for the multiphase converter Thermal logic output for over temperature. Serial VID data interface. Serial VID clock. Serial VID ALERT#. Open drain output. High indicates that the core output is regulating. Open drain output. High indicates that the aux output is regulating. Logic input. Logic high enables both outputs and logic low disables both outputs. A resistance from this pin to ground programs the oscillator frequency. This pin supplies a trimmed output voltage of 2V. Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground. Feed-forward input of Vin for the ramp slope compensation. The current fed into this pin is used to control of the ramp of PWM slope Temp sense for the single phase converter Page 3 14 15 16 17 18 VSPA VSNA DIFFOUTA FBA TRBSTA 19 COMPA 20 ILIMA 21 DROOPA 22 23 24 25 26 27 CSCOMPA CSSUMA IOUTA CSNA CSPA VBOOTA 28 PWMA/IMAXA 29 PWM4 30 PWM2/VBOOT 31 PWM3/IMAX 32 PWM1/ADDR 33 34 35 36 37 38 39 40 41 42 43 44 45 DRON CSP1 CSN1 CSP3 CSN3 CSP2 CSN2 CSP4 CSN4 IOUT CSREF CSSUM CSCOMP 46 DROOP 47 ILIM 48 COMP 49 50 51 52 53 TRBST FB DIFFOUT VSN FLAG / GND Rev1, 032012 Non-inverting input to the aux differential remote sense amplifier Inverting input to the aux differential remote sense amplifier Output of the aux differential remote sense amplifier Error amplifier voltage feedback for aux output Compensation pin for the load transient boost. Output of the aux error amplifier and the inverting input of the PWM comparator for aux output Over current shutdown threshold setting for aux output. A resistor to CSCOMPA sets the threshold. Used to program droop function for aux output. It’s connected to the resistor divider placed between CSCOMPA and CSREFA. Output of total current sense amplifier for aux output Inverting input of total current sense amplifier for aux output Total output current monitor for aux output Inverting input to aux current sense amplifier Non-Inverting input to aux current sense amplifier VBOOTA Voltage input pin. Set to adjust the aux boot-up voltage Aux PWM output to gate driver. During start up it is used to program ICC_MAXA with a resistor to ground Phase 4 PWM output. Pull to VCC to program 3 phase operation. Phase 2 PWM output. VBoot program pin. During start up it is used to program VBOOT with a resistor to ground. Phase 3 PWM output. ICC_MAX Input Pin. During start up it is used to program ICC_MAX with a resistor to ground. Phase 1 PWM output. A resistor to ground on this pin programs the SVID address of the devise. Bidirectional gate drive enable for core output. Non-inverting input to current balance sense amplifier for phase 1 Inverting input to current balance sense amplifier for phase 1 Non-inverting input to current balance sense amplifier for phase 3 Inverting input to current balance sense amplifier for phase 3 Non-inverting input to current balance sense amplifier for phase 2 Inverting input to current balance sense amplifier for phase 2 Non-inverting input to current balance sense amplifier for phase 4 Inverting input to current balance sense amplifier for phase 4 Total output current monitor for core output. Total output current sense amplifier reference voltage input. Inverting input of total current sense amplifier for core output. Output of total current sense amplifier for core output. Used to program droop function for core output. It’s connected to the resistor divider placed between CSCOMP and CSREF summing node. Over current shutdown threshold setting for core output. Resistor to CSCOMP to set threshold. Output of the error amplifier and the inverting inputs of the PWM comparators for the core output. Compensation pin for the load transient boost. Error amplifier voltage feedback for core output Output of the core differential remote sense amplifier. Inverting input to the core differential remote sense amplifier. Power supply return ( QFN Flag ) Page 4 Four Phase Plus One Phase Application Control Circuit Rev1, 032012 Page 5 ABSOLUTE MAXIMUM RATINGS Electrical Information Pin Symbol COMP,COMPA CSCOMP, CSCOMPA VSN DIFFOUT, DIFFOUTA VR_RDY,VR_RDYA VCC ROSC IOUT, IOUTA Output VRMP All Other Pins VMAX VCC+0.3V VCC+0.3V GND+300mV VCC+0.3V VCC+0.3V 6.5V VCC+0.3V 2.0 V +25V VCC+0.3V VMIN -0.3V -0.3V GND–300mV -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3 V *All signals referenced to GND unless noted otherwise. Thermal Information Thermal Characteristic 1) QFN Package Operating Junction Temperature Range2) RθJA TJ °C/W -10 to 125 °C -10 to 100 °C TSTG - 40 to +150 °C MSL 1 Operating Ambient Temperature Range Maximum Storage Temperature Range Moisture Sensitivity Level QFN Package 68 *The maximum package power dissipation must be observed. Notes: 1) JESD 51-5 (1S2P Direct-Attach Method) with 0 LFM 2) JESD 51-7 (1S2P Direct-Attach Method) with 0 LFM Rev1, 032012 Page 6 NCP6151/NCP6151A(4+1) ELECTRICAL CHARACTERISTICS Unless otherwise stated: -10oC<TA<100oC; Vcc=5V; CVCC=0.1μF PARAMETER ERROR AMPLIFIER Input Bias Current Open Loop DC Gain Open Loop Unity Gain Bandwidth Slew Rate Maximum Output Voltage Minimum Output Voltage Differential Summing Amplifier Input Bias Current VSP Input Voltage Range VSN Input Voltage Range -3dB Bandwidth Closed Loop DC gain Droop Accuracy Rev1, 032012 TEST CONDITIONS MIN TYP MAX @ 1.3V CL = 20pF to GND, RL = 10KΩ to GND CL = 20pF to GND, RL = 10KΩ to GND ∆Vin = 100mV, G = -10V/V, ∆Vout = 1.5V – 2.5V, CL = 20pF to GND, DC Load = 10k to GND ISOURCE = 2.0mA ISINK = 2.0mA -400 3.5 - - 1 V V VSP, VSPA ,VSN, VSNA=1.3V -400 -0.3 -0.3 - 400 3.0 0.3 nA V V CL = 20pF to GND, RL = 10KΩ to GND VS+ to VS- = 0.5 to 1.3V CSREF-DROOP=80mV DAC=0.8V to 1.2V -81.5 400 UNITS nA 80 dB 55 MHz 20 V/μs 12 MHz 1.0 V/V -78.5 mV Page 7 ELECTRICAL CHARACTERISTICS: Unless otherwise stated: -10oC<TA<100oC; Vcc=5V; CVCC=0.1μF PARAMETER CURRENT SUMMING AMPLIFIER Offset Voltage (Vos), note 3 Input Bias Current Open Loop Gain Current Sense Unity Gain Bandwidth Maximum CSCOMP (A) Output Voltage Minimum CSCOMP(A) Output Voltage CURRENT BALANCE AMPLIFIER TEST CONDITION MIN CSSUM=CSREF= 1V -300 -7.5 CL = 20pF to GND, RL = 10KΩ to GND Isource = 2mA CSSUM(A)=CSCOMP(A) Isink = 2mA CSSUM(A)=CSCOMP(A) CSP1-4=CSN1-4=1.2V CSPA=CSNA=1.2V Common Mode Input Voltage Range CSPx=CSNx Differential Mode Input Voltage CSNx=1.2V Range CSPx=CSNx =1.2V, Input Offset Voltage Matching Measured from the average Input Bias Current Current Sense Amplifier Gain Rev1, 032012 MAX UNITS 300 7.5 80 uV nA dB 10 MHz 3.5 - - V - - 0.15 V -50 -100 0 - 50 100 2.0 -100 - 100 mV -1.5 - 1.5 mV 5.7 6.0 6.3 V/V 3 % 0V < CSPx-CSNx < 0.1V, Multiphase Current Sense Gain CSN=CSP=10mV to 30mV Matching -3dB Bandwidth INPUT SUPPLY Supply Voltage Range VCC Quiescent Current EN=high EN=low UVLO Threshold VCC rising VCC falling VCC UVLO Hysteresis DAC SLEW RATE Soft Start Slew Rate Slew Rate Slow Slew Rate Fast AUX Soft Start Slew Rate AUX Slew Rate Slow AUX Slew Rate Fast ENABLE INPUT Enable High Input Leakage Current External 1K pull-up to 3.3V Upper Threshold VUPPER Lower Threshold VLOWER Total Hysteresis VUPPER – VLOWER Measure time from Enable Enable Delay Time transitioning HI to when DRON goes high, Vboot is not 0V TYP - -3 nA V 8 4.75 38 MHz 5.25 43 5 4.5 4.1 160 2.5 5 20 2.5 2.5 10 0.8 V mA mA V V mV mv/us mv/us mv/us mv/us mv/us mv/us 1.0 0.3 90 5.0 μA V V mV ms Page 8 ELECTRICAL CHARACTERISTICS: Unless otherwise stated: -10oC<TA<100oC; Vcc=5V; CVCC=0.1μF PARAMETER DRVON Output High Voltage Output Low Voltage Rise/Fall Time Internal Pull Down Resistance IOUT / IOUTA OUTPUT Input Referred Offset Voltage Output Source Current Current Gain TEST CONDITION Sourcing 500uA Sinking 500uA CL (PCB) = 20pF, ∆Vo = 10% to 90% EN = Low TYP MAX UNITS 0.1 V V 3.0 - 10 ns 70 kΩ Ilimit to CSREF Ilimit sink current= 80uA -1.5 (IOUTCURRENT ) / (ILIMITCURRENT), RILIM = 20k, RIOUT = 5.0k , DAC=0.8V,1.25V,1.52V 9.5 10 10.5 200 315 1.95 350 2.00 1000 385 2.05 OSCILLATOR Switching Frequency Range 4 Phase Operation RT=6.98 kΩ Rosc Output Voltage RT=6.98 kΩ OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP) Absolute Over Voltage Threshold CSREF, CSNA During Soft Start Over Voltage Threshold Above DAC VSP(A) rising Over Voltage Delay VSP(A) rising to PWMx low Under Voltage Threshold Below VSP(A) falling DAC-DROOP Under-voltage Delay VR12 DAC 1.0 V ≤ DAC < 1.52 V 0.8V< DAC < 0.995 V System Voltage Accuracy 0.25V < DAC < 0.795 V Droop Feed-Forward Up Current Measured on DROOP, DROOPA Droop Feed-Forward Down current Measured on DROOP, DROOPA Droop Feed-Forward Pulse On-Time OVERCURRENT PROTECTION (CORE RAIL) ILIM Threshold Current (OCP (PS0) Rlim=20k shutdown after 50 us delay) ILIM Threshold Current (immediate (PS0) Rlim=20k OCP shutdown) ILIM Threshold Current (OCP (PS1, PS2, PS3) Rlim=20k, N=number shutdown after 50 us delay) of phases in PS0 mode ILIM Threshold Current (immediate (PS1, PS2, PS3) Rlim=20k, N=number OCP shutdown) of phases in PS0 mode OVERCURRENT PROTECTION (+1 RAIL) ILIM Threshold Current (OCP (PS0) Rlim=20k shutdown after 50 us delay) ILIM Threshold Current (immediate (PS0) Rlim=20k OCP shutdown) ILIM Threshold Current (OCP (PS1, PS2, PS3) Rlim=20k, N=phase shutdown after 50 us delay) number in PS0 mode ILIM Threshold Current (immediate (PS1, PS2, PS3) Rlim=20k, N=phase OCP shutdown) number in PS0 mode Rev1, 032012 MIN 1.5 800 mV uA KHz kHz V 1.9 2.0 2.1 V 150 175 50 200 mV ns 250 300 350 mV 5 -0.5 -5 -8 us 0.5 5 8 % mV mV 72 31 μA uA µs 58 19 65 25 0.16 9.0 10 11.0 μA 13.5 15 16.5 μA 10/N μA 15/N μA 8.5 10 11.5 μA 13.5 15 16.5 μA 10 15 μA μA Page 9 ELECTRICAL CHARACTERISTICS: Unless otherwise stated: --10oC<TA<100oC; Vcc=5V; CVCC=0.1μF PARAMETER TEST CONDITION MODULATORS (PWM COMPARATORS) FOR CORE & AUX COMP voltage when the PWM 0% Duty Cycle outputs remain LO COMP voltage when the PWM 100% Duty Cycle outputs remain HI VRMP=12.0V PWM Ramp Duty Cycle Matching COMP=2V, PWM Ton matching PWM Phase Angle Error Between adjacent phases Ramp Feed-forward Voltage range TRBST TRBST/COMP offset TRBST Starts Sinking Current TRBST Sink Capability TRBSTA TRBSTA/COMPA offset TRBST Starts Sinking Current TRBSTA Sink Capability VR_HOT# Output Low Voltage I_VRHOT = -4mA Output Leakage Current High Impedance State TSENSE/TSENSEA Alert# Assert Threshold Alert# De-assert Threshold VRHOT Assert Threshold VRHOT Rising Threshold TSENSE Bias Current ADC Voltage Range Total Unadjusted Error (TUE) Differential Nonlinearity (DNL) 8-bit Power Supply Sensitivity Conversion Time Round Robin VR_RDY, VR_RDYA (POWER GOOD) OUTPUT Output Low Saturation Voltage IVR_RDY(A) = 4mA, External pull-up of 1KΩ to 3.3V, CTOT = Rise Time 45pF, ∆Vo = 10% to 90% External pull-up of 1KΩ to 3.3V, CTOT = Fall Time 45pF, ∆Vo = 90% to 10% VR_RDY, VR_RDYA pulled up to 5V Output Voltage at Power-up via 2KΩ Output Leakage Current When High VR_RDY & VR_RDYA = 5.0V VR_RDY Delay (rising) DAC=TARGET to VR_RDY VR_RDY Delay (falling) From OCP or OVP PWM Outputs Output High Voltage Sourcing 500uA Output Mid Voltage Output Low Voltage No Load, SetPS=02 Sinking 500uA CL (PCB) = 50pF, ∆Vo = GND to VCC Rise and Fall Time Phase Detection PWM Pin Source Current PWM Pin Threshold Voltage Phase Detect Timer SCLK, SDIO VIL VIH VOH Rev1, 032012 Input Low Voltage Input High Voltage Output High Voltage MIN - TYP MAX UNITS 1.3 - V 2.5 - V 15 20 % deg V 1 -15 5 350 500 mV uA 350 500 mV uA -1.0 - 117.6 513 491 472 494 120 0 -1 0.3 V 1.0 μA 122.4 mV mV mV mV μA 2 +1 1 V % LSB % μs μs 0.3 V +/-1 30 90 - - - 100 ns 10 ns - - 1.0 V -1.0 500 5 1.0 - μA μs μs VCC – 0.2V 1.9 - - - V 2.0 - 2.1 0.7 V V - 10 ns 100 3.3 20 μA V μs .45 .65 1.05 V V V Page 10 ELECTRICAL CHARACTERISTICS: Unless otherwise stated: -10oC<TA<100oC; Vcc=5V; CVCC=0.1μF Parameter RON Test Condition Buffer On Resistance (data line, ALERT#, and VRHOT) Leakage Current Pad Capacitance, note 3 VR clock to data delay (Tco), note 3 Setup time (Tsu), note 3 Hold time (Thld), note 3 MIN MAX Units 4 13 Ω -100 100 μA 4.0 8.3 pF ns ns ns 4 7 14 TYP Notes: 3) Guaranteed by design or characterization data, not in production test; Rev1, 032012 Page 11 Table 2: VR12 VID Codes VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Rev1, 032012 Voltage (V) OFF 0.25000 0.25500 0.26000 0.26500 0.27000 0.27500 0.28000 0.28500 0.29000 0.29500 0.30000 0.30500 0.31000 0.31500 0.32000 0.32500 0.33000 0.33500 0.34000 0.34500 0.35000 0.35500 0.36000 0.36500 0.37000 0.37500 0.38000 0.38500 0.39000 0.39500 0.40000 0.40500 0.41000 0.41500 0.42000 0.42500 0.43000 0.43500 HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 Page 12 Table 2: VR12 VID Codes (cont’d) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Rev1, 032012 Voltage (V) 0.44000 0.44500 0.45000 0.45500 0.46000 0.46500 0.47000 0.47500 0.48000 0.48500 0.49000 0.49500 0.50000 0.50500 0.51000 0.51500 0.52000 0.52500 0.53000 0.53500 0.54000 0.54500 0.55000 0.55500 0.56000 0.56500 0.57000 0.57500 0.58000 0.58500 0.59000 0.59500 0.60000 0.60500 0.61000 0.61500 0.62000 0.62500 0.63000 0.63500 0.64000 0.64500 0.65000 0.65500 0.66000 0.66500 0.67000 0.67500 0.68000 0.68500 HEX 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 Page 13 Table 2: VR12 VID Codes (cont’d) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Rev1, 032012 Voltage (V) 0.69000 0.69500 0.70000 0.70500 0.71000 0.71500 0.72000 0.72500 0.73000 0.73500 0.74000 0.74500 0.75000 0.75500 0.76000 0.76500 0.77000 0.77500 0.78000 0.78500 0.79000 0.79500 0.80000 0.80500 0.81000 0.81500 0.82000 0.82500 0.83000 0.83500 0.84000 0.84500 0.85000 0.85500 0.86000 0.86500 0.87000 0.87500 0.88000 0.88500 0.89000 0.89500 0.90000 0.90500 0.91000 0.91500 0.92000 0.92500 0.93000 0.93500 0.94000 HEX 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B Page 14 Table 2: VR12 VID Codes (cont’d) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Rev1, 032012 Voltage (V) 0.94500 0.95000 0.95500 0.96000 0.96500 0.97000 0.97500 0.98000 0.98500 0.99000 0.99500 1.00000 1.00500 1.01000 1.01500 1.02000 1.02500 1.03000 1.03500 1.04000 1.04500 1.05000 1.05500 1.06000 1.06500 1.07000 1.07500 1.08000 1.08500 1.09000 1.09500 1.10000 1.10500 1.11000 1.11500 1.12000 1.12500 1.13000 1.13500 1.14000 1.14500 HEX 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 Page 15 Table 2: VR12 VID Codes (cont’d) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Rev1, 032012 Voltage (V) 1.15000 1.15500 1.16000 1.16500 1.17000 1.17500 1.18000 1.18500 1.19000 1.19500 1.20000 1.20500 1.21000 1.21500 1.22000 1.22500 1.23000 1.23500 1.24000 1.24500 1.25000 1.25500 1.26000 1.26500 1.27000 1.27500 1.28000 1.28500 1.29000 1.29500 1.30000 1.30500 1.31000 1.31500 1.32000 1.32500 1.33000 1.33500 1.34000 1.34500 1.35000 HEX B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD Page 16 Table 2: VR12 VID Codes (cont’d) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Rev1, 032012 Voltage (V) 1.35500 1.36000 1.36500 1.37000 1.37500 1.38000 1.38500 1.39000 1.39500 1.40000 1.40500 1.41000 1.41500 1.42000 1.42500 1.43000 1.43500 1.44000 1.44500 1.45000 1.45500 1.46000 1.46500 1.47000 1.47500 1.48000 1.48500 1.49000 1.49500 1.50000 1.50500 1.51000 1.51500 1.52000 HEX DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Page 17 Start Up Timing Diagram 12V 5V VR12_EN SVID bus idle SCLK SDIO VSPA VID PKT VSP VID pkt Status PKT VSPA VSP SVID Alert VR_RDYA VR_RDY SVID Timing Diagram CPU Driving, Single Data Rate SCLK CPU send VR latch SDIO TCO_CPU tSU thld TCO_CPU Tco_CPU = clock to data delay in CPU tsu =0.5*T -Tco_CPU thld =0.5*T +Tco_CPU Rev1, 032012 Page 18 State Truth Table STATE POR VR_RDY(A) Pin Error AMP Comp(A) Pin OVP(A) DRVON & UVP(A) PIN N/A N/A N/A Resistive pull down Low Low Disabled Low Low Low Disabled Low Low Low Disabled Resistive pull up Low Operational Active / High 0<VCC<UVLO Disabled Method of Reset EN < threshold UVLO >threshold Start up Delay & Calibration EN> threshold UVLO>threshold DRVON Fault EN> threshold UVLO>threshold Driver must release DRVON to high DRVON<threshold Soft Start EN > threshold No latch UVLO >threshold DRVON > High Normal Operation High Operational EN > threshold Active / High N/A Latching UVLO >threshold DRVON > High Over Voltage Low N/A DAC+150mV High Over Current Low Operational Last DAC Code Low VID Code = 00h Low: if Reg34h:bit0=0; Clamped to 0.9V Disabled High, High:if Reg34h:bit0=1; Rev1, 032012 PWM outputs in mid state Page 19 State Diagram Rev1, 032012 Page 20 General The NCP6151/NCP6151A is a dual output four phase plus one phase dual edge modulated multiphase PWM controller designed to meet the Intel VR12 specifications with a serial SVID control interface. The NCP6151/NCP6151A implements PS0, PS1, PS2 and PS3 power saving states. NCP6151A support coupled inductor operation. It operates with 2 phases versus NCP6151 operating with single phase during PS1 mode. For NCP6151 Core Rail: Power Status PWM Output Operating Mode PS0 Multi-phase PWM interleaving output PS1 Single-phase RPM CCM mode (PWM1 only, PWM2~4 stay in Mid) PS2 Single-phase RPM DCM mode (PWM1 only, PWM2~4 stay in Mid) PS3 Existing definition is same as PS2 For NCP6151A Core Rail: Power Status PWM Output Operating Mode PS0 Multi-phase PWM interleaving output PS1 Two Phase PWM1 & PWM3 PS2 RPM PWM1 with sync diode behavior on PWM3 PS3 Existing definition is same as PS2 For NCP6151/NCP6151A AUX Rail: Power Status PWM Output Operating Mode PS0 Single-phase PWM output PS1 Same as PS0 PS2 Single-phase RPM DCM mode PS3 Existing definition is same as PS2 For NCP6151/NCP6151A, VID code change is supported by SVID interface with three options as below: Option SVID Feature Register Address Command ( Indicating the slew rate of VID code change) Code SetVID_Fast 01h >10mV/us VID code 24h change slew rate SetVID_Slow 02h =1/4 of SetVID_Fast VID 25h code change slew rate SetVID_Decay 03h No control, VID code N/A down Serial VID The NCP6151/NCP6151A supports the Intel serial VID interface. It communicates with the microprocessor through three wires (SCLK, SDIO, ALERT#). The table of supported registers is shown below. Index 00h Name Vendor ID 01h Product ID 02h Product Revision Protocol ID Capability 05h 06h Rev1, 032012 Description Uniquely identifies the VR vendor. The vendor ID assigned by Intel to ON Semiconductor is 0x1Ah Uniquely identifies the VR product. The VR vendor assigns this number. Uniquely identifies the revision or stepping of the VR control IC. The VR vendor assigns this data. Identifies the SVID Protocol the NCP6151 supports Informs the Master of the NCP6151’s Capabilities, 1 = supported, 0 = not supported Bit 7 = Iout_format. Bit 7 = 0 when 1A = 1LSB of Reg 15h. Bit 7 = 1 when Reg 15 FFh = Icc_Max. Default = 1 Access R Default 0x1Ah R 0x51 R 0x0A R R 0x01 0xC7 Page 21 07h 10h Generic ID Status_1 11h 12h Status_2 Temp zone 15h I_out 16h V_out 17h VR_Temp 18h P_out 1Ch Status 2 Last read 21h Icc_Max 22h Temp_Max 24h SR_fast 25h SR_slow 26h Vboot 30h Vout_Max 31h VID setting 32h Pwr State 33h Offset Rev1, 032012 Bit 6 = ADC Measurement of Temp Supported = 1 Bit 5 = ADC Measurement of Pin Supported = 0 Bit 4 = ADC Measurement of Vin Supported = 0 Bit 3 = ADC Measurement of Iin Supported = 0 Bit 2 = ADC Measurement of Pout Supported = 1 Bit 1 = ADC Measurement of Vout Supported = 1 Bit 0 = ADC Measurement of Iout Supported = 1 51h or 31h, depending on the generic Data register read after the ALERT# signal is asserted. Conveying the status of the VR. Data register showing optional status_2 data. Data register showing temperature zones the system is operating in 8 bit binary word ADC of current. This register reads 0xFF when the output current is at Icc_Max 8 bit binary word ADC of output voltage, measured between VSP and VSN. LSB size is 8mV 8 bit binary word ADC of voltage. Binary format in deg C, IE 100C=64h. A value of 00h indicates this function is not supported 8 bit binary word representative of output power. The output voltage is multiplied by the output current value and the result is stored in this register. A value of 00h indicates this function is not supported When the status 2 register is read its contents are copied into this register. The format is the same as the Status 2 Register. Data register containing the Icc_Max the platform supports. The value is measured on the ICCMAX pin on power up and placed in this register. From that point on the register is read only. Data register containing the max temperature the platform supports and the level VR_hot asserts. This value defaults to 100°C and programmable over the SVID Interface Slew Rate for SetVID_fast commands. Binary format in mV/us. Slew Rate for SetVID_slow commands. It is 4X slower than the SR_fast rate. Binary format in mV/us The Vboot is programmed using resistors on the Vboot pin which is sensed on power up. The NCP6151 will ramp to Vboot and hold at Vboot until it receives a new SVID SetVID command to move to a different voltage. Programmed by master and sets the maximum VID the VR will support. If a higher VID code is received, the VR should respond with “not supported” acknowledge. VR 12 VID format. Data register containing currently programmed VID voltage. VID data format. Register containing the current programmed power state. Sets offset in VID steps added to the VID setting for voltage margining. Bit 7 is sign bit, 0=positive margin, 1= negative margin. Remaining 7 BITS are # VID R R 51h or 31h 00h R R 00h 00h R 01h R 01h R 01h R 01h R 00h R 00h R/W 64h R 0Ah R 02h R 00h RW FBh RW 00h RW 00h RW 00h Page 22 steps for margin 2s complement. 00h=no margin 01h=+1 VID step 02h=+2 VID steps FFh=-1 VID step FEh=-2 VID steps. 34h MultiVR Config BOOT VOLTAGE PROGRAMMING The NCP6151/NCP6151A has a Vboot voltage register that can be externally programmed for each output. The VBOOTA also provides a feature that allows the “+1” single phase output to be disabled and effectively removed from the SVID bus. If the single phase output is disabled it alters the SVID address setting table to allow the multi-phase rail to show up at an even or odd address. See the Boot Voltage Table below. Boot Voltage Table Boot Voltage (V) Resistor Value (Ohms) 0 10k 0.9 25k 1.0 45k 1.1 70k 1.2 95k 1.35 125k 1.5 165k Shutdown (VBOOTA only) VBOOTA=VCC ADDRESSING THE NCP6151/NCP6151A The NCP6151/NCP6151A supports 7 possible dual SVID device addresses and 8 possible single device addresses. Pin 32 (PWM1/ADDR) is used to set the SVID address. On power up a 10uA current is sourced from this pin through a resistor connected to this pin and the resulting voltage is measured. The two tables below provide the resistor values for each corresponding SVID address. For dual addressing follow the Dual SVID Address Table. The address value is latched at startup. If VBOOTA is pulled to VCC the aux rail will be removed from the SVID bus, the address will then follow the Single Address SVID table below. Dual SVID Address Table Resistor Main Rail SVID Address Value 10k 0000 25k 0010 45k 0100 70k 0110 95k 1000 125k 1010 165k 1100 Rev1, 032012 Aux Rail SVID Address 0001 0011 0101 0111 1001 1011 1101 Page 23 Single SVID Address Table Resistor Main Rail SVID Address Value (VBOOTA tied to VCC) 10k 22k 36k 51k 68k 91k 120k 160k 220k 0000 0001 0010 0011 0100 0101 0110 0111 1000 Remote Sense Amplifier A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The remote sense amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage to VDIFFOUT = (VVSP − VVSN ) + (1.3V − VDAC ) + (VDROOP − VCSREF ) This signal then goes through a standard error compensation network and into the inverting input of the error amplifier. The non-inverting input of the error amplifier is connected to the same 1.3 V reference used for the differential sense amplifier output bias. High Performance Voltage Error Amplifier A high performance error amplifier is provided for high bandwidth transient performance. A standard type 3 compensation circuit is normally used to compensate the system. Differential Current Feedback Amplifiers Each phase has a low offset differential amplifier to sense that phase current for current balance and per phase OCP protection during soft-start. The inputs to the CSNx and CSPx pins are high impedance inputs. It is recommended that any external filter resistor RCSN not exceed 10kOhm to avoid offset issues with leakage current. It is also recommended that the voltage sense element be no less than 0.5mOhm for accurate current balance. Fine tuning of this time constant is generally not required. Rev1, 032012 Page 24 CSNx CSPx RCSN CCSN SWNx RCSN LPHASE = CCSN ∗ DCR VOUT DCR 1 LPHASE 2 The individual phase current is summed into to the PWM comparator feedback in this way current is balanced is via a current mode control approach. Total Current Sense Amplifier The NCP6151/NCP6151A uses a patented approach to sum the phase currents into a single temperature compensated total current signal. This signal is then used to generate the output voltage droop, total current limit, and the output current monitoring functions. The total current signal is floating with respect to CSREF. The current signal is the difference between CSCOMP and CSREF. The Ref(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground. The amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the inductor series resistance (DCR). Rth is placed near an inductor to sense the temperature of the inductor. This allows the filter time constant and gain to be a function of the Rth NTC resistor and compensate for the change in the DCR with temperature. The DC gain equation for the current sensing: VCSCOMP −CSREF = − Rcs 2 + Rcs1 ∗ Rth Rcs1 + Rth ∗ ( Iout Total ∗ DCR ) Rph Set the gain by adjusting the value of the Rph resistors. The DC gain should set to the output voltage droop. If the voltage from CSCOMP to CSREF is less than 100mV at ICCMAX then it is recommend to increase the gain of the CSCOMP amp and add a resister divider to the Droop pin filter. This is required to provide a good current signal to offset voltage ratio for the ILIMIT pin. When no droop is needed, the gain of the amplifier should be set to provide ~100mV across the current limit programming resistor at full load. The values of Rcs1 and Rcs2 are set based on the 100k NTC and the temperature effect of the inductor and should not need to be changed. The NTC should be placed near the closest inductor. The output voltage droop should be set with the droop filter divider. Rev1, 032012 Page 25 The pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor. This allows the circuit to recover the inductor DCR voltage drop current signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning of the time constant using commonly available values. It is best to fine tune this filter during transient testing. FZ = DCR @ 25C 2 ∗ PI * LPhase FP = 1 ⎛ Rcs1 ∗ Rth @ 25C ⎞ ⎟ ∗ (Ccs1 + Ccs 2 ) 2 * PI * ⎜⎜ Rcs 2 + Rcs1 + Rth @ 25C ⎟⎠ ⎝ Programming the Current Limit The current limit thresholds are programmed with a resistor between the ILIMIT and CSCOMP pins. The ILIMIT pin mirrors the voltage at the CSREF pin and mirrors the sink current internally to IOUT (reduced by the IOUT Current Gain) and the current limit comparators. The 100% current limit trips if the ILIMIT sink current exceeds 10uA for 50us. The 150% current limit trips with minimal delay if the ILIMIT sink current exceeds 15uA. Set the value of the current limit resistor based on the CSCOMP-CSREF voltage as shown below. Rcs 2 + RLIMIT = Rcs1 ∗ Rth Rcs1 + Rth ∗ ( Iout LIMIT ∗ DCR ) VCSCOMP −CSREF @ ILIMIT Rph or R LIMIT = 10u 10u Programming DROOP and DAC Feed-Forward Filter Cdroop CSREF 5 CSSUM 6 + DROOP The signals DROOP and CSREF are differentially summed with the output voltage feedback to add precision voltage droop to the output voltage. The total current feedback should be filtered before it is applied to the DROOP pin. This filter impedance provides DAC feed-forward during dynamic VID changes. Programming this filter can be made simpler if CSCOMP-CSREF is equal to the droop voltage. Rdroop sets the gain of the DAC feed-forward and Cdroop provides the time constant to cancel the time constant of the system per the following equations. Cout is the total output capacitance and Rout is the output impedance of the system. Rdroop 7 CSCOMP - Rdroop = Cout ∗ Rout ∗ 453.6 × 10 6 Rout ∗ Cout Cdroop = Rdroop If the Droop at maximum load is less than 100mV at ICCMAX we recommend altering this filter into a voltage divider such that a larger signal can be provided to the ILIMIT resistor by increasing the CSCOMP amp gain for better current monitor accuracy. The DROOP pin divider gain should be set to provide a voltage from DROOP to Rev1, 032012 Page 26 DROOP CSREF equal to the amount of voltage droop desired in the output. A current is applied to the DROOP pin during dynamic VID. In this case Rdroop1 in parallel with Rdroop2 should be equal to Rdroop Rdroop2 Cdroop CSREF 5 CSSUM 6 Rdroop1 + 7 CSCOMP - Programming IOUT The IOUT pin sources a current equal to the ILIMIT sink current. The voltage on the IOUT pin is monitored by the internal A/D converter and should be scaled with an external resistor to ground such that a load equal to ICCMAX generates a 2V signal on IOUT. A pull-up resistor from 5V VCC can be used to offset the IOUT signal positive if needed. R IOUT = 2.0V * R LIMIT Rcs1 ∗ Rth Rcs 2 + Rcs1 + Rth ∗ ( Iout 10 * ICC _ MAX ∗ DCR ) Rph Programming ICC_MAX and ICC_MAXA The SVID interface provides the platform ICC_MAX value at register 21h for both the multiphase and the single phase rail. A resistor to ground on the IMAX and IMAXA pins program these registers at the time the part in enabled. 10uA is sourced from these pins to generate a voltage on the program resistor. The value of the register is 1A per LSB and is set by the equation below. The resistor value should be no less than 10k. ICC _ MAX 21h = Rev1, 032012 R ∗ 10uA * 256 A 2V Page 27 Programming TSENSE and TSENSEA Two temperature sense inputs are provided. A precision current is sourced out the output of the TSENSE and TSENSEA pins to generate a voltage on the temperature sense network. The voltages on the temperature sense inputs are sampled by the internal A/D converter. A 100k NTC similar to the VISHAY ERT-J1VS104JA should be used. Rcomp1 is mainly used for noise. See the specification table for the thermal sensing voltage thresholds and source current. TSENSE Rcomp1 0.0 Cfilter 0.1uF Rcomp2 8.2K AGND RNTC 100K AGND Precision Oscillator A programmable precision oscillator is provided. The clock oscillator serves as the master clock to the ramp generator circuit. This oscillator is programmed by a resistor to ground on the ROSC pin. The oscillator frequency range is between 200KHz/phase to 1MHz/phase. The ROSC pin provides approximately 2V out and the source current is mirrored into the internal ramp oscillator. The oscillator frequency is approximately proportional to the current flowing in the ROSC resistor. 6.98kOhm × 350kHz = Rosc Fs The oscillator generates triangle ramps that are 0.5~2.5 V in amplitude depending on the VRMP pin voltage to provide input voltage feed forward compensation. The ramps are equally spaced out of phase with respect to each other and the signal phase rail is set half way between phases 1 and 2 of the multi phase rail for minimum input ripple current. Programming the Ramp Feed-Forward Circuit The ramp generator circuit provides the ramp used by the PWM comparators. The ramp generator provides voltage feed-forward control by varying the ramp magnitude with respect to the VRMP pin voltage. The VRMP pin also has a 4V UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin is high impedance input when the controller is disabled. The PWM ramp time is changed according to the following, VRAMPpk= pkPP = 0.1 ∗ VVRMP Rev1, 032012 Page 28 Programming TRBST The TRBST pin provides a signal to offset the output after load release overshoot. This network should be fine tuned during the board tuning process and is only necessary in systems with significant load release overshoot. The TRBST network allows maximum boost for low frequency load release events to minimize load release undershoot. The network time constants are set up to provide a TRBST roll of at higher frequencies where it is not needed. Cboost1*Rbst1 controls the time constant of the load release boost. This should be set to counter the under shoot after load release. Rbst1+ Rbst2 controls the maximum amount of boost during rapid step loading. Rbst2 is generally much larger then Rbst1. The Cboost2*Rbst2 time constant controls the roll off frequency of the TRBST function. Cboost2 FB Rbst1 Rbst3 Rbst2 TRBST Cboost1 PWM Comparators During steady state operation, the duty cycle is centered on the valley of the triangle ramp waveform and both edges of the PWM signal are modulated. During a transient event the duty will increase rapidly and proportionally turning on all phases as the error amp signal increases with respect to the ramps to provide a highly linear and proportional response to the step load. PHASE DETECTION SEQUENCE During start-up, the number of operational phases and their phase relationship is determined by the internal circuitry monitoring the PWM outputs. Normally, NCP6151/NCP6151A operates as a 4-phase VCORE+1-phase VAUX PWM controller. For NCP6151, Connecting PWM4 pin to VCC programs 3-phase operation. Prior to soft start, while ENABLE is high, NCP6151 PWM4 pin sinks approximately 100 µA. An internal comparator checks the voltage of PWM4 pin and compares it to a threshold of hold of 2.5V. If the pin is tied to VCC, its voltage is above the threshold and the controller is configured to three phase operation otherwise the part operates in four phase mode. The Aux rail can be disabled by pulling the VBOOTA signal to VCC. This changes the SVID address scheme to allow the multiphase to be programmed to any SVID Address odd or even. See the register resistor programming table. Rev1, 032012 Page 29 Phase Count Table Number of phases 4+1(NCP6151/NCP6151A) 3+1(NCP6151) 4+0(NCP6151/NCP6151A) 3+0(NCP6151) Resistor Programming PWM4 connected, VbootA programmed PWM4 tied to VCC, VbootA programmed PWM4 connected, VbootA tied to VCC PWM4 tied to VCC, VbootA tied to VCC 3+1 Unused Pin Connection Table Unused Connect Unused Connect to Pin to Pin PWM4 VCC CSN4 GND or CSN4 VCC VCC CSP4 Same CSP4 VCC(optional) as CSN4 4+0 Unused Pin Connection Table Unused Connect Pin to VBOOTA VCC VSPA GND VSNA GND DIFFOUTA float FBA COMPA COMPA FBA TRBSTA float CSPA GND CSNA GND CSCOMPA CSSUMA CSSUMA CSCOMPA DROOPA GND or CSCOMPA ILIMA float IMONA GND TSENSEA GND PWMA float 3+0 Unused Pin Connection Table Unused Pin PWM4 CSN4 Rev1, 032012 Connect to VCC GND or VCC Page 30 CSP4 ILIMA Same as CSN4 VCC GND GND float COMPA FBA float GND GND CSSUMA CSCOMPA GND or CSCOMPA float IMONA GND TSENSEA GND PWMA float VBOOTA VSPA VSNA DIFFOUTA FBA COMPA TRBSTA CSPA CSNA CSCOMPA CSSUMA DROOPA Protection Features Input Under Voltage Protection NCP6151/NCP6151A monitors the 5V VCC supply and the VRMP pin for under voltage protection. The gate driver monitors both the gate driver VCC and the BST voltage (12V drivers only). When the voltage on the gate driver is insufficient it will pull DRVON low and notify the controller the power is not ready. The gate driver will hold DRVON low for a minimum period of time to allow the controller to restart its startup sequence. In this case the PWM is set back to the MID state and soft start would begin again. See the figure below. Gate Driver UVLO Restart Soft Start Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the predetermined slew rate in the spec table. The PWM signals will start out open with a test current to collect data on phase count and for setting internal registers. After the configuration data is collected the controller Rev1, 032012 Page 31 enables and sets the PWM signal to the 2.0V MID state to indicate that the drivers should be in diode mode. DRVON will then be asserted and the COMP pin released to begin soft-start. The DAC will ramp from Zero to the target DAC codes and the PWM outputs will begin to fire. Each phase will move out of the MID state when the first PWM pulse is produced preventing the discharge of a pre-charged output. Soft-Start Sequence Over Current Latch- Off Protection The NCP6151/NCP6151A provides two different types of current limit protection. During normal operation a programmable total current limit is provided that scales with the phase count during power saving operation. This limit is proprammed with a resistor between the CSCOMP and ILIM pins. A second fixed per-phase current limit is provided for safe-start up monitoring during soft-start. The level of total current limit is set with the resistor from the ILIM pin to CSCOMP. The current through the external resistor connected between ILIM and CSCOMP is then compared to the internal current of 10uA and 15uA. If the current into the ILIM pin exceeds the 10A level an internal latch-off counter starts. The controller shuts down if the fault is not removed after 50us. If the current into the pin exceeds 15uA the controller will shut down immediately. To recover from an OCP fault the EN pin must be cycled low. The over-current limit is programmed by a resistor on the ILIM pin. The resistor value can be calculated by the following equation: R ILIM = VCSCOMP − VCSREF 10uA Under Voltage Monitor The output voltage is monitored at the output of the differential amplifier for UVLO. If the output falls more than 300mV below the DAC-DROOP voltage the UVLO comparator will trip sending the VR_RDY signal low. Over Voltage Protection During normal operation the output voltage is monitored at the differential inputs VSP and VSN. If the output voltage exceeds the DAC voltage by approximately 175 mV, PWMs will be forced low until the voltage drops below the OVP threshold after the first OVP trip the DAC will ramp down to zero to avoid a negative output voltage spike during shutdown. When the DAC gets to zero the PWMs will be forced low and the DRVON will remain high. To reset the part the Enable pin must be cycled low. During soft-start, the OVP threshold is set to Rev1, 032012 Page 32 2.0V. This allows the controller to start up without false triggering the OVP. Prior to soft-start the gate drivers will provide OVP protection directly at the switching nodes. OVP Threshold Behavior Layout Notes The NCP6151/NCP6151A has differential voltage and current monitoring. This improves signal integrity and reduces noise issues related to layout for easy design use. To insure proper function there are some general rules to follow. Always place the inductor current sense RC filters as close to the CSN and CSP pins on the controller as possible. Place the VCC decoupling caps as close as possible to the controller VCC pin. The high frequency filter cap on CSREF and the 10 ohm CSREF resistors should be placed close to the controller. The small high feed back cap from COMP to FB should be as close to the controller as possible. Please minimize the capacitance to ground of the FB traces by keeping them short. The filter cap from CSCOMP to CSREF should also be close to the controller. Rev1, 032012 Page 33 Rev1, 032012 Page 34